From 6d87b1572f854435a68f868624f91673c91985e1 Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Wed, 1 Feb 2023 02:55:53 -0700 Subject: [PATCH 01/25] arm64: zynqmp: Add missing ZYNQMP_FIRMWARE dependencies There are missing Kconfig dependencies in the code which is using firmware interface. The commit 71efd45a5fc7 ("arm64: zynqmp: Change firmware dependency") add option to also disable ZYNQMP_FIRMWARE. But not all Kconfig dependencies were properly described and also sdhci and gem drivers didn't protect the code properly. So, add the missing ZYNQMP_FIRMWARE dependencies. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230201095553.11219-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- board/xilinx/zynqmp/Kconfig | 1 + drivers/clk/Kconfig | 4 ++-- drivers/fpga/Kconfig | 2 +- drivers/mmc/zynq_sdhci.c | 4 ++-- drivers/net/zynq_gem.c | 2 +- 5 files changed, 7 insertions(+), 6 deletions(-) diff --git a/board/xilinx/zynqmp/Kconfig b/board/xilinx/zynqmp/Kconfig index 7d1f7398c3e..ffa2f0215d4 100644 --- a/board/xilinx/zynqmp/Kconfig +++ b/board/xilinx/zynqmp/Kconfig @@ -6,6 +6,7 @@ if ARCH_ZYNQMP config CMD_ZYNQMP bool "Enable ZynqMP specific commands" + depends on ZYNQMP_FIRMWARE default y help Enable ZynqMP specific commands like "zynqmp secure" diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 09aa97ee8c0..42280cbf83a 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -185,7 +185,7 @@ config CLK_VERSACLOCK config CLK_VERSAL bool "Enable clock driver support for Versal" depends on (ARCH_VERSAL || ARCH_VERSAL_NET) - select ZYNQMP_FIRMWARE + imply ZYNQMP_FIRMWARE help This clock driver adds support for clock realted settings for Versal platform. @@ -219,7 +219,7 @@ config CLK_ZYNQ config CLK_ZYNQMP bool "Enable clock driver support for ZynqMP" depends on ARCH_ZYNQMP - select ZYNQMP_FIRMWARE + imply ZYNQMP_FIRMWARE help This clock driver adds support for clock realted settings for ZynqMP platform. diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 61490d6d8de..62cb77b098c 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -75,7 +75,7 @@ config FPGA_XILINX config FPGA_ZYNQMPPL bool "Enable Xilinx FPGA driver for ZynqMP" - depends on FPGA_XILINX + depends on FPGA_XILINX && ZYNQMP_FIRMWARE help Enable FPGA driver for loading bitstream in BIT and BIN format on Xilinx Zynq UltraScale+ (ZynqMP) device. diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 91e309d2752..8b559d8a7ab 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -988,7 +988,7 @@ static const struct sdhci_ops arasan_ops = { }; #endif -#if defined(CONFIG_ARCH_ZYNQMP) +#if defined(CONFIG_ARCH_ZYNQMP) && defined(CONFIG_ZYNQMP_FIRMWARE) static int sdhci_zynqmp_set_dynamic_config(struct arasan_sdhci_priv *priv, struct udevice *dev) { @@ -1090,7 +1090,7 @@ static int arasan_sdhci_probe(struct udevice *dev) host = priv->host; -#if defined(CONFIG_ARCH_ZYNQMP) +#if defined(CONFIG_ARCH_ZYNQMP) && defined(CONFIG_ZYNQMP_FIRMWARE) if (device_is_compatible(dev, "xlnx,zynqmp-8.9a")) { ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_SD_CONFIG); diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index cc49788012f..211b2c6e556 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -738,7 +738,7 @@ static int gem_zynqmp_set_dynamic_config(struct udevice *dev) u32 pm_info[2]; int ret; - if (IS_ENABLED(CONFIG_ARCH_ZYNQMP)) { + if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) && IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) { if (!zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_GEM_CONFIG)) { ret = ofnode_read_u32_array(dev_ofnode(dev), From a09d9278a56a49c736636d44c681f6287199023d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 6 Feb 2023 13:50:00 +0100 Subject: [PATCH 02/25] xilinx: dts: Remove cdns,zynq-gem cdns prefix was deprecated and replaced by xlnx one in upstream Linux. Also U-Boot driver has been updated to support new compatible string that's why it is time to remove it and deprecate it. Signed-off-by: Michal Simek --- arch/arm/dts/zynq-7000.dtsi | 4 ++-- arch/arm/dts/zynqmp.dtsi | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 149c6446347..02cf382f066 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -258,7 +258,7 @@ }; gem0: ethernet@e000b000 { - compatible = "xlnx,zynq-gem", "cdns,zynq-gem", "cdns,gem"; + compatible = "xlnx,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; @@ -269,7 +269,7 @@ }; gem1: ethernet@e000c000 { - compatible = "xlnx,zynq-gem", "cdns,zynq-gem", "cdns,gem"; + compatible = "xlnx,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index b74fb3b0ba2..f32469f18ca 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -529,7 +529,7 @@ }; gem0: ethernet@ff0b0000 { - compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem"; + compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; @@ -544,7 +544,7 @@ }; gem1: ethernet@ff0c0000 { - compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem"; + compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; @@ -559,7 +559,7 @@ }; gem2: ethernet@ff0d0000 { - compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem"; + compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; @@ -574,7 +574,7 @@ }; gem3: ethernet@ff0e0000 { - compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem"; + compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; From b4b2f7bb5f9b33d60bafd1f1c8bf2616771fd3de Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 25 Nov 2022 15:41:36 +0100 Subject: [PATCH 03/25] arm64: dts: xilinx: align LED node names with dtschema The node names should be generic and DT schema expects certain pattern: xilinx/zynqmp-zcu100-revC.dtb: leds: 'vbus-det' does not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20221125144136.477171-1-krzysztof.kozlowski@linaro.org Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu100-revC.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index eea703ab67e..742a5398646 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -95,7 +95,7 @@ linux,default-trigger = "bluetooth-power"; }; - vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ + led-vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; From 06ba3c252f60679a28b9ba1c61c81c4c6ced2a87 Mon Sep 17 00:00:00 2001 From: Michael Grzeschik Date: Sun, 23 Oct 2022 23:56:49 +0200 Subject: [PATCH 04/25] arm64: zynqmp: Enable hs termination flag for USB dwc3 controller Since we need to support legacy phys with the dwc3 controller, we enable this quirk on the zynqmp platforms. Signed-off-by: Michael Grzeschik Link: https://lore.kernel.org/r/20221023215649.221726-1-m.grzeschik@pengutronix.de Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index f32469f18ca..2a6b3b2a5c6 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -874,6 +874,7 @@ snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; + snps,resume-hs-terminations; /* dma-coherent; */ }; }; @@ -905,6 +906,7 @@ snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; + snps,resume-hs-terminations; /* dma-coherent; */ }; }; From 5331845db4353bcdf12be50abd4a9cc72261180e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 5 Jan 2023 09:41:22 +0100 Subject: [PATCH 05/25] ARM: zynq: Use recommended dma-controller name instead of dmac Use standard name for dma controller. Issue is reported by dtbs_check as dmac@f8003000: $nodename:0: 'dmac@f8003000' does not match '^dma-controller(@.*)?$' Reviewed-by: Krzysztof Kozlowski Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/5637d7e3464fbc1b2b269a7df35e24edc2c8d4ac.1672908080.git.michal.simek@amd.com --- arch/arm/dts/zynq-7000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 02cf382f066..5ccee8b80b4 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -369,7 +369,7 @@ }; }; - dmac_s: dmac@f8003000 { + dmac_s: dma-controller@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; From 4837ff416d45c8f73552b749561cbe1dac80afb8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 15 Jun 2022 17:53:24 -0700 Subject: [PATCH 06/25] ARM: dts: xilinx: align gpio-key node names with dtschema The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220616005333.18491-31-krzysztof.kozlowski@linaro.org Signed-off-by: Michal Simek --- arch/arm/dts/zynq-zc702.dts | 4 ++-- arch/arm/dts/zynq-zturn-common.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 24ad49ee6af..27fb194fc9e 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -34,14 +34,14 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - sw14 { + switch-14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; - sw13 { + switch-13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ diff --git a/arch/arm/dts/zynq-zturn-common.dtsi b/arch/arm/dts/zynq-zturn-common.dtsi index edba3d86c31..c849c24ed10 100644 --- a/arch/arm/dts/zynq-zturn-common.dtsi +++ b/arch/arm/dts/zynq-zturn-common.dtsi @@ -49,7 +49,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - K1 { + key { label = "K1"; gpios = <&gpio0 0x32 0x1>; linux,code = <0x66>; From 89c3a5151c97b48c0246f33213e160c81717dd34 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Apr 2022 14:18:54 +0200 Subject: [PATCH 07/25] ARM: dts: zynq-7000: drop useless 'dma-channels/requests' properties The pl330 DMA controller provides number of DMA channels and requests through its registers, so duplicating this information (with a chance of mistakes) in DTS is pointless. Additionally the DTS used always wrong property names which causes DT schema check failures - the bindings documented 'dma-channels' and 'dma-requests' properties without leading hash sign. Reported-by: Rob Herring Suggested-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski Acked-by: Michal Simek Link: https://lore.kernel.org/r/20220430121902.59895-2-krzysztof.kozlowski@linaro.org --- arch/arm/dts/zynq-7000.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 5ccee8b80b4..a87f961f2ae 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -381,8 +381,6 @@ <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; From cfa39857dee0fc267dcb07f4b7e39f2a1e40ccdd Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 5 Jan 2023 09:40:32 +0100 Subject: [PATCH 08/25] ARM: zynq: Comment interrupt names IRQs for pl330 pl330 DT yaml description doesn't define interrupt-names property that's why comment it but keep it as comment. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/8e5a921c16efe09030fda036340186c11dd990bf.1672908030.git.michal.simek@amd.com --- arch/arm/dts/zynq-7000.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index a87f961f2ae..97a9e49a19c 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -373,8 +373,10 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; - interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", - "dma4", "dma5", "dma6", "dma7"; + /* + * interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", + * "dma4", "dma5", "dma6", "dma7"; + */ interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, From 749cbcfeacd7063c83506ff5add037cd621fe451 Mon Sep 17 00:00:00 2001 From: Neal Frager Date: Tue, 14 Feb 2023 13:19:59 +0000 Subject: [PATCH 09/25] fpga: zynqmppl: fix fpga loads command for unencrypted use case When using the fpga loads command, the driver is passing the AES encryption key address is all cases. However, for the authenticated, but not encrypted use case, there is no AES encryption key, and this value is 0. When AES encryption is not used on the fpga bitstream, the pmufw assumes that the AES key address is a bitstream size value like what is used by the unsecure fpga load command. To fix the problem, this patch checks to see if the AES key address is zero. If the AES key address is zero, it means that AES is not being used on the bitstream and the bitstream size should be passed instead. Thus, matching the fpga load functionality. Signed-off-by: Neal Frager Acked-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230214131959.40298-1-neal.frager@amd.com Signed-off-by: Michal Simek --- drivers/fpga/zynqmppl.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index d1491da02c3..7b5128fe27a 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -332,10 +332,16 @@ static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize, buf_lo = lower_32_bits((ulong)buf); buf_hi = upper_32_bits((ulong)buf); - ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo, + if ((u32)(uintptr_t)fpga_sec_info->userkey_addr) + ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo, buf_hi, - (u32)(uintptr_t)fpga_sec_info->userkey_addr, - flag, ret_payload); + (u32)(uintptr_t)fpga_sec_info->userkey_addr, + flag, ret_payload); + else + ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo, + buf_hi, (u32)bsize, + flag, ret_payload); + if (ret) puts("PL FPGA LOAD fail\n"); else From 89f0f14fe28a26f7332a5a53878e2f8e0fa57626 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Thu, 16 Feb 2023 15:39:20 +0200 Subject: [PATCH 10/25] arm64: zynqmp: Add an OP-TEE node to the device tree Since the zynqmp boards can run upstream OP-TEE, and having the DT node present doesn't cause any side effects add it in case someone tries to load OP-TEE. Signed-off-by: Ilias Apalodimas Link: https://lore.kernel.org/r/20230216133921.866786-1-ilias.apalodimas@linaro.org Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 2a6b3b2a5c6..6a166381fa7 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -147,6 +147,11 @@ }; firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; #power-domain-cells = <1>; From e2aa078c1c682e535d31bb6227a17d5a50ad8a42 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 15 Feb 2023 09:45:21 +0100 Subject: [PATCH 11/25] cmd: smccc: Print results in hex instead of dec Printing return value in HEX instead of DEC. Return values are 64 bit values which impossible to decode in DEC. For example getting CHIP ID in dec is quite long. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/9a0278a7da729cb69b7a4d46c5e7eb8c3217c635.1676450712.git.michal.simek@amd.com --- cmd/smccc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/smccc.c b/cmd/smccc.c index 0539a42587e..fb80431ad1d 100644 --- a/cmd/smccc.c +++ b/cmd/smccc.c @@ -43,7 +43,7 @@ static int do_call(struct cmd_tbl *cmdtp, int flag, int argc, else arm_smccc_hvc(fid, a1, a2, a3, a4, a5, a6, a7, &res); - printf("Res: %ld %ld %ld %ld\n", res.a0, res.a1, res.a2, res.a3); + printf("Res: 0x%lx 0x%lx 0x%lx 0x%lx\n", res.a0, res.a1, res.a2, res.a3); return 0; } From 5544a5c7c50fc9d2b93285eaa7cc6f4424ac8236 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 15 Feb 2023 09:45:22 +0100 Subject: [PATCH 12/25] xilinx: Enable SMC command for arm64 targets SMC command is very useful for TF-A testing or issuing commands which are not covered by any driver. Strongly recommend to disable this command on any product unless it is required. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/23c77a2cbd083963ca17b84de4108dbb1f28597f.1676450712.git.michal.simek@amd.com --- configs/xilinx_versal_net_virt_defconfig | 1 + configs/xilinx_versal_virt_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 09926435020..edd94633979 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -48,6 +48,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y +CONFIG_CMD_SMC=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_SQUASHFS=y CONFIG_CMD_MTDPARTS=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 169cece4d37..7e38fd41562 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -48,6 +48,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y +CONFIG_CMD_SMC=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_SQUASHFS=y CONFIG_CMD_MTDPARTS=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 4d30f5fdb3d..d29df93f43f 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -92,6 +92,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_GETTIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_REGULATOR=y +CONFIG_CMD_SMC=y CONFIG_CMD_TPM=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_SQUASHFS=y From dd0ebfe8a44421cdcc12ac4e5c3b3625cdf0ed1e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 20 Feb 2023 09:09:04 +0100 Subject: [PATCH 13/25] arm64: zynqmp: Remove comment about gem spec in kv260 The latest SOM specification doesn't enforce certain MIO lines allocated for ethernet or ethernet controller itself. That's why remove comment about it which is likely there from early version of specification. Also removed the same comment from pinctrl node. It is clear that it has to be defined for different carrier cards. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/9406377bf2c391ac0200670511bd6b0edb097c96.1676880543.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 2 +- arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 2 +- arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 4 ++-- arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts index 83c65029c75..c82e1dfac9d 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts @@ -229,7 +229,7 @@ /* gem2/gem3 via PL with phys u79@2 and u80@3 */ -&pinctrl0 { /* required by spec */ +&pinctrl0 { status = "okay"; pinctrl_uart1_default: uart1-default { diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts index f41a2f830ca..9dd160c7a7c 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts @@ -229,7 +229,7 @@ /* gem2/gem3 via PL with phys u79@2 and u80@3 */ -&pinctrl0 { /* required by spec */ +&pinctrl0 { status = "okay"; pinctrl_uart1_default: uart1-default { diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts index 0be5b29c051..6f5a4260656 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts @@ -159,7 +159,7 @@ bus-width = <8>; }; -&gem3 { /* required by spec */ +&gem3 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; @@ -185,7 +185,7 @@ }; }; -&pinctrl0 { /* required by spec */ +&pinctrl0 { status = "okay"; pinctrl_uart1_default: uart1-default { diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts index fca57a6d91e..7764adf1295 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts @@ -146,7 +146,7 @@ bus-width = <8>; }; -&gem3 { /* required by spec */ +&gem3 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; @@ -172,7 +172,7 @@ }; }; -&pinctrl0 { /* required by spec */ +&pinctrl0 { status = "okay"; pinctrl_uart1_default: uart1-default { From 4fffbc1108f3f5e2932cdefea8b5f831b46040c7 Mon Sep 17 00:00:00 2001 From: Jiajie Chen Date: Mon, 27 Feb 2023 23:09:39 +0800 Subject: [PATCH 14/25] spi: xilinx_spi: Fix spi reset It was incorrectly using an old priv->regs pointer, which was initialized to zero. SPI resets won't happen on first call. Signed-off-by: Jiajie Chen Link: https://lore.kernel.org/r/20230227150938.211820-1-c@jia.je Signed-off-by: Michal Simek --- drivers/spi/xilinx_spi.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 4e9115dafee..9e6255a172a 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -112,10 +112,9 @@ struct xilinx_spi_priv { static int xilinx_spi_probe(struct udevice *bus) { struct xilinx_spi_priv *priv = dev_get_priv(bus); - struct xilinx_spi_regs *regs = priv->regs; - - priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus); + struct xilinx_spi_regs *regs; + regs = priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus); priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0); writel(SPISSR_RESET_VALUE, ®s->srr); From 437d77f16bf1a7791d74ec81ca4d669860c8b056 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Thu, 23 Feb 2023 22:07:06 -0700 Subject: [PATCH 15/25] mtd: nand: arasan: Remove hardcoded bbt option Bad block table option is hardcoded to read from flash with NAND_BBT_USE_FLASH option. This decision should be done based on DT property. Remove this hardcoding, to be able to use DT property. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230224050709.30014-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/mtd/nand/raw/arasan_nfc.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c index 4621bfb03e3..ddb4cb1cbae 100644 --- a/drivers/mtd/nand/raw/arasan_nfc.c +++ b/drivers/mtd/nand/raw/arasan_nfc.c @@ -1248,7 +1248,6 @@ static int arasan_probe(struct udevice *dev) /* Buffer read/write routines */ nand_chip->read_buf = arasan_nand_read_buf; nand_chip->write_buf = arasan_nand_write_buf; - nand_chip->bbt_options = NAND_BBT_USE_FLASH; writel(0x0, &info->reg->cmd_reg); writel(0x0, &info->reg->pgm_reg); From 1e01769a2d24863247331205cf08bc504005b593 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Thu, 23 Feb 2023 22:07:07 -0700 Subject: [PATCH 16/25] mtd: nand: arasan: Set ofnode value Ofnode value is not set, so all the DT properties are not being read and due to this default values are being used. Find nand node and set chip->flash_node value. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230224050709.30014-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/mtd/nand/raw/arasan_nfc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c index ddb4cb1cbae..99e2681c14b 100644 --- a/drivers/mtd/nand/raw/arasan_nfc.c +++ b/drivers/mtd/nand/raw/arasan_nfc.c @@ -1230,12 +1230,16 @@ static int arasan_probe(struct udevice *dev) struct nand_drv *info = &arasan->nand_ctrl; struct nand_config *nand = &info->config; struct mtd_info *mtd; + ofnode child; int err = -1; info->reg = (struct nand_regs *)dev_read_addr(dev); mtd = nand_to_mtd(nand_chip); nand_set_controller_data(nand_chip, &arasan->nand_ctrl); + ofnode_for_each_subnode(child, dev_ofnode(dev)) + nand_set_flash_node(nand_chip, child); + #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE nand_chip->options |= NAND_NO_SUBPAGE_WRITE; #endif From 9207c48491fd8a6841dcce8ba3c9b89dda28adec Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Thu, 23 Feb 2023 22:07:08 -0700 Subject: [PATCH 17/25] arm64: dts: zynqmp: Fix nand dt node DC3 nand node is not correct, it is showing all partitions under controller node directly. Create two sub nand nodes with partitions for each. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230224050709.30014-4-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 115 ++++++++++++++--------- 1 file changed, 69 insertions(+), 46 deletions(-) diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index 13812470ae3..8a06c2a90a9 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -128,54 +128,77 @@ arasan,has-mdma; num-cs = <2>; - partition@0 { /* for testing purpose */ - label = "nand-fsbl-uboot"; - reg = <0x0 0x0 0x400000>; - }; - partition@1 { /* for testing purpose */ - label = "nand-linux"; - reg = <0x0 0x400000 0x1400000>; - }; - partition@2 { /* for testing purpose */ - label = "nand-device-tree"; - reg = <0x0 0x1800000 0x400000>; - }; - partition@3 { /* for testing purpose */ - label = "nand-rootfs"; - reg = <0x0 0x1C00000 0x1400000>; - }; - partition@4 { /* for testing purpose */ - label = "nand-bitstream"; - reg = <0x0 0x3000000 0x400000>; - }; - partition@5 { /* for testing purpose */ - label = "nand-misc"; - reg = <0x0 0x3400000 0xFCC00000>; - }; + nand@0 { + reg = <0x0>; + #address-cells = <0x2>; + #size-cells = <0x1>; + nand-ecc-mode = "soft"; + nand-ecc-algo = "bch"; + nand-rb = <0>; + label = "main-storage-0"; + nand-ecc-step-size = <1024>; + nand-ecc-strength = <24>; - partition@6 { /* for testing purpose */ - label = "nand1-fsbl-uboot"; - reg = <0x1 0x0 0x400000>; + partition@0 { /* for testing purpose */ + label = "nand-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand-rootfs"; + reg = <0x0 0x1C00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand-misc"; + reg = <0x0 0x3400000 0xFCC00000>; + }; }; - partition@7 { /* for testing purpose */ - label = "nand1-linux"; - reg = <0x1 0x400000 0x1400000>; - }; - partition@8 { /* for testing purpose */ - label = "nand1-device-tree"; - reg = <0x1 0x1800000 0x400000>; - }; - partition@9 { /* for testing purpose */ - label = "nand1-rootfs"; - reg = <0x1 0x1C00000 0x1400000>; - }; - partition@10 { /* for testing purpose */ - label = "nand1-bitstream"; - reg = <0x1 0x3000000 0x400000>; - }; - partition@11 { /* for testing purpose */ - label = "nand1-misc"; - reg = <0x1 0x3400000 0xFCC00000>; + nand@1 { + reg = <0x1>; + #address-cells = <0x2>; + #size-cells = <0x1>; + nand-ecc-mode = "soft"; + nand-ecc-algo = "bch"; + nand-rb = <0>; + label = "main-storage-1"; + nand-ecc-step-size = <1024>; + nand-ecc-strength = <24>; + + partition@0 { /* for testing purpose */ + label = "nand1-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand1-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand1-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand1-rootfs"; + reg = <0x0 0x1C00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand1-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand1-misc"; + reg = <0x0 0x3400000 0xFCC00000>; + }; }; }; From 9b669ef059180c3041d3d2237bf05d46102997cf Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Thu, 23 Feb 2023 22:07:09 -0700 Subject: [PATCH 18/25] arm64: dts: zynqmp: Enable nand-on-flash-bbt in DT by default By default enable nand-on-flash-bbt DT flag, so that driver always refers to the bad block table(bbt) present on the flash device. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230224050709.30014-5-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 ++ arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 4e6160bcd8b..b6bc2f5be03 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -142,6 +142,7 @@ label = "main-storage-0"; nand-ecc-step-size = <1024>; nand-ecc-strength = <24>; + nand-on-flash-bbt; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; @@ -178,6 +179,7 @@ label = "main-storage-1"; nand-ecc-step-size = <1024>; nand-ecc-strength = <24>; + nand-on-flash-bbt; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index 8a06c2a90a9..6021f8b4e1b 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -138,6 +138,7 @@ label = "main-storage-0"; nand-ecc-step-size = <1024>; nand-ecc-strength = <24>; + nand-on-flash-bbt; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; @@ -174,6 +175,7 @@ label = "main-storage-1"; nand-ecc-step-size = <1024>; nand-ecc-strength = <24>; + nand-on-flash-bbt; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; From cc24fd78593896ba038c71eb356b32fdaa1cd690 Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Wed, 1 Mar 2023 03:33:33 -0700 Subject: [PATCH 19/25] xilinx: zynqmp: Add missing prototype for zynqmp_mmio_write Add missing prototype to fix the sparse warning, warning: no previous prototype for 'zynqmp_mmio_write' [-Wmissing-prototypes]. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230301103334.1455-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- arch/arm/mach-versal-net/include/mach/sys_proto.h | 7 +------ arch/arm/mach-versal/include/mach/sys_proto.h | 6 +----- drivers/mmc/zynq_sdhci.c | 1 + drivers/spi/zynqmp_gqspi.c | 5 +++++ 4 files changed, 8 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-versal-net/include/mach/sys_proto.h b/arch/arm/mach-versal-net/include/mach/sys_proto.h index 5bba9030f2d..a20cf02712b 100644 --- a/arch/arm/mach-versal-net/include/mach/sys_proto.h +++ b/arch/arm/mach-versal-net/include/mach/sys_proto.h @@ -8,9 +8,4 @@ void mem_map_fill(void); -static inline int zynqmp_mmio_write(const u32 address, const u32 mask, - const u32 value) -{ - BUILD_BUG(); - return -EINVAL; -} +int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h index 8e5712e0c9e..3f01508ecb5 100644 --- a/arch/arm/mach-versal/include/mach/sys_proto.h +++ b/arch/arm/mach-versal/include/mach/sys_proto.h @@ -13,8 +13,4 @@ enum { void tcm_init(u8 mode); void mem_map_fill(void); -static inline int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value) -{ - BUILD_BUG(); - return -EINVAL; -} +int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 8b559d8a7ab..9dc310663f2 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -14,6 +14,7 @@ #include "mmc_private.h" #include #include +#include #include #include #include diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 335b458cb90..c4aee279aa4 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -183,6 +183,11 @@ struct zynqmp_qspi_priv { const struct spi_mem_op *op; }; +__weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value) +{ + return 0; +} + static int zynqmp_qspi_of_to_plat(struct udevice *bus) { struct zynqmp_qspi_plat *plat = dev_get_plat(bus); From ebea05e10ea8d838163273ebb4f538febc299cce Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Wed, 1 Mar 2023 03:33:34 -0700 Subject: [PATCH 20/25] spl: Add missing prototype for board_boot_order Add missing prototype to fix the sparse warning, warning: no previous prototype for 'board_boot_order' [-Wmissing-prototypes]. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230301103334.1455-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- include/spl.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/spl.h b/include/spl.h index 827bd25c883..bad12fb01f4 100644 --- a/include/spl.h +++ b/include/spl.h @@ -884,5 +884,6 @@ void spl_perform_fixups(struct spl_image_info *spl_image); */ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size); +void board_boot_order(u32 *spl_boot_list); void spl_save_restore_data(void); #endif From 26c8c1bd12617aab0480d0a559194e4e0631e637 Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Sat, 11 Mar 2023 19:38:34 +0200 Subject: [PATCH 21/25] tools: relocate-rela: adjust le64_to_cpu -> le32_to_cpu in decode_elf32() The sh_addr/sh_offset/sh_size fields in Elf32_Shdr are 32-bits wide, so use le32_to_cpu() instead of the 64-bit variant. Fixes: 5e0e1a86d327 ("tools: relocate-rela: Fix ELF decoding on big-endian hosts") Reviewed-by: Michal Simek Signed-off-by: Ovidiu Panait Link: https://lore.kernel.org/r/20230311173838.521804-1-ovpanait@gmail.com Signed-off-by: Michal Simek --- tools/relocate-rela.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c index 2d2a2ed2772..689e2d46559 100644 --- a/tools/relocate-rela.c +++ b/tools/relocate-rela.c @@ -316,9 +316,9 @@ static int decode_elf32(FILE *felf, char **argv) debug("%s\n", sh_name); - sh_addr = le64_to_cpu(sh_table[i].sh_addr); - sh_offset = le64_to_cpu(sh_table[i].sh_offset); - sh_size = le64_to_cpu(sh_table[i].sh_size); + sh_addr = le32_to_cpu(sh_table[i].sh_addr); + sh_offset = le32_to_cpu(sh_table[i].sh_offset); + sh_size = le32_to_cpu(sh_table[i].sh_size); if (!strcmp(".rela.dyn", sh_name)) { debug("Found section\t\".rela_dyn\"\n"); From 424f04fcd9ab7b2c19521605827e2453dd79c3e2 Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Sat, 11 Mar 2023 19:38:35 +0200 Subject: [PATCH 22/25] tools: relocate-rela: introduce elf16_to_cpu() and elf32_to_cpu() Add elf16_to_cpu() and elf32_to_cpu() functions that allow to read data in both big-endian and little-endian formats. Reviewed-by: Michal Simek Signed-off-by: Ovidiu Panait Link: https://lore.kernel.org/r/20230311173838.521804-2-ovpanait@gmail.com Signed-off-by: Michal Simek --- tools/relocate-rela.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c index 689e2d46559..b27c41b96f8 100644 --- a/tools/relocate-rela.c +++ b/tools/relocate-rela.c @@ -45,6 +45,7 @@ #endif static int ei_class; +static int ei_data; static uint64_t rela_start, rela_end, text_base, dyn_start; @@ -61,6 +62,22 @@ static void debug(const char *fmt, ...) } } +static uint16_t elf16_to_cpu(uint16_t data) +{ + if (ei_data == ELFDATA2LSB) + return le16_to_cpu(data); + + return be16_to_cpu(data); +} + +static uint32_t elf32_to_cpu(uint32_t data) +{ + if (ei_data == ELFDATA2LSB) + return le32_to_cpu(data); + + return be32_to_cpu(data); +} + static bool supported_rela(Elf64_Rela *rela) { uint64_t mask = 0xffffffffULL; /* would be different on 32-bit */ @@ -384,6 +401,9 @@ static int decode_elf(char **argv) ei_class = e_ident[4]; debug("EI_CLASS(1=32bit, 2=64bit) %d\n", ei_class); + ei_data = e_ident[5]; + debug("EI_DATA(1=little endian, 2=big endian) %d\n", ei_data); + if (ei_class == 2) return decode_elf64(felf, argv); From 02d30e5f92d834f020bb7ef6a92ccbf042ed25fc Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Sat, 11 Mar 2023 19:38:36 +0200 Subject: [PATCH 23/25] tools: relocate-rela: add support for handling 32-bit big endian files Currently, a microblaze build with CONFIG_SYS_BIG_ENDIAN=y and CONFIG_STATIC_RELA=y fails with: tools/relocate-rela: Not supported machine type ELF decoding failed make[2]: *** [u-boot/Makefile:1306: u-boot-nodtb.bin] Error 1 To fix this, convert the 32-bit codepath to use the previously added elf{16,32}_to_cpu() functions. The aarch64 codepath is left untouched. This commit ensures that CI doesn't fail for the next patches which enable runtime relocation by default for microblaze. Reviewed-by: Michal Simek Signed-off-by: Ovidiu Panait Link: https://lore.kernel.org/r/20230311173838.521804-3-ovpanait@gmail.com Signed-off-by: Michal Simek --- tools/relocate-rela.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c index b27c41b96f8..fe8cd6bda98 100644 --- a/tools/relocate-rela.c +++ b/tools/relocate-rela.c @@ -251,7 +251,7 @@ static int decode_elf32(FILE *felf, char **argv) return 25; } - machine = le16_to_cpu(header.e_machine); + machine = elf16_to_cpu(header.e_machine); debug("Machine %d\n", machine); if (machine != EM_MICROBLAZE) { @@ -259,10 +259,10 @@ static int decode_elf32(FILE *felf, char **argv) return 30; } - text_base = le32_to_cpu(header.e_entry); - section_header_base = le32_to_cpu(header.e_shoff); - section_header_size = le16_to_cpu(header.e_shentsize) * - le16_to_cpu(header.e_shnum); + text_base = elf32_to_cpu(header.e_entry); + section_header_base = elf32_to_cpu(header.e_shoff); + section_header_size = elf16_to_cpu(header.e_shentsize) * + elf16_to_cpu(header.e_shnum); sh_table = malloc(section_header_size); if (!sh_table) { @@ -290,8 +290,8 @@ static int decode_elf32(FILE *felf, char **argv) return 27; } - sh_index = le16_to_cpu(header.e_shstrndx); - sh_size = le32_to_cpu(sh_table[sh_index].sh_size); + sh_index = elf16_to_cpu(header.e_shstrndx); + sh_size = elf32_to_cpu(sh_table[sh_index].sh_size); debug("e_shstrndx %x, sh_size %lx\n", sh_index, sh_size); sh_str = malloc(sh_size); @@ -306,8 +306,8 @@ static int decode_elf32(FILE *felf, char **argv) * Specifies the byte offset from the beginning of the file * to the first byte in the section. */ - sh_offset = le32_to_cpu(sh_table[sh_index].sh_offset); - sh_num = le16_to_cpu(header.e_shnum); + sh_offset = elf32_to_cpu(sh_table[sh_index].sh_offset); + sh_num = elf16_to_cpu(header.e_shnum); ret = fseek(felf, sh_offset, SEEK_SET); if (ret) { @@ -329,13 +329,13 @@ static int decode_elf32(FILE *felf, char **argv) } for (i = 0; i < sh_num; i++) { - char *sh_name = sh_str + le32_to_cpu(sh_table[i].sh_name); + char *sh_name = sh_str + elf32_to_cpu(sh_table[i].sh_name); debug("%s\n", sh_name); - sh_addr = le32_to_cpu(sh_table[i].sh_addr); - sh_offset = le32_to_cpu(sh_table[i].sh_offset); - sh_size = le32_to_cpu(sh_table[i].sh_size); + sh_addr = elf32_to_cpu(sh_table[i].sh_addr); + sh_offset = elf32_to_cpu(sh_table[i].sh_offset); + sh_size = elf32_to_cpu(sh_table[i].sh_size); if (!strcmp(".rela.dyn", sh_name)) { debug("Found section\t\".rela_dyn\"\n"); @@ -540,9 +540,9 @@ static int rela_elf32(char **argv, FILE *f) PRIu32 " r_addend:\t%" PRIx32 "\n", rela.r_offset, rela.r_info, rela.r_addend); - swrela.r_offset = le32_to_cpu(rela.r_offset); - swrela.r_info = le32_to_cpu(rela.r_info); - swrela.r_addend = le32_to_cpu(rela.r_addend); + swrela.r_offset = elf32_to_cpu(rela.r_offset); + swrela.r_info = elf32_to_cpu(rela.r_info); + swrela.r_addend = elf32_to_cpu(rela.r_addend); debug("SWRela:\toffset:\t%" PRIx32 " r_info:\t%" PRIu32 " r_addend:\t%" PRIx32 "\n", From 3363cf96eb372e03c4ac6774ad1657e4b0449a23 Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Sat, 11 Mar 2023 19:38:37 +0200 Subject: [PATCH 24/25] microblaze: drop CONFIG_NEEDS_MANUAL_RELOC Microblaze and m68k are the only remaining architectures that still enable CONFIG_NEEDS_MANUAL_RELOC by default. Microblaze has had runtime relocation support using CONFIG_STATIC_RELA for quite some time, since commit d58c007498 ("microblaze: Add support for run time relocation"). Drop support for CONFIG_NEEDS_MANUAL_RELOC and make runtime relocation the default, as the rest of the architectures do. Reviewed-by: Michal Simek Signed-off-by: Ovidiu Panait Link: https://lore.kernel.org/r/20230311173838.521804-4-ovpanait@gmail.com Signed-off-by: Michal Simek --- arch/microblaze/Kconfig | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index ce157a79ccc..e38c9f6d711 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -4,19 +4,8 @@ menu "MicroBlaze architecture" config SYS_ARCH default "microblaze" -config NEEDS_MANUAL_RELOC - bool "Disable position-independent pre-relocation code" - default y - help - U-Boot expects to be linked to a specific hard-coded address, and to - be loaded to and run from that address. This option lifts that - restriction, thus allowing the code to be loaded to and executed from - almost any 4K aligned address. This logic relies on the relocation - information that is embedded in the binary to support U-Boot - relocating itself to the top-of-RAM later during execution. - config STATIC_RELA - def_bool y if !NEEDS_MANUAL_RELOC + def_bool y choice prompt "Target select" From 7ac50f88f8a9374e5cb4bc2a88c002d02ef3c570 Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Sat, 11 Mar 2023 19:38:38 +0200 Subject: [PATCH 25/25] microblaze: drop remnants of manual reloc Runtime relocation has been made the default for microblaze, so do the following cleanups: - drop all manual reloc codepaths in start.S - drop all STATIC_RELA ifdefs, as it is now enabled unconditionally in Kconfig Reviewed-by: Michal Simek Signed-off-by: Ovidiu Panait Link: https://lore.kernel.org/r/20230311173838.521804-5-ovpanait@gmail.com Signed-off-by: Michal Simek --- arch/microblaze/config.mk | 4 ---- arch/microblaze/cpu/Makefile | 3 +-- arch/microblaze/cpu/start.S | 28 ---------------------------- 3 files changed, 1 insertion(+), 34 deletions(-) diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk index 467c5ca1b12..64c3f313195 100644 --- a/arch/microblaze/config.mk +++ b/arch/microblaze/config.mk @@ -13,10 +13,6 @@ LDFLAGS_FINAL += --gc-sections ifeq ($(CONFIG_SPL_BUILD),) PLATFORM_CPPFLAGS += -fPIC -endif - -ifeq ($(CONFIG_STATIC_RELA),y) -PLATFORM_CPPFLAGS += -fPIC LDFLAGS_u-boot += -pic endif diff --git a/arch/microblaze/cpu/Makefile b/arch/microblaze/cpu/Makefile index 1c586a7de02..b8c1dcbe14f 100644 --- a/arch/microblaze/cpu/Makefile +++ b/arch/microblaze/cpu/Makefile @@ -5,7 +5,6 @@ extra-y = start.o obj-y = irq.o -obj-y += interrupts.o cache.o exception.o cpuinfo.o -obj-$(CONFIG_STATIC_RELA) += relocate.o +obj-y += interrupts.o cache.o exception.o cpuinfo.o relocate.o obj-$(CONFIG_XILINX_MICROBLAZE0_PVR) += pvr.o obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 7079d9e1704..c1e0fcda0a4 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -10,16 +10,11 @@ #include #include -#if defined(CONFIG_STATIC_RELA) #define SYM_ADDR(reg, reg_add, symbol) \ mfs r20, rpc; \ addik r20, r20, _GLOBAL_OFFSET_TABLE_ + 8; \ lwi reg, r20, symbol@GOT; \ addk reg, reg reg_add; -#else -#define SYM_ADDR(reg, reg_add, symbol) \ - addi reg, reg_add, symbol -#endif .text .global _start @@ -35,7 +30,6 @@ _start: addi r1, r0, CONFIG_SPL_STACK #else add r1, r0, r20 -#if defined(CONFIG_STATIC_RELA) bri 1f /* Force alignment for easier ASM code below */ @@ -67,7 +61,6 @@ uboot_sym_start: brlid r15, mb_fix_rela nop -#endif #endif addi r1, r1, -4 /* Decrement SP to top of memory */ @@ -310,7 +303,6 @@ relocate_code: brlid r15, __setup_exceptions nop -#if defined(CONFIG_STATIC_RELA) /* reloc_offset is current location */ SYM_ADDR(r10, r0, _start) @@ -331,27 +323,7 @@ relocate_code: add r9, r9, r5 brlid r15, mb_fix_rela nop - /* end of code which does relocation */ -#else - /* Check if GOT exist */ - addik r21, r23, _got_start - addik r22, r23, _got_end - cmpu r12, r21, r22 - beqi r12, 2f /* No GOT table - jump over */ - - /* Skip last 3 entries plus 1 because of loop boundary below */ - addik r22, r22, -0x10 - - /* Relocate the GOT. */ -3: lw r12, r21, r0 /* Load entry */ - addk r12, r12, r23 /* Add reloc offset */ - sw r12, r21, r0 /* Save entry back */ - - cmpu r12, r21, r22 /* Check if this cross boundary */ - bneid r12, 3b - addik r21. r21, 4 -#endif /* Flush caches to ensure consistency */ brlid r15, flush_cache_all