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pinctrl: nxp: imx91: Support print pin muxing

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Add support for printing pin names and current mux configuration on i.MX91
when CMD_PINMUX is enabled by adding full pin descriptor table for i.MX91
pads.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan 2026-02-25 09:29:35 +08:00 committed by Fabio Estevam
parent 87cf5b3c89
commit ce4f470eb4
2 changed files with 230 additions and 0 deletions
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2
drivers/pinctrl/nxp/pinctrl-imx9.c
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@ -26,6 +26,8 @@ static const struct udevice_id imx9_pinctrl_match[] = {
#if IS_ENABLED(CONFIG_IMX93)
#include "pinctrl-imx93.c"
#elif IS_ENABLED(CONFIG_IMX91)
#include "pinctrl-imx91.c"
#endif
static int imx9_get_pins_count(struct udevice *dev)

228
drivers/pinctrl/nxp/pinctrl-imx91.c Normal file
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@ -0,0 +1,228 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2026 NXP
*/
#include "pinctrl-imx.h"
enum imx91_pads {
DAP_TDI = 0,
DAP_TMS_SWDIO = 1,
DAP_TCLK_SWCLK = 2,
DAP_TDO_TRACESWO = 3,
GPIO_IO00 = 4,
GPIO_IO01 = 5,
GPIO_IO02 = 6,
GPIO_IO03 = 7,
GPIO_IO04 = 8,
GPIO_IO05 = 9,
GPIO_IO06 = 10,
GPIO_IO07 = 11,
GPIO_IO08 = 12,
GPIO_IO09 = 13,
GPIO_IO10 = 14,
GPIO_IO11 = 15,
GPIO_IO12 = 16,
GPIO_IO13 = 17,
GPIO_IO14 = 18,
GPIO_IO15 = 19,
GPIO_IO16 = 20,
GPIO_IO17 = 21,
GPIO_IO18 = 22,
GPIO_IO19 = 23,
GPIO_IO20 = 24,
GPIO_IO21 = 25,
GPIO_IO22 = 26,
GPIO_IO23 = 27,
GPIO_IO24 = 28,
GPIO_IO25 = 29,
GPIO_IO26 = 30,
GPIO_IO27 = 31,
GPIO_IO28 = 32,
GPIO_IO29 = 33,
CCM_CLKO1 = 34,
CCM_CLKO2 = 35,
CCM_CLKO3 = 36,
CCM_CLKO4 = 37,
ENET1_MDC = 38,
ENET1_MDIO = 39,
ENET1_TD3 = 40,
ENET1_TD2 = 41,
ENET1_TD1 = 42,
ENET1_TD0 = 43,
ENET1_TX_CTL = 44,
ENET1_TXC = 45,
ENET1_RX_CTL = 46,
ENET1_RXC = 47,
ENET1_RD0 = 48,
ENET1_RD1 = 49,
ENET1_RD2 = 50,
ENET1_RD3 = 51,
ENET2_MDC = 52,
ENET2_MDIO = 53,
ENET2_TD3 = 54,
ENET2_TD2 = 55,
ENET2_TD1 = 56,
ENET2_TD0 = 57,
ENET2_TX_CTL = 58,
ENET2_TXC = 59,
ENET2_RX_CTL = 60,
ENET2_RXC = 61,
ENET2_RD0 = 62,
ENET2_RD1 = 63,
ENET2_RD2 = 64,
ENET2_RD3 = 65,
SD1_CLK = 66,
SD1_CMD = 67,
SD1_DATA0 = 68,
SD1_DATA1 = 69,
SD1_DATA2 = 70,
SD1_DATA3 = 71,
SD1_DATA4 = 72,
SD1_DATA5 = 73,
SD1_DATA6 = 74,
SD1_DATA7 = 75,
SD1_STROBE = 76,
SD2_VSELECT = 77,
SD3_CLK = 78,
SD3_CMD = 79,
SD3_DATA0 = 80,
SD3_DATA1 = 81,
SD3_DATA2 = 82,
SD3_DATA3 = 83,
SD2_CD_B = 84,
SD2_CLK = 85,
SD2_CMD = 86,
SD2_DATA0 = 87,
SD2_DATA1 = 88,
SD2_DATA2 = 89,
SD2_DATA3 = 90,
SD2_RESET_B = 91,
I2C1_SCL = 92,
I2C1_SDA = 93,
I2C2_SCL = 94,
I2C2_SDA = 95,
UART1_RXD = 96,
UART1_TXD = 97,
UART2_RXD = 98,
UART2_TXD = 99,
PDM_CLK = 100,
PDM_BIT_STREAM0 = 101,
PDM_BIT_STREAM1 = 102,
SAI1_TXFS = 103,
SAI1_TXC = 104,
SAI1_TXD0 = 105,
SAI1_RXD0 = 106,
WDOG_ANY = 107,
};
static const struct imx_pinctrl_pin_desc imx9_pinctrl_pads[] = {
IMX_PINCTRL_PIN(DAP_TDI),
IMX_PINCTRL_PIN(DAP_TMS_SWDIO),
IMX_PINCTRL_PIN(DAP_TCLK_SWCLK),
IMX_PINCTRL_PIN(DAP_TDO_TRACESWO),
IMX_PINCTRL_PIN(GPIO_IO00),
IMX_PINCTRL_PIN(GPIO_IO01),
IMX_PINCTRL_PIN(GPIO_IO02),
IMX_PINCTRL_PIN(GPIO_IO03),
IMX_PINCTRL_PIN(GPIO_IO04),
IMX_PINCTRL_PIN(GPIO_IO05),
IMX_PINCTRL_PIN(GPIO_IO06),
IMX_PINCTRL_PIN(GPIO_IO07),
IMX_PINCTRL_PIN(GPIO_IO08),
IMX_PINCTRL_PIN(GPIO_IO09),
IMX_PINCTRL_PIN(GPIO_IO10),
IMX_PINCTRL_PIN(GPIO_IO11),
IMX_PINCTRL_PIN(GPIO_IO12),
IMX_PINCTRL_PIN(GPIO_IO13),
IMX_PINCTRL_PIN(GPIO_IO14),
IMX_PINCTRL_PIN(GPIO_IO15),
IMX_PINCTRL_PIN(GPIO_IO16),
IMX_PINCTRL_PIN(GPIO_IO17),
IMX_PINCTRL_PIN(GPIO_IO18),
IMX_PINCTRL_PIN(GPIO_IO19),
IMX_PINCTRL_PIN(GPIO_IO20),
IMX_PINCTRL_PIN(GPIO_IO21),
IMX_PINCTRL_PIN(GPIO_IO22),
IMX_PINCTRL_PIN(GPIO_IO23),
IMX_PINCTRL_PIN(GPIO_IO24),
IMX_PINCTRL_PIN(GPIO_IO25),
IMX_PINCTRL_PIN(GPIO_IO26),
IMX_PINCTRL_PIN(GPIO_IO27),
IMX_PINCTRL_PIN(GPIO_IO28),
IMX_PINCTRL_PIN(GPIO_IO29),
IMX_PINCTRL_PIN(CCM_CLKO1),
IMX_PINCTRL_PIN(CCM_CLKO2),
IMX_PINCTRL_PIN(CCM_CLKO3),
IMX_PINCTRL_PIN(CCM_CLKO4),
IMX_PINCTRL_PIN(ENET1_MDC),
IMX_PINCTRL_PIN(ENET1_MDIO),
IMX_PINCTRL_PIN(ENET1_TD3),
IMX_PINCTRL_PIN(ENET1_TD2),
IMX_PINCTRL_PIN(ENET1_TD1),
IMX_PINCTRL_PIN(ENET1_TD0),
IMX_PINCTRL_PIN(ENET1_TX_CTL),
IMX_PINCTRL_PIN(ENET1_TXC),
IMX_PINCTRL_PIN(ENET1_RX_CTL),
IMX_PINCTRL_PIN(ENET1_RXC),
IMX_PINCTRL_PIN(ENET1_RD0),
IMX_PINCTRL_PIN(ENET1_RD1),
IMX_PINCTRL_PIN(ENET1_RD2),
IMX_PINCTRL_PIN(ENET1_RD3),
IMX_PINCTRL_PIN(ENET2_MDC),
IMX_PINCTRL_PIN(ENET2_MDIO),
IMX_PINCTRL_PIN(ENET2_TD3),
IMX_PINCTRL_PIN(ENET2_TD2),
IMX_PINCTRL_PIN(ENET2_TD1),
IMX_PINCTRL_PIN(ENET2_TD0),
IMX_PINCTRL_PIN(ENET2_TX_CTL),
IMX_PINCTRL_PIN(ENET2_TXC),
IMX_PINCTRL_PIN(ENET2_RX_CTL),
IMX_PINCTRL_PIN(ENET2_RXC),
IMX_PINCTRL_PIN(ENET2_RD0),
IMX_PINCTRL_PIN(ENET2_RD1),
IMX_PINCTRL_PIN(ENET2_RD2),
IMX_PINCTRL_PIN(ENET2_RD3),
IMX_PINCTRL_PIN(SD1_CLK),
IMX_PINCTRL_PIN(SD1_CMD),
IMX_PINCTRL_PIN(SD1_DATA0),
IMX_PINCTRL_PIN(SD1_DATA1),
IMX_PINCTRL_PIN(SD1_DATA2),
IMX_PINCTRL_PIN(SD1_DATA3),
IMX_PINCTRL_PIN(SD1_DATA4),
IMX_PINCTRL_PIN(SD1_DATA5),
IMX_PINCTRL_PIN(SD1_DATA6),
IMX_PINCTRL_PIN(SD1_DATA7),
IMX_PINCTRL_PIN(SD1_STROBE),
IMX_PINCTRL_PIN(SD2_VSELECT),
IMX_PINCTRL_PIN(SD3_CLK),
IMX_PINCTRL_PIN(SD3_CMD),
IMX_PINCTRL_PIN(SD3_DATA0),
IMX_PINCTRL_PIN(SD3_DATA1),
IMX_PINCTRL_PIN(SD3_DATA2),
IMX_PINCTRL_PIN(SD3_DATA3),
IMX_PINCTRL_PIN(SD2_CD_B),
IMX_PINCTRL_PIN(SD2_CLK),
IMX_PINCTRL_PIN(SD2_CMD),
IMX_PINCTRL_PIN(SD2_DATA0),
IMX_PINCTRL_PIN(SD2_DATA1),
IMX_PINCTRL_PIN(SD2_DATA2),
IMX_PINCTRL_PIN(SD2_DATA3),
IMX_PINCTRL_PIN(SD2_RESET_B),
IMX_PINCTRL_PIN(I2C1_SCL),
IMX_PINCTRL_PIN(I2C1_SDA),
IMX_PINCTRL_PIN(I2C2_SCL),
IMX_PINCTRL_PIN(I2C2_SDA),
IMX_PINCTRL_PIN(UART1_RXD),
IMX_PINCTRL_PIN(UART1_TXD),
IMX_PINCTRL_PIN(UART2_RXD),
IMX_PINCTRL_PIN(UART2_TXD),
IMX_PINCTRL_PIN(PDM_CLK),
IMX_PINCTRL_PIN(PDM_BIT_STREAM0),
IMX_PINCTRL_PIN(PDM_BIT_STREAM1),
IMX_PINCTRL_PIN(SAI1_TXFS),
IMX_PINCTRL_PIN(SAI1_TXC),
IMX_PINCTRL_PIN(SAI1_TXD0),
IMX_PINCTRL_PIN(SAI1_RXD0),
IMX_PINCTRL_PIN(WDOG_ANY),
};