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timer: fttmr010_timer: Remove unused driver

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This driver is unused. Remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2025-08-06 08:55:02 -06:00
parent 2a61c56dea
commit cb76b20839
4 changed files with 0 additions and 160 deletions
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7
drivers/timer/Kconfig
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@ -166,13 +166,6 @@ config DESIGNWARE_APB_TIMER
Enables support for the Designware APB Timer driver. This timer is Enables support for the Designware APB Timer driver. This timer is
present on Altera SoCFPGA SoCs. present on Altera SoCFPGA SoCs.
config FTTMR010_TIMER
bool "Faraday Technology timer support"
depends on TIMER
help
Select this to enable support for the timer found on
devices using Faraday Technology's IP.
config GXP_TIMER config GXP_TIMER
bool "HPE GXP Timer" bool "HPE GXP Timer"
depends on TIMER depends on TIMER

1
drivers/timer/Makefile
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@ -15,7 +15,6 @@ obj-$(CONFIG_$(PHASE_)ATMEL_PIT_TIMER) += atmel_pit_timer.o
obj-$(CONFIG_$(PHASE_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o obj-$(CONFIG_$(PHASE_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o
obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
obj-$(CONFIG_FTTMR010_TIMER) += fttmr010_timer.o
obj-$(CONFIG_GXP_TIMER) += gxp-timer.o obj-$(CONFIG_GXP_TIMER) += gxp-timer.o
obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
obj-$(CONFIG_NOMADIK_MTU_TIMER) += nomadik-mtu-timer.o obj-$(CONFIG_NOMADIK_MTU_TIMER) += nomadik-mtu-timer.o

91
drivers/timer/fttmr010_timer.c
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@ -1,91 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* 23/08/2022 Port to DM
*/
#include <dm.h>
#include <log.h>
#include <timer.h>
#include <asm/io.h>
#include <dm/ofnode.h>
#include <faraday/fttmr010.h>
#include <asm/global_data.h>
#define TIMER_LOAD_VAL 0xffffffff
struct fttmr010_timer_priv {
struct fttmr010 __iomem *regs;
};
static u64 fttmr010_timer_get_count(struct udevice *dev)
{
struct fttmr010_timer_priv *priv = dev_get_priv(dev);
struct fttmr010 *tmr = priv->regs;
u32 now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);
/* increment tbu if tbl has rolled over */
if (now < gd->arch.tbl)
gd->arch.tbu++;
gd->arch.tbl = now;
return ((u64)gd->arch.tbu << 32) | gd->arch.tbl;
}
static int fttmr010_timer_probe(struct udevice *dev)
{
struct fttmr010_timer_priv *priv = dev_get_priv(dev);
struct fttmr010 *tmr;
unsigned int cr;
priv->regs = dev_read_addr_ptr(dev);
if (!priv->regs)
return -EINVAL;
tmr = priv->regs;
debug("Faraday FTTMR010 timer revision 0x%08X\n", readl(&tmr->revision));
/* disable timers */
writel(0, &tmr->cr);
/* setup timer */
writel(TIMER_LOAD_VAL, &tmr->timer3_load);
writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
writel(0, &tmr->timer3_match1);
writel(0, &tmr->timer3_match2);
/* we don't want timer to issue interrupts */
writel(FTTMR010_TM3_MATCH1 |
FTTMR010_TM3_MATCH2 |
FTTMR010_TM3_OVERFLOW,
&tmr->interrupt_mask);
cr = readl(&tmr->cr);
cr |= FTTMR010_TM3_CLOCK; /* use external clock */
cr |= FTTMR010_TM3_ENABLE;
writel(cr, &tmr->cr);
gd->arch.tbl = 0;
gd->arch.tbu = 0;
return 0;
}
static const struct timer_ops fttmr010_timer_ops = {
.get_count = fttmr010_timer_get_count,
};
static const struct udevice_id fttmr010_timer_ids[] = {
{ .compatible = "faraday,fttmr010-timer" },
{}
};
U_BOOT_DRIVER(fttmr010_timer) = {
.name = "fttmr010_timer",
.id = UCLASS_TIMER,
.of_match = fttmr010_timer_ids,
.priv_auto = sizeof(struct fttmr010_timer_priv),
.probe = fttmr010_timer_probe,
.ops = &fttmr010_timer_ops,
};

61
include/faraday/fttmr010.h
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@ -1,61 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*/
/*
* Timer
*/
#ifndef __FTTMR010_H
#define __FTTMR010_H
struct fttmr010 {
unsigned int timer1_counter; /* 0x00 */
unsigned int timer1_load; /* 0x04 */
unsigned int timer1_match1; /* 0x08 */
unsigned int timer1_match2; /* 0x0c */
unsigned int timer2_counter; /* 0x10 */
unsigned int timer2_load; /* 0x14 */
unsigned int timer2_match1; /* 0x18 */
unsigned int timer2_match2; /* 0x1c */
unsigned int timer3_counter; /* 0x20 */
unsigned int timer3_load; /* 0x24 */
unsigned int timer3_match1; /* 0x28 */
unsigned int timer3_match2; /* 0x2c */
unsigned int cr; /* 0x30 */
unsigned int interrupt_state; /* 0x34 */
unsigned int interrupt_mask; /* 0x38 */
unsigned int revision; /* 0x3c */
};
/*
* Timer Control Register
*/
#define FTTMR010_TM3_UPDOWN (1 << 11)
#define FTTMR010_TM2_UPDOWN (1 << 10)
#define FTTMR010_TM1_UPDOWN (1 << 9)
#define FTTMR010_TM3_OFENABLE (1 << 8)
#define FTTMR010_TM3_CLOCK (1 << 7)
#define FTTMR010_TM3_ENABLE (1 << 6)
#define FTTMR010_TM2_OFENABLE (1 << 5)
#define FTTMR010_TM2_CLOCK (1 << 4)
#define FTTMR010_TM2_ENABLE (1 << 3)
#define FTTMR010_TM1_OFENABLE (1 << 2)
#define FTTMR010_TM1_CLOCK (1 << 1)
#define FTTMR010_TM1_ENABLE (1 << 0)
/*
* Timer Interrupt State & Mask Registers
*/
#define FTTMR010_TM3_OVERFLOW (1 << 8)
#define FTTMR010_TM3_MATCH2 (1 << 7)
#define FTTMR010_TM3_MATCH1 (1 << 6)
#define FTTMR010_TM2_OVERFLOW (1 << 5)
#define FTTMR010_TM2_MATCH2 (1 << 4)
#define FTTMR010_TM2_MATCH1 (1 << 3)
#define FTTMR010_TM1_OVERFLOW (1 << 2)
#define FTTMR010_TM1_MATCH2 (1 << 1)
#define FTTMR010_TM1_MATCH1 (1 << 0)
#endif /* __FTTMR010_H */