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sunxi: change SUNXI_HIGH_SRAM option to SUNXI_SRAM_ADDRESS

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The new Allwinner H6 SoC has its SRAM A1 at neither 0x0 nor 0x10000, but
it's at 0x20000. Thus the SUNXI_HIGH_SRAM option needs to be refactored
to support this new configuration.

Change it to SUNXI_SRAM_ADDRESS, which holds the real address of SRAM
A1 in the memory map.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Icenowy Zheng 2018-07-21 16:20:20 +08:00 committed by Jagan Teki
parent dddc4b4af3
commit cadc7c20e5
3 changed files with 17 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/include/asm/arch-sunxi/spl.h
View File

@ -11,11 +11,7 @@
#define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */ #define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */
#define SPL_HEADER_VERSION 2 #define SPL_HEADER_VERSION 2
#ifdef CONFIG_SUNXI_HIGH_SRAM #define SPL_ADDR CONFIG_SUNXI_SRAM_ADDRESS
#define SPL_ADDR 0x10000
#else
#define SPL_ADDR 0x0
#endif
/* The low 8-bits of the 'boot_media' field in the SPL header */ /* The low 8-bits of the 'boot_media' field in the SPL header */
#define SUNXI_BOOTED_FROM_MMC0 0 #define SUNXI_BOOTED_FROM_MMC0 0

14
arch/arm/mach-sunxi/Kconfig
View File

@ -73,16 +73,15 @@ config SUN8I_RSB
with various RSB based devices, such as AXP223, AXP8XX PMICs, with various RSB based devices, such as AXP223, AXP8XX PMICs,
and AC100/AC200 ICs. and AC100/AC200 ICs.
config SUNXI_HIGH_SRAM config SUNXI_SRAM_ADDRESS
bool hex
default n default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
default 0x0
---help--- ---help---
Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
with the first SRAM region being located at address 0. with the first SRAM region being located at address 0.
Some newer SoCs map the boot ROM at address 0 instead and move the Some newer SoCs map the boot ROM at address 0 instead and move the
SRAM to 64KB, just behind the mask ROM. SRAM to a different address.
Chips using the latter setup are supposed to select this option to
adjust the addresses accordingly.
config SUNXI_A64_TIMER_ERRATUM config SUNXI_A64_TIMER_ERRATUM
bool bool
@ -257,7 +256,6 @@ config MACH_SUN9I
select CPU_V7A select CPU_V7A
select DRAM_SUN9I select DRAM_SUN9I
select SUN6I_PRCM select SUN6I_PRCM
select SUNXI_HIGH_SRAM
select SUNXI_GEN_SUN6I select SUNXI_GEN_SUN6I
select SUN8I_RSB select SUN8I_RSB
select SUPPORT_SPL select SUPPORT_SPL
@ -269,7 +267,6 @@ config MACH_SUN50I
select PHY_SUN4I_USB select PHY_SUN4I_USB
select SUNXI_DE2 select SUNXI_DE2
select SUNXI_GEN_SUN6I select SUNXI_GEN_SUN6I
select SUNXI_HIGH_SRAM
select SUPPORT_SPL select SUPPORT_SPL
select SUNXI_DRAM_DW select SUNXI_DRAM_DW
select SUNXI_DRAM_DW_32BIT select SUNXI_DRAM_DW_32BIT
@ -281,7 +278,6 @@ config MACH_SUN50I_H5
bool "sun50i (Allwinner H5)" bool "sun50i (Allwinner H5)"
select ARM64 select ARM64
select MACH_SUNXI_H3_H5 select MACH_SUNXI_H3_H5
select SUNXI_HIGH_SRAM
select FIT select FIT
select SPL_LOAD_FIT select SPL_LOAD_FIT

17
include/configs/sunxi-common.h
View File

@ -82,20 +82,19 @@
#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */ #define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */
#ifdef CONFIG_SUNXI_HIGH_SRAM
/* /*
* The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is
* slightly bigger. Note that it is possible to map the first 32 KiB of the * slightly bigger. Note that it is possible to map the first 32 KiB of the
* A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the
* undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and
* the 1 actually activates the mapping of the first 32 KiB to 0x00000000. * the 1 actually activates the mapping of the first 32 KiB to 0x00000000.
* A64 and H5 also has SRAM A1 at 0x00010000, but no magic remap register
* is known yet.
* H6 has SRAM A1 at 0x00020000.
*/ */
#define CONFIG_SYS_INIT_RAM_ADDR 0x10000 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS
#define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */ /* FIXME: this may be larger on some SoCs */
#else
#define CONFIG_SYS_INIT_RAM_ADDR 0x0
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
#endif
#define CONFIG_SYS_INIT_SP_OFFSET \ #define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
@ -184,7 +183,11 @@
#define CONFIG_SPL_BOARD_LOAD_IMAGE #define CONFIG_SPL_BOARD_LOAD_IMAGE
#endif #endif
#ifdef CONFIG_SUNXI_HIGH_SRAM /*
* We cannot use expressions here, because expressions won't be evaluated in
* autoconf.mk.
*/
#if CONFIG_SUNXI_SRAM_ADDRESS == 0x10000
#define CONFIG_SPL_TEXT_BASE 0x10060 /* sram start+header */ #define CONFIG_SPL_TEXT_BASE 0x10060 /* sram start+header */
#define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */ #define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */
#ifdef CONFIG_ARM64 #ifdef CONFIG_ARM64