sysreset: socfpga: soc64: Enable L2 reset

Put all slave CPUs (CPU1-3) into WFI mode. Master CPU (CPU0) writes
the magic word into system manager's scratch register to indicate
the system has performed L2 reset and request reset manager to
perform hardware handshake and then trigger L2 reset. CPU0 put
itself into WFI mode. L2 reset will reboot all HPS CPU cores after
which all HPS cores are in WFI mode. L2 reset is followed by warm
reset request by SPL via RMR_EL3 system register.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>

arch/arm/Kconfig

@@ -1173,7 +1173,7 @@ config ARCH_SOCFPGA
 	select SYSRESET
 	select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \
-	  TARGET_SOCFPGA_SOC64
+           TARGET_SOCFPGA_SOC64
 	select SYSRESET_PSCI if TARGET_SOCFPGA_AGILEX5
 	imply CMD_DM
 	imply CMD_MTDPARTS

drivers/sysreset/sysreset_socfpga_soc64.c

@@ -1,19 +1,78 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2019 Pepperl+Fuchs
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  * Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
  */
 
+#include <command.h>
+#include <cpu_func.h>
 #include <dm.h>
 #include <errno.h>
 #include <sysreset.h>
 #include <asm/arch/mailbox_s10.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/secure.h>
+
+#define GICD_CTRL_ADDRESS	0xfffc1000
+
+static __always_inline void __l2_reset_cpu(void)
+{
+	asm volatile(/* Disable GIC distributor (IRQs). */
+		"str    wzr, [%3]\n"
+		/* Set Magic Number */
+		"str	%0, [%1]\n"
+		/* Increase timeout in rstmgr.hdsktimeout */
+		"ldr	x2, =0xFFFFFF\n"
+		"str	w2, [%2, #0x64]\n"
+		"ldr	w2, [%2, #0x10]\n"
+		/*
+		 * Set l2flushen = 1, etrstallen = 1,
+		 * fpgahsen = 1 and sdrselfrefen = 1
+		 * in rstmgr.hdsken to perform handshake
+		 * in certain peripherals before trigger
+		 * L2 reset.
+		 */
+		"ldr	x3, =0x10D\n"
+		"orr	x2, x2, x3\n"
+		"str	w2, [%2, #0x10]\n"
+		/* Trigger L2 reset in rstmgr.coldmodrst */
+		"ldr	w2, [%2, #0x34]\n"
+		"orr	x2, x2, #0x100\n"
+		"isb\n"
+		"dsb	sy\n"
+		"str	w2, [%2, #0x34]\n"
+		/* Put all cores into WFI mode */
+		"1:\n"
+		"	wfi\n"
+		"	b	1b\n"
+		: : "r" (L2_RESET_DONE_STATUS),
+		    "r" (L2_RESET_DONE_REG),
+		    "r" (SOCFPGA_RSTMGR_ADDRESS),
+		    "r" (GICD_CTRL_ADDRESS)
+		: "x1", "x2", "x3");
+}
+
+static void l2_reset_cpu(void)
+{
+	__l2_reset_cpu();
+}
 
 static int socfpga_sysreset_request(struct udevice *dev,
 				    enum sysreset_t type)
 {
-	puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
+	if (type == SYSRESET_WARM) {
-	mbox_reset_cold();
+		/* flush dcache */
+		flush_dcache_all();
+
+		/* request a warm reset */
+		puts("Do warm reset now...\n");
+		l2_reset_cpu();
+	} else {
+		puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
+		mbox_reset_cold();
+	}
+
 	return -EINPROGRESS;
 }
 

include/configs/socfpga_soc64_common.h

@@ -18,6 +18,15 @@
 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
 #define CPU_RELEASE_ADDR		0xFFD12210
 
+/*
+ * Share sysmgr.boot_scratch_cold6 & 7 (64bit) with VBAR_LE3_BASE_ADDR
+ * Indicate L2 reset is done. HPS should trigger warm reset via RMR_EL3.
+ */
+#define L2_RESET_DONE_REG		0xFFD12218
+
+/* Magic word to indicate L2 reset is completed */
+#define L2_RESET_DONE_STATUS		0x1228E5E7
+
 /*
  * U-Boot console configurations
  */