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rockchip: sdram: update the sys_reg to sys_reg2
We are using sys_reg2 and sys_reg3 as ddr cap info, sync the variable name to what we real use to avoid confuse people. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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@ -83,60 +83,60 @@ size_t rockchip_sdram_size(phys_addr_t reg)
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u32 cs1_col = 0;
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u32 cs1_col = 0;
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u32 bg = 0;
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u32 bg = 0;
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u32 dbw, dram_type;
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u32 dbw, dram_type;
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u32 sys_reg = readl(reg);
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u32 sys_reg2 = readl(reg);
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u32 sys_reg3 = readl(reg + 4);
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u32 sys_reg3 = readl(reg + 4);
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u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT)
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u32 ch_num = 1 + ((sys_reg2 >> SYS_REG_NUM_CH_SHIFT)
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& SYS_REG_NUM_CH_MASK);
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& SYS_REG_NUM_CH_MASK);
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dram_type = (sys_reg >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
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dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
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debug("%s %x %x\n", __func__, (u32)reg, sys_reg);
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debug("%s %x %x\n", __func__, (u32)reg, sys_reg2);
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for (ch = 0; ch < ch_num; ch++) {
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for (ch = 0; ch < ch_num; ch++) {
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rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
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rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) &
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SYS_REG_RANK_MASK);
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SYS_REG_RANK_MASK);
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cs0_col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) &
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cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) &
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SYS_REG_COL_MASK);
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SYS_REG_COL_MASK);
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cs1_col = cs0_col;
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cs1_col = cs0_col;
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bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
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bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
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if ((sys_reg3 >> SYS_REG_VERSION_SHIFT &
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if ((sys_reg3 >> SYS_REG_VERSION_SHIFT &
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SYS_REG_VERSION_MASK) == 0x2) {
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SYS_REG_VERSION_MASK) == 0x2) {
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cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
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cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
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SYS_REG_CS1_COL_MASK);
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SYS_REG_CS1_COL_MASK);
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if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
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if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
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SYS_REG_EXTEND_CS0_ROW_MASK) << 2) + (sys_reg >>
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SYS_REG_EXTEND_CS0_ROW_MASK) << 2) + (sys_reg2 >>
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SYS_REG_CS0_ROW_SHIFT(ch) &
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SYS_REG_CS0_ROW_SHIFT(ch) &
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SYS_REG_CS0_ROW_MASK) == 7)
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SYS_REG_CS0_ROW_MASK) == 7)
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cs0_row = 12;
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cs0_row = 12;
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else
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else
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cs0_row = 13 + (sys_reg >>
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cs0_row = 13 + (sys_reg2 >>
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SYS_REG_CS0_ROW_SHIFT(ch) &
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SYS_REG_CS0_ROW_SHIFT(ch) &
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SYS_REG_CS0_ROW_MASK) +
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SYS_REG_CS0_ROW_MASK) +
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((sys_reg3 >>
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((sys_reg3 >>
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SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
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SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
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SYS_REG_EXTEND_CS0_ROW_MASK) << 2);
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SYS_REG_EXTEND_CS0_ROW_MASK) << 2);
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if (((sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
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if (((sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
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SYS_REG_EXTEND_CS1_ROW_MASK) << 2) + (sys_reg >>
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SYS_REG_EXTEND_CS1_ROW_MASK) << 2) + (sys_reg2 >>
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SYS_REG_CS1_ROW_SHIFT(ch) &
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SYS_REG_CS1_ROW_SHIFT(ch) &
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SYS_REG_CS1_ROW_MASK) == 7)
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SYS_REG_CS1_ROW_MASK) == 7)
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cs1_row = 12;
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cs1_row = 12;
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else
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else
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cs1_row = 13 + (sys_reg >>
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cs1_row = 13 + (sys_reg2 >>
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SYS_REG_CS1_ROW_SHIFT(ch) &
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SYS_REG_CS1_ROW_SHIFT(ch) &
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SYS_REG_CS1_ROW_MASK) +
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SYS_REG_CS1_ROW_MASK) +
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((sys_reg3 >>
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((sys_reg3 >>
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SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
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SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
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SYS_REG_EXTEND_CS1_ROW_MASK) << 2);
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SYS_REG_EXTEND_CS1_ROW_MASK) << 2);
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} else {
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} else {
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cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
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cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) &
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SYS_REG_CS0_ROW_MASK);
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SYS_REG_CS0_ROW_MASK);
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cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
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cs1_row = 13 + (sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) &
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SYS_REG_CS1_ROW_MASK);
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SYS_REG_CS1_ROW_MASK);
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}
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}
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bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
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bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) &
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SYS_REG_BW_MASK));
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SYS_REG_BW_MASK));
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row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
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row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) &
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SYS_REG_ROW_3_4_MASK;
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SYS_REG_ROW_3_4_MASK;
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if (dram_type == DDR4) {
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if (dram_type == DDR4) {
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dbw = (sys_reg >> SYS_REG_DBW_SHIFT(ch)) &
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dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) &
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SYS_REG_DBW_MASK;
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SYS_REG_DBW_MASK;
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bg = (dbw == 2) ? 2 : 1;
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bg = (dbw == 2) ? 2 : 1;
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}
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}
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