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clk: qcom: qcs615: Add GCC_AHB2PHY_WEST_CLK clock support

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Add GCC_AHB2PHY_WEST_CLK gate clock definition to the QCS615
clock driver. This clock is required for proper PHY operation
and eliminates clock-related warnings during USB initialization.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260213-talos_usb-v1-2-4c4355d61437@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
This commit is contained in:
Balaji Selvanathan 2026-02-13 14:31:19 +05:30 committed by Casey Connolly
parent c4f40d0925
commit c4169dfa1d
1 changed files with 1 additions and 0 deletions
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1
drivers/clk/qcom/clock-qcs615.c
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@ -67,6 +67,7 @@ static const struct gate_clk qcs615_clks[] = {
GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf054, BIT(0)),
GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf058, BIT(0)),
GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x8c014, BIT(0)),
GATE_CLK(GCC_AHB2PHY_WEST_CLK, 0x6a004, BIT(0)),
GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT),
GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT),
GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT),