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Revert "riscv: Clear pending interrupts before enabling IPIs"

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Clearing MIP.MSIP is not guaranteed to do anything by the spec. In
addition, most existing RISC-V hardware does nothing when this bit is set.

The following commits "riscv: Use a valid bit to ignore already-pending
IPIs" and "riscv: Clear pending IPIs on initialization" should implement
the original intent of the reverted commit in a more robust manner.

This reverts commit 9472630337e7c4ac442066b5a752aaa8c3b4d4a6.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This commit is contained in:
Sean Anderson 2020-09-21 07:51:35 -04:00 committed by Andes
parent 422c3c5edf
commit c41045411b
1 changed files with 0 additions and 2 deletions
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2
arch/riscv/cpu/start.S
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@ -65,8 +65,6 @@ _start:
#else #else
li t0, SIE_SSIE li t0, SIE_SSIE
#endif #endif
/* Clear any pending IPIs */
csrc MODE_PREFIX(ip), t0
csrs MODE_PREFIX(ie), t0 csrs MODE_PREFIX(ie), t0
#endif #endif