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arm64: zynqmp: Sync si570 setup and clock names

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Setup proper si570 names and default factory setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michal Simek 2019-06-25 08:55:52 +02:00
parent 2703d4b42d
commit bdd368afda
1 changed files with 14 additions and 14 deletions
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28
arch/arm/dts/zynqmp-p-a2197-00-revA.dts
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@ -387,9 +387,9 @@
compatible = "silabs,si570"; compatible = "silabs,si570";
reg = <0x5d>; /* 570JAC000900DG */ reg = <0x5d>; /* 570JAC000900DG */
temperature-stability = <50>; temperature-stability = <50>;
factory-fout = <156250000>; /* FIXME every chip can be different */ factory-fout = <33333333>;
clock-frequency = <33333333>; clock-frequency = <33333333>;
clock-output-names = "REF_CLK"; /* FIXME */ clock-output-names = "ref_clk";
}; };
/* Connection via Samtec J212D */ /* Connection via Samtec J212D */
/* Use for storing information about X-PRC card */ /* Use for storing information about X-PRC card */
@ -455,9 +455,9 @@
compatible = "silabs,si570"; compatible = "silabs,si570";
reg = <0x60>; /* 570BAB000299DG */ reg = <0x60>; /* 570BAB000299DG */
temperature-stability = <50>; temperature-stability = <50>;
factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ factory-fout = <200000000>;
clock-frequency = <33333333>; clock-frequency = <200000000>;
clock-output-names = "REF_CLK"; /* FIXME */ clock-output-names = "si570_ddrdimm1_clk";
}; };
/* 0x50 SPD? */ /* 0x50 SPD? */
}; };
@ -470,9 +470,9 @@
compatible = "silabs,si570"; compatible = "silabs,si570";
reg = <0x60>; /* 570BAB000299DG */ reg = <0x60>; /* 570BAB000299DG */
temperature-stability = <50>; temperature-stability = <50>;
factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ factory-fout = <200000000>;
clock-frequency = <33333333>; clock-frequency = <200000000>;
clock-output-names = "REF_CLK"; /* FIXME */ clock-output-names = "si570_ddrdimm2_clk";
}; };
/* 0x50 SPD? */ /* 0x50 SPD? */
}; };
@ -485,9 +485,9 @@
compatible = "silabs,si570"; compatible = "silabs,si570";
reg = <0x60>; /* 570BAB000299DG */ reg = <0x60>; /* 570BAB000299DG */
temperature-stability = <50>; temperature-stability = <50>;
factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ factory-fout = <200000000>;
clock-frequency = <33333333>; clock-frequency = <200000000>;
clock-output-names = "LPDDR4_SI570_CLK"; clock-output-names = "si570_lpddr4_clk";
}; };
}; };
i2c@6 { /* HSDP_SI570 */ i2c@6 { /* HSDP_SI570 */
@ -499,9 +499,9 @@
compatible = "silabs,si570"; compatible = "silabs,si570";
reg = <0x5d>; /* 570JAC000900DG */ reg = <0x5d>; /* 570JAC000900DG */
temperature-stability = <50>; temperature-stability = <50>;
factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ factory-fout = <156250000>;
clock-frequency = <33333333>; clock-frequency = <156250000>;
clock-output-names = "HSDP_SI570"; clock-output-names = "si570_hsdp_clk";
}; };
}; };
i2c@7 { /* PCIE_CLK */ i2c@7 { /* PCIE_CLK */