Merge branch 'master' of git://git.denx.de/u-boot-arm

Conflicts:

	cpu/arm_cortexa8/s5pc1xx/cache.c
	include/configs/spear6xx.h
	lib_ppc/reloc.S

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

MAINTAINERS

@@ -574,6 +574,7 @@ Peter Figuli <peposh@etc.sk>
 Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
 
 	meesc		ARM926EJS (AT91SAM9263 SoC)
+	otc570		ARM926EJS (AT91SAM9263 SoC)
 
 Sedji Gaouaou<sedji.gaouaou@atmel.com>
 	at91sam9g10ek		ARM926EJS (AT91SAM9G10 SoC)
@@ -598,6 +599,16 @@ Gary Jennejohn <garyj@denx.de>
 	smdk2400	ARM920T
 	trab		ARM920T
 
+Matthias Kaehlcke <matthias@kaehlcke.net>
+	edb9301			ARM920T (EP9301)
+	edb9302			ARM920T (EP9302)
+	edb9302a		ARM920T (EP9302)
+	edb9307			ARM920T (EP9307)
+	edb9307a		ARM920T (EP9307)
+	edb9312			ARM920T (EP9312)
+	edb9315			ARM920T (EP9315)
+	edb9315a		ARM920T (EP9315)
+
 Konstantin Kletschke <kletschke@synertronixx.de>
 	scb9328		ARM920T
 

MAKEALL

@@ -403,6 +403,7 @@ LIST_85xx="		\
 	MPC8560ADS	\
 	MPC8568MDS	\
 	MPC8569MDS	\
+	MPC8569MDS_ATM	\
 	MPC8572DS	\
 	MPC8572DS_36BIT	\
 	P2020DS		\
@@ -554,6 +555,14 @@ LIST_ARM9="			\
 	cp946es			\
 	cp966			\
 	da830evm		\
+	edb9301			\
+	edb9302			\
+	edb9302a		\
+	edb9307			\
+	edb9307a		\
+	edb9312			\
+	edb9315			\
+	edb9315a		\
 	imx27lite		\
 	lpd7a400		\
 	mv88f6281gtw_ge		\
@@ -658,6 +667,7 @@ LIST_at91="			\
 	meesc			\
 	mp2usb			\
 	m501sk			\
+	otc570			\
 	pm9261			\
 	pm9263			\
 	SBC35_A9G20		\

Makefile

@@ -324,6 +324,10 @@ $(obj)u-boot.img:	$(obj)u-boot.bin
 			sed -e 's/"[	 ]*$$/ for $(BOARD) board"/') \
 		-d $< $@
 
+$(obj)u-boot.imx:       $(obj)u-boot.bin
+		$(obj)tools/mkimage -n $(IMX_CONFIG) -T imximage \
+		-e $(TEXT_BASE) -d $< $@
+
 $(obj)u-boot.kwb:       $(obj)u-boot.bin
 		$(obj)tools/mkimage -n $(KWD_CONFIG) -T kwbimage \
 		-a $(TEXT_BASE) -e $(TEXT_BASE) -d $< $@
@@ -2412,6 +2416,16 @@ caddy2_config \
 vme8349_config:		unconfig
 	@$(MKCONFIG) -t $(@:_config=) vme8349 ppc mpc83xx vme8349 esd
 
+edb9301_config \
+edb9302_config \
+edb9302a_config \
+edb9307_config \
+edb9307a_config \
+edb9312_config \
+edb9315_config \
+edb9315a_config: unconfig
+	@$(MKCONFIG) -t $(@:_config=) edb93xx arm arm920t edb93xx NULL ep93xx
+
 #########################################################################
 ## MPC85xx Systems
 #########################################################################
@@ -2485,8 +2499,9 @@ MPC8555CDS_config:	unconfig
 MPC8568MDS_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale
 
+MPC8569MDS_ATM_config \
 MPC8569MDS_config:	unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8569mds freescale
+	@$(MKCONFIG) -t $(@:_config=) MPC8569MDS ppc mpc85xx mpc8569mds freescale
 
 MPC8572DS_36BIT_config \
 MPC8572DS_config:       unconfig
@@ -2867,6 +2882,9 @@ at91sam9g45ekes_config	:	unconfig
 	fi;
 	@$(MKCONFIG) -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91
 
+otc570_config	:	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs otc570 esd at91
+
 pm9263_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
 

README

@@ -3922,7 +3922,9 @@ For PowerPC, the following registers have specific use:
 	R30:	GOT pointer
 	R31:	frame pointer
 
-	(U-Boot also uses R14 as internal GOT pointer.)
+	(U-Boot also uses R12 as internal GOT pointer. r12
+	is a volatile register so r12 needs to be reset when
+	going back and forth between asm and C)
 
     ==> U-Boot will use R2 to hold a pointer to the global data
 

board/amcc/kilauea/kilauea.c

@@ -39,6 +39,37 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
+static int board_cpld_version(void)
+{
+	u32 cpld;
+
+	cpld = in_be32((void *)CONFIG_SYS_FPGA_FIFO_BASE);
+	if ((cpld & CONFIG_SYS_FPGA_MAGIC_MASK) != CONFIG_SYS_FPGA_MAGIC) {
+		/*
+		 * Magic not found -> "old" CPLD revision which needs
+		 * the "old" EBC configuration
+		 */
+		mtebc(PB2AP, EBC_BXAP_BME_ENABLED | EBC_BXAP_FWT_ENCODE(5) |
+		      EBC_BXAP_BWT_ENCODE(0) | EBC_BXAP_BCE_DISABLE |
+		      EBC_BXAP_BCT_2TRANS | EBC_BXAP_CSN_ENCODE(0) |
+		      EBC_BXAP_OEN_ENCODE(0) | EBC_BXAP_WBN_ENCODE(3) |
+		      EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_TH_ENCODE(4) |
+		      EBC_BXAP_RE_DISABLED | EBC_BXAP_SOR_DELAYED |
+		      EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED);
+
+		/*
+		 * Return 0 for "old" CPLD version
+		 */
+		return 0;
+	}
+
+	/*
+	 * Magic found -> "new" CPLD revision which needs no new
+	 * EBC configuration
+	 */
+	return (cpld & CONFIG_SYS_FPGA_VER_MASK) >> 8;
+}
+
 /*
  * Board early initialization function
  */
@@ -208,6 +239,13 @@ int board_early_init_f (void)
 	val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
 	mtsdr(SDR0_PFC1, val);
 
+	/*
+	 * The CPLD version detection has to be the first access to
+	 * the CPLD, so we need to make this access this early and
+	 * save the CPLD version for later.
+	 */
+	gd->board_type = board_cpld_version();
+
 	/*
 	 * Configure FPGA register with PCIe reset
 	 */
@@ -280,7 +318,7 @@ int checkboard (void)
 		puts(", serial# ");
 		puts(s);
 	}
-	putc('\n');
+	printf(" (CPLD rev. %ld)\n", gd->board_type);
 
 	return (0);
 }

board/davinci/da830evm/da830evm.c

@@ -42,34 +42,43 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define pinmux	&davinci_syscfg_regs->pinmux
 
-#ifdef CONFIG_SPI_FLASH
 /* SPI0 pin muxer settings */
-const struct pinmux_config spi0_pins[] = {
+static const struct pinmux_config spi0_pins[] = {
 	{ pinmux[7], 1, 3 },
 	{ pinmux[7], 1, 4 },
 	{ pinmux[7], 1, 5 },
 	{ pinmux[7], 1, 6 },
 	{ pinmux[7], 1, 7 }
 };
-#endif
 
 /* UART pin muxer settings */
-const struct pinmux_config uart_pins[] = {
+static const struct pinmux_config uart_pins[] = {
 	{ pinmux[8], 2, 7 },
 	{ pinmux[9], 2, 0 }
 };
 
 /* I2C pin muxer settings */
-const struct pinmux_config i2c_pins[] = {
+static const struct pinmux_config i2c_pins[] = {
 	{ pinmux[9], 2, 3 },
 	{ pinmux[9], 2, 4 }
 };
 
 /* USB0_DRVVBUS pin muxer settings */
-const struct pinmux_config usb_pins[] = {
+static const struct pinmux_config usb_pins[] = {
 	{ pinmux[9], 1, 1 }
 };
 
+static const struct pinmux_resource pinmuxes[] = {
+#ifdef CONFIG_SPI_FLASH
+	PINMUX_ITEM(spi0_pins),
+#endif
+	PINMUX_ITEM(uart_pins),
+	PINMUX_ITEM(i2c_pins),
+#ifdef CONFIG_USB_DA8XX
+	PINMUX_ITEM(usb_pins),
+#endif
+};
+
 int board_init(void)
 {
 #ifndef CONFIG_USE_IRQ
@@ -112,18 +121,8 @@ int board_init(void)
 		 DAVINCI_SYSCFG_SUSPSRC_UART2),
 	       &davinci_syscfg_regs->suspsrc);
 
-#ifdef CONFIG_SPI_FLASH
+	/* configure pinmux settings */
-	if (davinci_configure_pin_mux(spi0_pins, ARRAY_SIZE(spi0_pins)) != 0)
+	if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
-		return 1;
-#endif
-
-	if (davinci_configure_pin_mux(uart_pins, ARRAY_SIZE(uart_pins)) != 0)
-		return 1;
-
-	if (davinci_configure_pin_mux(i2c_pins, ARRAY_SIZE(i2c_pins)) != 0)
-		return 1;
-
-	if (davinci_configure_pin_mux(usb_pins, ARRAY_SIZE(usb_pins)) != 0)
 		return 1;
 
 	/* enable the console UART */

board/edb93xx/Makefile

@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= edb93xx.o flash_cfg.o pll_cfg.o sdram_cfg.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/edb93xx/config.mk

@@ -0,0 +1,33 @@
+LDSCRIPT := $(SRCTREE)/cpu/arm920t/ep93xx/u-boot.lds
+
+ifdef CONFIG_EDB9301
+TEXT_BASE = 0x05700000
+endif
+
+ifdef CONFIG_EDB9302
+TEXT_BASE = 0x05700000
+endif
+
+ifdef CONFIG_EDB9302A
+TEXT_BASE = 0xc5700000
+endif
+
+ifdef CONFIG_EDB9307
+TEXT_BASE = 0x01f00000
+endif
+
+ifdef CONFIG_EDB9307A
+TEXT_BASE = 0xc1f00000
+endif
+
+ifdef CONFIG_EDB9312
+TEXT_BASE = 0x01f00000
+endif
+
+ifdef CONFIG_EDB9315
+TEXT_BASE = 0x01f00000
+endif
+
+ifdef CONFIG_EDB9315A
+TEXT_BASE = 0xc1f00000
+endif

board/edb93xx/early_udelay.h

@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* delay execution before timers are initialized */
+static inline void early_udelay(uint32_t usecs)
+{
+	/* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
+	register uint32_t loops = (usecs * 1000) / 20;
+
+	__asm__ volatile ("1:\n"
+			"subs %0, %1, #1\n"
+			"bne 1b":"=r" (loops):"0" (loops));
+}

board/edb93xx/edb93xx.c

@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * (C) Copyright 2002 2003
+ * Network Audio Technologies, Inc. <www.netaudiotech.com>
+ * Adam Bezanson <bezanson@netaudiotech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MAX_BANK_SIZE	0x04000000 /* 64 MB */
+
+static ulong const bank_addr[CONFIG_NR_DRAM_BANKS] = {
+	PHYS_SDRAM_1,
+#ifdef PHYS_SDRAM_2
+	PHYS_SDRAM_2,
+#endif
+#ifdef PHYS_SDRAM_3
+	PHYS_SDRAM_3,
+#endif
+#ifdef PHYS_SDRAM_4
+	PHYS_SDRAM_4
+#endif
+};
+
+int board_init(void)
+{
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+	icache_enable();
+
+#ifdef USE_920T_MMU
+	dcache_enable();
+#endif
+
+	/*
+	 * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
+	 * 14.7456/2 MHz
+	 */
+	uint32_t value = readl(&syscon->pwrcnt);
+	value |= SYSCON_PWRCNT_UART_BAUD;
+	writel(value, &syscon->pwrcnt);
+
+	/* Machine number, as defined in linux/arch/arm/tools/mach-types */
+	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	/* We have a console */
+	gd->have_console = 1;
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+	return ep93xx_eth_initialize(0, MAC_BASE);
+}
+
+int dram_init(void)
+{
+	unsigned int *src, *dst;
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		const ulong bank_size = get_ram_size((long *)bank_addr[i],
+						MAX_BANK_SIZE);
+		if (bank_size) {
+			gd->bd->bi_dram[i].start = bank_addr[i];
+			gd->bd->bi_dram[i].size = bank_size;
+		}
+	}
+
+	/* copy exception vectors */
+	src = (unsigned int *)_armboot_start;
+	dst = (unsigned int *)PHYS_SDRAM_1;
+	memcpy(dst, src, 16 * sizeof(unsigned int));
+
+	return 0;
+}

board/edb93xx/flash_cfg.c

@@ -0,0 +1,38 @@
+/*
+ * Flash setup for Cirrus edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+#define SMC_BCR6_VALUE	(2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT |	\
+				SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT |		\
+				1 << SMC_BCR_MW_SHIFT)
+
+void flash_cfg(void)
+{
+	struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
+
+	writel(SMC_BCR6_VALUE, &smc->bcr6);
+}

board/edb93xx/pll_cfg.c

@@ -0,0 +1,58 @@
+/*
+ * PLL setup for Cirrus edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "pll_cfg.h"
+#include "early_udelay.h"
+
+void pll_cfg(void)
+{
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+	/* setup PLL1 */
+	writel(CLKSET1_VAL, &syscon->clkset1);
+
+	/*
+	 * flush the pipeline
+	 * writing to CLKSET1 causes the EP93xx to enter standby for between
+	 * 8 ms to 16 ms, until PLL1 stabilizes
+	 */
+	asm("nop");
+	asm("nop");
+	asm("nop");
+	asm("nop");
+	asm("nop");
+
+	/* setup PLL2 */
+	writel(CLKSET2_VAL, &syscon->clkset2);
+
+	/*
+	 * the user's guide recommends to wait at least 1 ms for PLL2 to
+	 * stabilize
+	 */
+	early_udelay(1000);
+}

board/edb93xx/pll_cfg.h

@@ -0,0 +1,72 @@
+/*
+ * PLL register values for Cirrus edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/ep93xx.h>
+
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) ||	\
+	defined(CONFIG_EDB9302A)
+/*
+ * fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2
+ * pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000,
+ * pll1_x2: 331776000.000000, pll1_out: 331776000.000000
+ */
+#define CLKSET1_VAL	(7 << SYSCON_CLKSET_PLL_X2IPD_SHIFT |	\
+			8 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT |	\
+			19 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT |	\
+			1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT |	\
+			3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT |	\
+			SYSCON_CLKSET1_NBYP1 |			\
+			1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
+#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||	\
+	defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) ||	\
+	defined(CONFIG_EDB9315A)
+/*
+ * fclk_div: 2, nbyp1: 1, hclk_div: 4, pclk_div: 2
+ * pll1_x1: 3096576000.000000, pll1_x2ip: 129024000.000000,
+ * pll1_x2: 3999744000.000000, pll1_out: 1999872000.000000
+ */
+#define CLKSET1_VAL	(23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT |	\
+			30 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT |	\
+			20 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT |	\
+			1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT |	\
+			2 << SYSCON_CLKSET1_HCLK_DIV_SHIFT |	\
+			SYSCON_CLKSET1_NBYP1 |			\
+			1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
+#else
+#error "Undefined board"
+#endif
+
+/*
+ * usb_div: 4, nbyp2: 1, pll2_en: 1
+ * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
+ * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
+ */
+#define CLKSET2_VAL	(23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT |	\
+			24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT |	\
+			24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT |	\
+			1 << SYSCON_CLKSET_PLL_PS_SHIFT |	\
+			SYSCON_CLKSET2_PLL2_EN |		\
+			SYSCON_CLKSET2_NBYP2 |			\
+			3 << SYSCON_CLKSET2_USB_DIV_SHIFT)

board/edb93xx/sdram_cfg.c

@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/io.h>
+#include "sdram_cfg.h"
+#include "early_udelay.h"
+
+#define PROGRAM_MODE_REG(bank)		(*(volatile uint32_t *)		\
+		(SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL))
+
+#define PRECHARGE_BANK(bank)		(*(volatile uint32_t *)		\
+				(SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank))
+
+static void force_precharge(void);
+static void setup_refresh_timer(void);
+static void program_mode_registers(void);
+
+void sdram_cfg(void)
+{
+	struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
+
+	writel(SDRAM_DEVCFG_VAL, &sdram->SDRAM_DEVCFG_REG);
+
+	/* Issue continous NOP commands */
+	writel(GLCONFIG_INIT | GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig);
+
+	early_udelay(200);
+
+	force_precharge();
+
+	setup_refresh_timer();
+
+	program_mode_registers();
+
+	/* Select normal operation mode */
+	writel(GLCONFIG_CKE, &sdram->glconfig);
+}
+
+static void force_precharge(void)
+{
+	/*
+	 * Errata most EP93xx revisions say that PRECHARGE ALL isn't always
+	 * issued.
+	 *
+	 * Do a read from each bank to make sure they're precharged
+	 */
+
+	PRECHARGE_BANK(0);
+	PRECHARGE_BANK(1);
+	PRECHARGE_BANK(2);
+	PRECHARGE_BANK(3);
+}
+
+static void setup_refresh_timer(void)
+{
+	struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
+
+	/* Load refresh timer with 10 to issue refresh every 10 cycles */
+	writel(0x0a, &sdram->refrshtimr);
+
+	/*
+	 * Wait at least 80 clock cycles to provide 8 refresh cycles
+	 * to all SDRAMs
+	 */
+	early_udelay(1);
+
+	/*
+	 * Program refresh timer with normal value
+	 * We need 8192 refresh cycles every 64ms
+	 * at 15ns (HCLK >= 66MHz) per cycle:
+	 * 64ms / 8192 = 7.8125us
+	 * 7.8125us / 15ns = 520 (0x208)
+	 */
+	/*
+	 * TODO: redboot uses 0x1e0 for the slowest possible device
+	 * but i don't understand how this value is calculated
+	 */
+	writel(0x208, &sdram->refrshtimr);
+}
+
+static void program_mode_registers(void)
+{
+	/*
+	 * The mode registers are programmed by performing a read from each
+	 * SDRAM bank. The value of the address that is read defines the value
+	 * that is written into the mode register
+	 */
+
+	PROGRAM_MODE_REG(0);
+
+#if (CONFIG_NR_DRAM_BANKS >= 2)
+	PROGRAM_MODE_REG(1);
+#endif
+
+#if (CONFIG_NR_DRAM_BANKS >= 3)
+	PROGRAM_MODE_REG(2);
+#endif
+
+#if (CONFIG_NR_DRAM_BANKS == 4)
+	PROGRAM_MODE_REG(3);
+#endif
+}

board/edb93xx/sdram_cfg.h

@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/ep93xx.h>
+
+#define SDRAM_BASE_ADDR		PHYS_SDRAM_1
+
+#ifdef CONFIG_EDB93XX_SDCS0
+#define SDRAM_DEVCFG_REG	devcfg0
+#elif defined(CONFIG_EDB93XX_SDCS3)
+#define SDRAM_DEVCFG_REG	devcfg3
+#else
+#error "SDRAM bank configuration"
+#endif
+
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) ||	\
+	defined(CONFIG_EDB9302A)
+/*
+ * 1x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
+ *
+ * CLK cycle time min:
+ *	@ CAS latency = 3: 7.5ns
+ *	@ CAS latency = 2: 10ns
+ * We're running at 66MHz (15ns cycle time) external bus speed (HCLK),
+ * so it's safe to use CAS latency = 2
+ *
+ * RAS-to-CAS delay min:
+ *	20ns
+ * At 15ns cycle time, we use RAS-to-CAS delay = 2
+ *
+ * SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear
+ * as four blocks of 8MB size, instead of eight blocks of 4MB size:
+ *
+ * EDB9301/EDB9302:
+ *
+ * 0x00000000 - 0x007fffff
+ * 0x01000000 - 0x017fffff
+ * 0x04000000 - 0x047fffff
+ * 0x05000000 - 0x057fffff
+ *
+ *
+ * EDB9302a:
+ *
+ * 0xc0000000 - 0xc07fffff
+ * 0xc1000000 - 0xc17fffff
+ * 0xc4000000 - 0xc47fffff
+ * 0xc5000000 - 0xc57fffff
+ *
+ * BANKCOUNT = 1: This is a device with four banks
+ */
+
+#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT |			\
+				SDRAM_DEVCFG_SROMLL |			\
+				SDRAM_DEVCFG_CASLAT_2 |			\
+				SDRAM_DEVCFG_RASTOCAS_2 |		\
+				SDRAM_DEVCFG_EXTBUSWIDTH)
+
+/*
+ * 16 bit ext. bus
+ *
+ * A[22:09] is output as SYA[13:0]
+ * CAS latency: 2
+ * Burst type: sequential
+ * Burst length: 8 (required for 16 bit ext. bus)
+ * SYA[13:0] = 0x0023
+ */
+#define SDRAM_MODE_REG_VAL	0x4600
+
+#define SDRAM_BANK_SEL_0	0x00000000 /* A[22:21] = b00 */
+#define SDRAM_BANK_SEL_1	0x00200000 /* A[22:21] = b01 */
+#define SDRAM_BANK_SEL_2	0x00400000 /* A[22:21] = b10 */
+#define SDRAM_BANK_SEL_3	0x00600000 /* A[22:21] = b11 */
+
+#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||	\
+	defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) ||	\
+	defined(CONFIG_EDB9315A)
+/*
+ * 2x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
+ *
+ * CLK cycle time min:
+ *	@ CAS latency = 3: 7.5ns
+ *	@ CAS latency = 2: 10ns
+ * We're running at 100MHz (10ns cycle time) external bus speed (HCLK),
+ * so it's safe to use CAS latency = 2
+ *
+ * RAS-to-CAS delay min:
+ *	20ns
+ * At 10ns cycle time, we use RAS-to-CAS delay = 2
+ *
+ * EDB9307, EDB9312, EDB9315:
+ *
+ * 0x00000000 - 0x01ffffff
+ * 0x04000000 - 0x05ffffff
+ *
+ *
+ * EDB9307a, EDB9315a:
+ *
+ * 0xc0000000 - 0xc1ffffff
+ * 0xc4000000 - 0xc5ffffff
+ */
+
+#define SDRAM_DEVCFG_VAL	(SDRAM_DEVCFG_BANKCOUNT |		\
+				SDRAM_DEVCFG_SROMLL |			\
+				SDRAM_DEVCFG_CASLAT_2 |			\
+				SDRAM_DEVCFG_RASTOCAS_2)
+
+/*
+ * 32 bit ext. bus
+ *
+ * A[23:10] is output as SYA[13:0]
+ * CAS latency: 2
+ * Burst type: sequential
+ * Burst length: 4
+ * SYA[13:0] = 0x0022
+ */
+#define SDRAM_MODE_REG_VAL	0x8800
+
+#define SDRAM_BANK_SEL_0	0x00000000 /* A[23:22] = b00 */
+#define SDRAM_BANK_SEL_1	0x00400000 /* A[23:22] = b01 */
+#define SDRAM_BANK_SEL_2	0x00800000 /* A[23:22] = b10 */
+#define SDRAM_BANK_SEL_3	0x00c00000 /* A[23:22] = b11 */
+#endif

board/esd/otc570/Makefile

@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y				+= $(BOARD).o
+COBJS-$(CONFIG_HAS_DATAFLASH)	+= partition.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/esd/otc570/config.mk

@@ -0,0 +1 @@
+TEXT_BASE = 0x23f00000

board/esd/otc570/otc570.c

@@ -0,0 +1,365 @@
+/*
+ * (C) Copyright 2010
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/at91sam9_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/io.h>
+#include <atmel_lcdc.h>
+#include <lcd.h>
+#include <netdev.h>
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static int hw_rev = -1;	/* hardware revision */
+
+int get_hw_rev(void)
+{
+	if (hw_rev >= 0)
+		return hw_rev;
+
+	hw_rev = at91_get_gpio_value(AT91_PIN_PB19);
+	hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1;
+	hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2;
+	hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3;
+
+	if (hw_rev == 15)
+		hw_rev = 0;
+
+	return hw_rev;
+}
+
+#ifdef CONFIG_CMD_NAND
+static void otc570_nand_hw_init(void)
+{
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
+	at91_sys_write(AT91_MATRIX_EBI0CSA,
+		csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	at91_sys_write(AT91_SMC_SETUP(3),
+		AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+		AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+		AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+	at91_sys_write(AT91_SMC_MODE(3),
+		AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		AT91_SMC_EXNWMODE_DISABLE |
+		AT91_SMC_DBW_8 |
+		AT91_SMC_TDF_(2));
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif /* CONFIG_CMD_NAND */
+
+#ifdef CONFIG_MACB
+static void otc570_macb_hw_init(void)
+{
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
+	at91_macb_hw_init();
+}
+#endif
+
+/*
+ * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
+ * controller debugging
+ * The ET1100 is located at physical address 0x70000000
+ * Its process memory is located at physical address 0x70001000
+ */
+static void otc570_ethercat_hw_init(void)
+{
+	/* Configure SMC EBI1_CS0 for EtherCAT */
+	at91_sys_write(AT91_SMC1_SETUP(0),
+		AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
+		AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC1_PULSE(0),
+		AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) |
+		AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(9));
+	at91_sys_write(AT91_SMC1_CYCLE(0),
+		AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(6));
+	/*
+	 * Configure behavior at external wait signal, byte-select mode, 16 bit
+	 * data bus width, none data float wait states and TDF optimization
+	 */
+	at91_sys_write(AT91_SMC1_MODE(0),
+		AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY |
+		AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) |
+		AT91_SMC_TDFMODE);
+
+	/* Configure RDY/BSY */
+	at91_set_B_periph(AT91_PIN_PE20, 0);	/* EBI1_NWAIT */
+}
+
+#ifdef CONFIG_LCD
+/* Number of columns and rows, pixel clock in Hz and hsync/vsync polarity */
+vidinfo_t panel_info = {
+	.vl_col =		640,
+	.vl_row =		480,
+	.vl_clk =		25175000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
+				ATMEL_LCDC_INVFRAME_INVERTED,
+
+	.vl_bpix =		3,	/* Bits per pixel, 0 = 1bit, 3 = 8bit */
+	.vl_tft =		1,	/* 0 = passive, 1 = TFT */
+	.vl_vsync_len =		1,	/* Length of vertical sync in NOL */
+	.vl_upper_margin =	35,	/* Idle lines at the frame start */
+	.vl_lower_margin =	5,	/* Idle lines at the end of the frame */
+	.vl_hsync_len =		5,	/* Width of the LCDHSYNC pulse */
+	.vl_left_margin =	112,	/* Idle cycles at the line beginning */
+	.vl_right_margin =	1,	/* Idle cycles at the end of the line */
+
+	.mmio =			AT91SAM9263_LCDC_BASE,
+};
+
+void lcd_enable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA30, 0);	/* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA30, 1);	/* power down */
+}
+
+static void otc570_lcd_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PC0, 0);	/* LCDVSYNC */
+	at91_set_A_periph(AT91_PIN_PC1, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PC2, 0);	/* LCDDOTCK */
+	at91_set_A_periph(AT91_PIN_PC3, 0);	/* LCDDEN */
+	at91_set_B_periph(AT91_PIN_PB9, 0);	/* LCDCC */
+	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDD2 */
+	at91_set_A_periph(AT91_PIN_PC7, 0);	/* LCDD3 */
+	at91_set_A_periph(AT91_PIN_PC8, 0);	/* LCDD4 */
+	at91_set_A_periph(AT91_PIN_PC9, 0);	/* LCDD5 */
+	at91_set_A_periph(AT91_PIN_PC10, 0);	/* LCDD6 */
+	at91_set_A_periph(AT91_PIN_PC11, 0);	/* LCDD7 */
+	at91_set_A_periph(AT91_PIN_PC14, 0);	/* LCDD10 */
+	at91_set_A_periph(AT91_PIN_PC15, 0);	/* LCDD11 */
+	at91_set_A_periph(AT91_PIN_PC16, 0);	/* LCDD12 */
+	at91_set_B_periph(AT91_PIN_PC12, 0);	/* LCDD13 */
+	at91_set_A_periph(AT91_PIN_PC18, 0);	/* LCDD14 */
+	at91_set_A_periph(AT91_PIN_PC19, 0);	/* LCDD15 */
+	at91_set_A_periph(AT91_PIN_PC22, 0);	/* LCDD18 */
+	at91_set_A_periph(AT91_PIN_PC23, 0);	/* LCDD19 */
+	at91_set_A_periph(AT91_PIN_PC24, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PC17, 0);	/* LCDD21 */
+	at91_set_A_periph(AT91_PIN_PC26, 0);	/* LCDD22 */
+	at91_set_A_periph(AT91_PIN_PC27, 0);	/* LCDD23 */
+	at91_set_gpio_output(AT91_PIN_PA30, 1);	/* PCI */
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
+
+	gd->fb_base = CONFIG_OTC570_LCD_BASE;
+}
+
+#ifdef CONFIG_LCD_INFO
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+	int i;
+	char temp[32];
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i].size;
+
+	lcd_printf("\n%s\n", U_BOOT_VERSION);
+	lcd_printf("%s CPU at %s MHz\n", AT91_CPU_NAME,
+					strmhz(temp, get_cpu_clk_rate()));
+	lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
+		dram_size >> 20,
+		nand_size >> 20 );
+	lcd_printf("  Board            : esd ARM9 HMI Panel - OTC570\n");
+	lcd_printf("  Hardware-revision: 1.%d\n", get_hw_rev());
+	lcd_printf("  Mach-type        : %lu\n", gd->bd->bi_arch_number);
+}
+#endif /* CONFIG_LCD_INFO */
+#endif /* CONFIG_LCD */
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27));
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}
+
+int checkboard(void)
+{
+	char str[32];
+
+	puts("Board: esd ARM9 HMI Panel - OTC570");
+	if (getenv_r("serial#", str, sizeof(str)) > 0) {
+		puts(", serial# ");
+		puts(str);
+	}
+	printf("\nHardware-revision: 1.%d\n", get_hw_rev());
+	printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
+	return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	char *str;
+
+	char *serial = getenv("serial#");
+	if (serial) {
+		str = strchr(serial, '_');
+		if (str && (strlen(str) >= 4)) {
+			serialnr->high = (*(str + 1) << 8) | *(str + 2);
+			serialnr->low = simple_strtoul(str + 3, NULL, 16);
+		}
+	} else {
+		serialnr->high = 0;
+		serialnr->low = 0;
+	}
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+	return hw_rev | 0x100;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	char str[64];
+
+	at91_set_gpio_output(AT91_PIN_PA29, 1);
+	at91_set_A_periph(AT91_PIN_PA26, 1);			/* TXD0 */
+	at91_set_A_periph(AT91_PIN_PA27, 0);			/* RXD0 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0);
+	/* Set USART_MODE = 1 (RS485) */
+	at91_sys_write((0xFFF8C004 - AT91_BASE_SYS), 1);
+
+	printf("USART0: ");
+
+	if (getenv_r("usart0", str, sizeof(str)) == -1) {
+		printf("No entry - assuming 1-wire\n");
+		/* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */
+		at91_set_gpio_output(AT91_PIN_PA29, 0);
+	} else {
+		if (strcmp(str, "1-wire") == 0) {
+			printf("%s\n", str);
+			at91_set_gpio_output(AT91_PIN_PA29, 0);
+		} else if (strcmp(str, "rs485") == 0) {
+			printf("%s\n", str);
+			at91_set_gpio_output(AT91_PIN_PA29, 1);
+		} else {
+			printf("Wrong entry - assuming 1-wire ");
+			printf("(valid values are '1-wire' or 'rs485')\n");
+			at91_set_gpio_output(AT91_PIN_PA29, 0);
+		}
+	}
+	printf("Display memory address: 0x%08lX\n", gd->fb_base);
+
+	return 0;
+}
+#endif /* CONFIG_MISC_INIT_R */
+
+int board_init(void)
+{
+	/* Peripheral Clock Enable Register */
+	at91_sys_write(AT91_PMC_PCER,	1 << AT91SAM9263_ID_PIOA |
+					1 << AT91SAM9263_ID_PIOB |
+					1 << AT91SAM9263_ID_PIOCDE |
+					1 << AT91SAM9263_ID_TWI |
+					1 << AT91SAM9263_ID_SPI0 |
+					1 << AT91SAM9263_ID_LCDC |
+					1 << AT91SAM9263_ID_UHP);
+
+	/* arch number of OTC570-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_OTC570;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	otc570_nand_hw_init();
+#endif
+	otc570_ethercat_hw_init();
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+	otc570_macb_hw_init();
+#endif
+#ifdef CONFIG_AT91_CAN
+	at91_can_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+	at91_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	otc570_lcd_hw_init();
+#endif
+	return 0;
+}

board/esd/otc570/partition.c

@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+};
+
+/* define the area offsets */
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+};

board/freescale/common/pq-mds-pib.c

@@ -63,7 +63,7 @@ int pib_init(void)
 #endif
 
 #if defined(CONFIG_PQ_MDS_PIB_ATM)
-#if defined(CONFIG_MPC8360EMDS)
+#if defined(CONFIG_MPC8360EMDS) || defined(CONFIG_MPC8569MDS)
 	val8 = 0;
 	i2c_write(0x20, 0x6, 1, &val8, 1);
 	i2c_write(0x20, 0x7, 1, &val8, 1);

board/freescale/mpc8569mds/mpc8569mds.c

@@ -39,6 +39,9 @@
 #include <fsl_esdhc.h>
 
 #include "bcsr.h"
+#if defined(CONFIG_PQ_MDS_PIB)
+#include "../common/pq-mds-pib.h"
+#endif
 
 phys_size_t fixed_sdram(void);
 
@@ -545,6 +548,10 @@ void pci_init_board(void)
 
 	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
 
+#if defined(CONFIG_PQ_MDS_PIB)
+	pib_init();
+#endif
+
 #ifdef CONFIG_PCIE1
 	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
 

board/netstar/crcit.c

@@ -56,13 +56,14 @@ static int do_crc(char *path, unsigned version)
 		fprintf(stderr, "File too large\n");
 		return EXIT_FAILURE;
 	}
-	size = (size + 3) & ~3;	/* round up to 4 bytes */
+	size  = (size + 3) & ~3;	/* round up to 4 bytes */
-	data[0] = size + 4;	/* add size of version field */
+	size += 4;			/* add size of version field */
+	data[0] = size;
 	data[1] = version;
-	data[2 + (size >> 2)] = crc32(0, (unsigned char *)(data + 1), data[0]);
+	data[size/4 + 1] = crc32(0, (unsigned char *)(data + 1), size);
 	close(fd);
 
-	if (write(STDOUT_FILENO, data, size + 3*4) == -1) {
+	if (write(STDOUT_FILENO, data, size + 4 /*size*/ + 4 /*crc*/) == -1) {
 		perror("Error writing file");
 		return EXIT_FAILURE;
 	}

board/netstar/eeprom.c

@@ -22,8 +22,6 @@
  * Some code shamelessly stolen back from Robin Getz.
  */
 
-#define DEBUG
-
 #include <common.h>
 #include <exports.h>
 #include <timestamp.h>
@@ -142,8 +140,6 @@ static int parse_element(char *s, unsigned char *buf, int len)
 	return cnt;
 }
 
-extern int crcek(void);
-
 int eeprom(int argc, char *argv[])
 {
 	int i, len, ret;
@@ -161,8 +157,6 @@ int eeprom(int argc, char *argv[])
 		return 1;
 	}
 
-	return crcek();
-
 	if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
 		printf("SMSC91111 not found.\n");
 		return 2;
@@ -176,7 +170,7 @@ int eeprom(int argc, char *argv[])
 
 	/* Print help message */
 	if (argv[1][1] == 'h') {
-		printf("VoiceBlue EEPROM writer\n");
+		printf("NetStar EEPROM writer\n");
 		printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
 		printf("Usage:\n\t<mac_address> [<element_1>] [<...>]\n");
 		return 0;

board/netstar/eeprom_start.S

@@ -8,170 +8,6 @@
  */
 
 .globl _start
-_start:	b       eeprom
+_start:	b	eeprom
-
-#include "crcek.h"
-
-/**
- * do_crc32 - calculate CRC32 of given buffer
- * r0 - crc
- * r1 - pointer to buffer
- * r2 - buffer len
- */
-	.macro	do_crc32
-	ldr	r5, FFFFFFFF
-	eor	r0, r0, r5
-	adr	r3, CRC32_TABLE
-1:
-	ldrb    r4, [r1], #1
-	eor	r4, r4, r0
-	and	r4, r4, #0xff
-	ldr	r4, [r3, r4, lsl#2]
-	eor	r0, r4, r0, lsr#8
-	subs	r2, r2, #0x1
-	bne	1b
-	eor	r0, r0, r5
-	.endm
-
-	.macro crcuj, offset, size
-	ldr	r1, \offset
-	ldr	r2, [r1]
-	cmp	r2, #0		@ no data, no problem
-	beq	2f
-	mov     r7, #1
-	tst	r2, #3		@ unaligned size
-	bne	2f
-	mov     r7, #2
-	ldr	r0, \size
-	cmp	r2, r0		@ bogus size
-	bhi	2f
-	mov     r7, #3
-	add	r1, r1, #4
-	mov	r0, #0
-	do_crc32
-	ldr	r1, [r1]
-2:
-	cmp	r0, r1
-	.endm
-
-	.macro wait, reg
-	mov	\reg, #0x1000
-3:
-	subs	\reg, \reg, #0x1
-	bne	3b
-
-	.endm
-.text
-.globl crcek
-crcek:
-	mov	r6, #0
-@	crcuj	_LOADER1_OFFSET, _LOADER_SIZE
-@	bne	crc1_bad
-@	orr	r6, r6, #1
-crc1_bad:
-	crcuj	_LOADER2_OFFSET, _LOADER_SIZE
-	bne	crc2_bad
-	orr	r6, r6, #2
-crc2_bad:
-@	mov	r0, r6
-	mov     pc, lr
-	ldr	r3, _LOADER1_OFFSET
-	ldr	r4, _LOADER2_OFFSET
-	tst	r6, #3
-	beq	one_is_bad	@ one of them (or both) has bad crc
-	ldr	r1, [r3, #4]
-	ldr	r2, [r4, #4]
-	cmp	r1, r2		@ boot 2nd loader if versions differ
-	beq	boot_1st
-	b	boot_2nd
-one_is_bad:
-	tst	r6, #1
-	bne	boot_1st
-	tst	r6, #2
-	bne	boot_2nd
-@ We are doomed, so let user know.
-	ldr	r0, GPIO_BASE	@ configure GPIO pins
-	ldr	r1, GPIO_DIRECTION
-	strh	r1, [r0, #0x08]
-blink_loop:
-	mov	r1, #0x08
-	strh    r1, [r0, #0x04]
-	wait	r3
-	mov	r1, #0x10
-	strh    r1, [r0, #0x04]
-	wait	r3
-	b blink_loop
-boot_1st:
-	add	pc, r3, #8
-boot_2nd:
-	add	pc, r4, #8
-
-_LOADER_SIZE:
-	.word LOADER_SIZE - 8	@ minus size and crc32
-_LOADER1_OFFSET:
-	.word LOADER1_OFFSET
-_LOADER2_OFFSET:
-	.word LOADER2_OFFSET
-
-FFFFFFFF:
-	.word 0xffffffff
-CRC32_TABLE:
-	.word 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419
-	.word 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4
-	.word 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07
-	.word 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de
-	.word 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856
-	.word 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9
-	.word 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4
-	.word 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b
-	.word 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3
-	.word 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a
-	.word 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599
-	.word 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924
-	.word 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190
-	.word 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f
-	.word 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e
-	.word 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01
-	.word 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed
-	.word 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950
-	.word 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3
-	.word 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2
-	.word 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a
-	.word 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5
-	.word 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010
-	.word 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f
-	.word 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17
-	.word 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6
-	.word 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615
-	.word 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8
-	.word 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344
-	.word 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb
-	.word 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a
-	.word 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5
-	.word 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1
-	.word 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c
-	.word 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef
-	.word 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236
-	.word 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe
-	.word 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31
-	.word 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c
-	.word 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713
-	.word 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b
-	.word 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242
-	.word 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1
-	.word 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c
-	.word 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278
-	.word 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7
-	.word 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66
-	.word 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9
-	.word 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605
-	.word 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8
-	.word 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b
-	.word 0x2d02ef8d
-
-GPIO_BASE:
-	.word 0xfffce000
-GPIO_DIRECTION:
-	.word 0x0000ffe7
 
 .end

board/overo/overo.c

@@ -100,13 +100,13 @@ static void setup_net_chip(void)
 	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 
 	/* Configure GPMC registers */
-	writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
+	writel(NET_LAN9221_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
-	writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
+	writel(NET_LAN9221_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
-	writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
+	writel(NET_LAN9221_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
-	writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
+	writel(NET_LAN9221_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
-	writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
+	writel(NET_LAN9221_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
-	writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
+	writel(NET_LAN9221_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
-	writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
+	writel(NET_LAN9221_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
 
 	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
 	writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);

board/overo/overo.h

@@ -33,6 +33,15 @@ const omap3_sysinfo sysinfo = {
 #endif
 };
 
+/* GPMC CS 5 connected to an SMSC LAN9221 ethernet controller */
+#define NET_LAN9221_GPMC_CONFIG1    0x00001000
+#define NET_LAN9221_GPMC_CONFIG2    0x00080701
+#define NET_LAN9221_GPMC_CONFIG3    0x00020201
+#define NET_LAN9221_GPMC_CONFIG4    0x08030703
+#define NET_LAN9221_GPMC_CONFIG5    0x00060908
+#define NET_LAN9221_GPMC_CONFIG6    0x87030000
+#define NET_LAN9221_GPMC_CONFIG7    0x00000f6c
+
 /*
  * IEN  - Input Enable
  * IDIS - Input Disable

common/cmd_bootm.c

@@ -352,6 +352,7 @@ static int bootm_load_os(image_info_t os, ulong *load_end, int boot_progress)
 		*load_end = load + image_len;
 		puts("OK\n");
 		break;
+#ifdef CONFIG_GZIP
 	case IH_COMP_GZIP:
 		printf ("   Uncompressing %s ... ", type_name);
 		if (gunzip ((void *)load, unc_len,
@@ -365,6 +366,7 @@ static int bootm_load_os(image_info_t os, ulong *load_end, int boot_progress)
 
 		*load_end = load + image_len;
 		break;
+#endif /* CONFIG_GZIP */
 #ifdef CONFIG_BZIP2
 	case IH_COMP_BZIP2:
 		printf ("   Uncompressing %s ... ", type_name);

common/cmd_jffs2.c

@@ -406,8 +406,6 @@ int mtdparts_init(void)
 		part->offset = 0x00000000;
 #endif
 
-		part->sector_size = get_part_sector_size(id, part);
-
 		part->dev = current_mtd_dev;
 		INIT_LIST_HEAD(&part->link);
 
@@ -415,6 +413,8 @@ int mtdparts_init(void)
 		if (part->size == SIZE_REMAINING)
 			part->size = id->size - part->offset;
 
+		part->sector_size = get_part_sector_size(id, part);
+
 		DEBUGF("part  : name = %s, size = 0x%08lx, offset = 0x%08lx\n",
 				part->name, part->size, part->offset);
 

common/cmd_mp.c

@@ -46,6 +46,8 @@ cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 			cpu_reset(cpuid);
 		} else if (strncmp(argv[2], "status", 6) == 0) {
 			cpu_status(cpuid);
+		} else if (strncmp(argv[2], "disable", 7) == 0) {
+			return cpu_disable(cpuid);
 		} else {
 			cmd_usage(cmdtp);
 			return 1;
@@ -86,6 +88,7 @@ U_BOOT_CMD(
 	"Multiprocessor CPU boot manipulation and release",
 	    "<num> reset                 - Reset cpu <num>\n"
 	"cpu <num> status                - Status of cpu <num>\n"
+	"cpu <num> disable               - Disable cpu <num>\n"
 	"cpu <num> release <addr> [args] - Release cpu <num> at <addr> with [args]"
 #ifdef CPU_ARCH_HELP
 	"\n"

common/cmd_ximg.c

@@ -31,8 +31,17 @@
 #include <common.h>
 #include <command.h>
 #include <image.h>
+#include <watchdog.h>
+#if defined(CONFIG_BZIP2)
+#include <bzlib.h>
+#endif
 #include <asm/byteorder.h>
 
+#ifndef CONFIG_SYS_XIMG_LEN
+/* use 8MByte as default max gunzip size */
+#define CONFIG_SYS_XIMG_LEN	0x800000
+#endif
+
 int
 do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
@@ -50,6 +59,8 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	const void	*fit_data;
 	size_t		fit_len;
 #endif
+	uint		unc_len = CONFIG_SYS_XIMG_LEN;
+	uint8_t		comp;
 
 	verify = getenv_yesno ("verify");
 
@@ -92,8 +103,10 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 			return 1;
 		}
 
-		if (image_get_comp (hdr) != IH_COMP_NONE) {
+		comp = image_get_comp (hdr);
-			printf("Wrong Compression Type for %s command\n",
+		if ((comp != IH_COMP_NONE) && (argc < 4)) {
+			printf("Must specify load address for %s command "
+					"with compressed image\n",
 					cmdtp->name);
 			return 1;
 		}
@@ -138,9 +151,11 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 			return 1;
 		}
 
-		if (fit_image_check_comp (fit_hdr, noffset, IH_COMP_NONE)) {
+		if (fit_image_check_comp (fit_hdr, noffset, IH_COMP_NONE)
-			printf("Wrong Compression Type for %s command\n",
+		    && (argc < 4)) {
-					cmdtp->name);
+			printf("Must specify load address for %s command "
+				"with compressed image\n",
+				cmdtp->name);
 			return 1;
 		}
 
@@ -153,11 +168,18 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 		}
 
 		/* get subimage data address and length */
-		if (fit_image_get_data (fit_hdr, noffset, &fit_data, &fit_len)) {
+		if (fit_image_get_data (fit_hdr, noffset,
+					&fit_data, &fit_len)) {
 			puts ("Could not find script subimage data\n");
 			return 1;
 		}
 
+		if (fit_image_get_comp (fit_hdr, noffset, &comp)) {
+			puts ("Could not find script subimage "
+				"compression type\n");
+			return 1;
+		}
+
 		data = (ulong)fit_data;
 		len = (ulong)fit_len;
 		break;
@@ -168,7 +190,63 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	}
 
 	if (argc > 3) {
-		memcpy((char *) dest, (char *) data, len);
+		switch (comp) {
+		case IH_COMP_NONE:
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+			{
+				size_t l = len;
+				size_t tail;
+				void *to = (void *) dest;
+				void *from = (void *)data;
+
+				printf ("   Loading part %d ... ", part);
+
+				while (l > 0) {
+					tail = (l > CHUNKSZ) ? CHUNKSZ : l;
+					WATCHDOG_RESET();
+					memmove (to, from, tail);
+					to += tail;
+					from += tail;
+					l -= tail;
+				}
+			}
+#else	/* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */
+			printf ("   Loading part %d ... ", part);
+			memmove ((char *) dest, (char *)data, len);
+#endif	/* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
+			break;
+		case IH_COMP_GZIP:
+			printf ("   Uncompressing part %d ... ", part);
+			if (gunzip ((void *) dest, unc_len,
+				    (uchar *) data, &len) != 0) {
+				puts ("GUNZIP ERROR - image not loaded\n");
+				return 1;
+			}
+			break;
+#if defined(CONFIG_BZIP2)
+		case IH_COMP_BZIP2:
+			printf ("   Uncompressing part %d ... ", part);
+			/*
+			 * If we've got less than 4 MB of malloc() space,
+			 * use slower decompression algorithm which requires
+			 * at most 2300 KB of memory.
+			 */
+			i = BZ2_bzBuffToBuffDecompress
+				((char*)ntohl(hdr->ih_load),
+				 &unc_len, (char *)data, len,
+				 CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0);
+			if (i != BZ_OK) {
+				printf ("BUNZIP2 ERROR %d - "
+					"image not loaded\n", i);
+				return 1;
+			}
+			break;
+#endif /* CONFIG_BZIP2 */
+		default:
+			printf ("Unimplemented compression type %d\n", comp);
+			return 1;
+		}
+		puts ("OK\n");
 	}
 
 	sprintf(pbuf, "%8lx", data);

common/image.c

@@ -140,6 +140,7 @@ static table_entry_t uimage_type[] = {
 	{	IH_TYPE_STANDALONE, "standalone", "Standalone Program", },
 	{	IH_TYPE_FLATDT,     "flat_dt",    "Flat Device Tree",	},
 	{	IH_TYPE_KWBIMAGE,   "kwbimage",   "Kirkwood Boot Image",},
+	{	IH_TYPE_IMXIMAGE,   "imximage",   "Freescale i.MX Boot Image",},
 	{	-1,		    "",		  "",			},
 };
 

cpu/74xx_7xx/config.mk

@@ -21,6 +21,6 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -meabi
 
 PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -mstring

cpu/74xx_7xx/start.S

@@ -63,7 +63,7 @@
 /*
  * Set up GOT: Global Offset Table
  *
- * Use r14 to access the GOT
+ * Use r12 to access the GOT
  */
 	START_GOT
 	GOT_ENTRY(_GOT2_TABLE_)
@@ -132,28 +132,15 @@ Alignment:
 	mfspr	r5,DSISR
 	stw	r5,_DSISR(r21)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_Alignment:
-	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
 
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
 	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
+		MSR_KERNEL, COPY_EE)
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_ProgramCheck:
-	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
 
 	/* No FPU on MPC8xx.  This exception is not supposed to happen.
 	*/
@@ -612,6 +599,7 @@ relocate_code:
 	mr	r9,  r4		/* Save copy of Global Data pointer	*/
 	mr	r10, r5		/* Save copy of Destination Address	*/
 
+	GET_GOT
 	mr	r3,  r5				/* Destination Address	*/
 	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
 	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
@@ -629,7 +617,7 @@ relocate_code:
 	sub	r15, r10, r4
 
 	/* First our own GOT */
-	add	r14, r14, r15
+	add	r12, r12, r15
 	/* then the one used by the C code */
 	add	r30, r30, r15
 
@@ -704,7 +692,7 @@ in_ram:
 	bl	board_init_ecc
 #endif
 	/*
-	 * Relocation Function, r14 point to got2+0x8000
+	 * Relocation Function, r12 point to got2+0x8000
 	 *
 	 * Adjust got2 pointers, no need to check for 0, this code
 	 * already puts a few entries in the table.
@@ -778,6 +766,8 @@ in_ram:
 	 */
 	.globl	trap_init
 trap_init:
+	mflr	r4			/* save link register		*/
+	GET_GOT
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 
@@ -785,8 +775,6 @@ trap_init:
 
 	cmplw	0, r7, r8
 	bgelr				/* return if r7>=r8 - just in case */
-
-	mflr	r4			/* save link register		*/
 1:
 	lwz	r0, 0(r7)
 	stw	r0, 0(r9)
@@ -837,23 +825,6 @@ trap_init:
 	mtlr	r4			/* restore link register	*/
 	blr
 
-	/*
-	 * Function: relocate entries for one exception vector
-	 */
-trap_reloc:
-	lwz	r0, 0(r7)		/* hdlr ...			*/
-	add	r0, r0, r3		/*  ... += dest_addr		*/
-	stw	r0, 0(r7)
-
-	lwz	r0, 4(r7)		/* int_return ...		*/
-	add	r0, r0, r3		/*  ... += dest_addr		*/
-	stw	r0, 4(r7)
-
-	sync
-	isync
-
-	blr
-
 #ifdef CONFIG_SYS_INIT_RAM_LOCK
 lock_ram_in_cache:
 	/* Allocate Initial RAM in data cache.

cpu/arm920t/ep93xx/Makefile

@@ -0,0 +1,56 @@
+#
+# Cirrus Logic EP93xx CPU-specific Makefile
+#
+# Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+#
+# Copyright (C) 2004, 2005
+# Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+#
+# Copyright (C) 2006
+# Dominic Rath <Dominic.Rath@gmx.de>
+#
+# Based on an original Makefile, which is
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+# for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS   = cpu.o led.o speed.o timer.o
+SOBJS   = lowlevel_init.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS    := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:    $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+

cpu/arm920t/ep93xx/cpu.c

@@ -0,0 +1,51 @@
+/*
+ * Cirrus Logic EP93xx CPU-specific support.
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.	See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
+extern void reset_cpu(ulong addr)
+{
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+	uint32_t value;
+
+	/* Unlock DeviceCfg and set SWRST */
+	writel(0xAA, &syscon->sysswlock);
+	value = readl(&syscon->devicecfg);
+	value |= SYSCON_DEVICECFG_SWRST;
+	writel(value, &syscon->devicecfg);
+
+	/* Unlock DeviceCfg and clear SWRST */
+	writel(0xAA, &syscon->sysswlock);
+	value = readl(&syscon->devicecfg);
+	value &= ~SYSCON_DEVICECFG_SWRST;
+	writel(value, &syscon->devicecfg);
+
+	/* Dying... */
+	while (1)
+		; /* noop */
+}

cpu/arm920t/ep93xx/led.c

@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2010, 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/io.h>
+#include <asm/arch/ep93xx.h>
+#include <config.h>
+#include <status_led.h>
+
+static uint8_t saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF};
+static uint32_t gpio_pin[2] = {1 << STATUS_LED_GREEN,
+			       1 << STATUS_LED_RED};
+
+inline void switch_LED_on(uint8_t led)
+{
+	register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
+
+	writel(readl(&gpio->pedr) | gpio_pin[led], &gpio->pedr);
+	saved_state[led] = STATUS_LED_ON;
+}
+
+inline void switch_LED_off(uint8_t led)
+{
+	register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
+
+	writel(readl(&gpio->pedr) & ~gpio_pin[led], &gpio->pedr);
+	saved_state[led] = STATUS_LED_OFF;
+}
+
+void red_LED_on(void)
+{
+	switch_LED_on(STATUS_LED_RED);
+}
+
+void red_LED_off(void)
+{
+	switch_LED_off(STATUS_LED_RED);
+}
+
+void green_LED_on(void)
+{
+	switch_LED_on(STATUS_LED_GREEN);
+}
+
+void green_LED_off(void)
+{
+	switch_LED_off(STATUS_LED_GREEN);
+}
+
+void __led_init(led_id_t mask, int state)
+{
+	__led_set(mask, state);
+}
+
+void __led_toggle(led_id_t mask)
+{
+	if (STATUS_LED_RED == mask) {
+		if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
+			red_LED_off();
+		else
+			red_LED_on();
+	} else if (STATUS_LED_GREEN == mask) {
+		if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
+			green_LED_off();
+		else
+			green_LED_on();
+	}
+}
+
+void __led_set(led_id_t mask, int state)
+{
+	if (STATUS_LED_RED == mask) {
+		if (STATUS_LED_ON == state)
+			red_LED_on();
+		else
+			red_LED_off();
+	} else if (STATUS_LED_GREEN == mask) {
+		if (STATUS_LED_ON == state)
+			green_LED_on();
+		else
+			green_LED_off();
+	}
+}

cpu/arm920t/ep93xx/lowlevel_init.S

@@ -0,0 +1,65 @@
+/*
+ * Low-level initialization for EP93xx
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <version.h>
+#include <asm/arch/ep93xx.h>
+
+.globl lowlevel_init
+lowlevel_init:
+	/* backup return address */
+	ldr r1, =SYSCON_SCRATCH0
+	str lr, [r1]
+
+	/* Turn on both LEDs */
+	bl red_LED_on
+	bl green_LED_on
+
+	/* Configure flash wait states before we switch to the PLL */
+	bl flash_cfg
+
+	/* Set up PLL */
+	bl pll_cfg
+
+	/* Turn off the Green LED and leave the Red LED on */
+	bl green_LED_off
+
+	/* Setup SDRAM */
+	bl sdram_cfg
+
+	/* Turn on Green LED, Turn off the Red LED */
+	bl green_LED_on
+	bl red_LED_off
+
+	/* FIXME: we use async mode for now */
+	mrc p15, 0, r0, c1, c0, 0
+	orr r0, r0, #0xc0000000
+	mcr p15, 0, r0, c1, c0, 0
+
+	/* restore return address */
+	ldr r1, =SYSCON_SCRATCH0
+	ldr lr, [r1]
+
+	mov pc, lr

cpu/arm920t/ep93xx/speed.c

@@ -0,0 +1,110 @@
+/*
+ * Cirrus Logic EP93xx PLL support.
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+#include <div64.h>
+
+/*
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ *
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+
+/*
+ * return the PLL output frequency
+ *
+ * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
+ * / (X2IPD + 1) / 2^PS
+ */
+static ulong get_PLLCLK(uint32_t *pllreg)
+{
+	uint8_t i;
+	const uint32_t clkset = readl(pllreg);
+	uint64_t rate = CONFIG_SYS_CLK_FREQ;
+	rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
+	rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
+	do_div(rate, (clkset  & 0x1f) + 1);			/* X2IPD */
+	for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
+		rate >>= 1;
+
+	return (ulong)rate;
+}
+
+/* return FCLK frequency */
+ulong get_FCLK()
+{
+	const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+	const uint32_t clkset1 = readl(&syscon->clkset1);
+	const uint8_t fclk_div =
+		fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7];
+	const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div;
+
+	return fclk_rate;
+}
+
+/* return HCLK frequency */
+ulong get_HCLK(void)
+{
+	const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+	const uint32_t clkset1 = readl(&syscon->clkset1);
+	const uint8_t hclk_div =
+		hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7];
+	const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div;
+
+	return hclk_rate;
+}
+
+/* return PCLK frequency */
+ulong get_PCLK(void)
+{
+	const uint8_t pclk_divisors[] = { 1, 2, 4, 8 };
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+	const uint32_t clkset1 = readl(&syscon->clkset1);
+	const uint8_t pclk_div =
+		pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3];
+	const ulong pclk_rate = get_HCLK() / pclk_div;
+
+	return pclk_rate;
+}
+
+/* return UCLK frequency */
+ulong get_UCLK(void)
+{
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+	ulong uclk_rate;
+
+	const uint32_t value = readl(&syscon->pwrcnt);
+	if (value & SYSCON_PWRCNT_UART_BAUD)
+		uclk_rate = CONFIG_SYS_CLK_FREQ;
+	else
+		uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
+
+	return uclk_rate;
+}

cpu/arm920t/ep93xx/timer.c

@@ -0,0 +1,168 @@
+/*
+ * Cirrus Logic EP93xx timer support.
+ *
+ * Copyright (C) 2009, 2010
+ * Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support,
+ * author unknown.
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+#define TIMER_CLKSEL	(1 << 3)
+#define TIMER_MODE	(1 << 6)
+#define TIMER_ENABLE	(1 << 7)
+
+#define TIMER_FREQ	508469
+#define TIMER_LOAD_VAL	(TIMER_FREQ / CONFIG_SYS_HZ)
+
+static ulong timestamp;
+static ulong lastdec;
+
+static inline unsigned long clk_to_systicks(unsigned long clk_ticks)
+{
+	unsigned long sys_ticks = (clk_ticks * CONFIG_SYS_HZ) / TIMER_FREQ;
+
+	return sys_ticks;
+}
+
+static inline unsigned long usecs_to_ticks(unsigned long usecs)
+{
+	unsigned long ticks;
+
+	if (usecs >= 1000) {
+		ticks = usecs / 1000;
+		ticks *= (TIMER_LOAD_VAL * CONFIG_SYS_HZ);
+		ticks /= 1000;
+	} else {
+		ticks = usecs * TIMER_LOAD_VAL * CONFIG_SYS_HZ;
+		ticks /= (1000 * 1000);
+	}
+
+	return ticks;
+}
+
+static inline unsigned long read_timer(void)
+{
+	struct timer_regs *timer = (struct timer_regs *)TIMER_BASE;
+
+	return readl(&timer->timer3.value);
+}
+
+/*
+ * timer without interrupts
+ */
+unsigned long long get_ticks(void)
+{
+	const unsigned long now = read_timer();
+
+	if (lastdec >= now) {
+		/* normal mode */
+		timestamp += lastdec - now;
+	} else {
+		/* we have an overflow ... */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	}
+
+	lastdec = now;
+
+	return timestamp;
+}
+
+unsigned long get_timer_masked(void)
+{
+	return clk_to_systicks(get_ticks());
+}
+
+unsigned long get_timer(unsigned long base)
+{
+	return get_timer_masked() - base;
+}
+
+void reset_timer_masked(void)
+{
+	lastdec = read_timer();
+	timestamp = 0;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+void set_timer(unsigned long t)
+{
+	timestamp = t;
+}
+
+void __udelay(unsigned long usec)
+{
+	const unsigned long ticks = usecs_to_ticks(usec);
+	const unsigned long target = clk_to_systicks(ticks) + get_timer(0);
+
+	while (get_timer_masked() < target)
+		/* noop */;
+}
+
+void udelay_masked(unsigned long usec)
+{
+	const unsigned long ticks = usecs_to_ticks(usec);
+	const unsigned long target = clk_to_systicks(ticks) + get_timer(0);
+
+	reset_timer_masked();
+
+	while (get_timer_masked() < target)
+		/* noop */;
+}
+
+int timer_init(void)
+{
+	struct timer_regs *timer = (struct timer_regs *)TIMER_BASE;
+
+	/* use timer 3 with 508KHz and free running */
+	writel(TIMER_CLKSEL, &timer->timer3.control);
+
+	/* auto load, manual update of Timer 3 */
+	lastdec = TIMER_LOAD_VAL;
+	writel(TIMER_LOAD_VAL, &timer->timer3.load);
+
+	/* Enable the timer and periodic mode */
+	writel(TIMER_ENABLE | TIMER_MODE | TIMER_CLKSEL,
+		&timer->timer3.control);
+
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+unsigned long get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}

cpu/arm920t/ep93xx/u-boot.lds

@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+		/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
+	  . = 0x1000;
+	  LONG(0x53555243)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

cpu/mpc512x/config.mk

@@ -19,7 +19,7 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -meabi
 
 PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \
 			-ffixed-r2 -msoft-float -mcpu=603e

cpu/mpc512x/cpu.c

@@ -66,9 +66,10 @@ int checkcpu (void)
 	default:
 		puts ("unknown ");
 	}
-	printf ("at %s MHz, CSB at %s MHz\n",
+	printf ("at %s MHz, CSB at %s MHz (RSR=0x%04lx)\n",
 		strmhz(buf1, clock),
-		strmhz(buf2, gd->csb_clk) );
+		strmhz(buf2, gd->csb_clk),
+		gd->reset_status & 0xffff);
 	return 0;
 }
 

cpu/mpc512x/start.S

@@ -65,7 +65,7 @@
 /*
  * Set up GOT: Global Offset Table
  *
- * Use r14 to access the GOT
+ * Use r12 to access the GOT
  */
 	START_GOT
 	GOT_ENTRY(_GOT2_TABLE_)
@@ -127,30 +127,15 @@ Alignment:
 	mfspr	r5,DSISR
 	stw	r5,_DSISR(r21)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
-	rlwimi	r20,r23,0,25,25		/* copy IP bit from saved MSR */
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_Alignment:
-	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
 
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
 	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
+		MSR_KERNEL, COPY_EE)
-	rlwimi	r20,r23,0,25,25		/* copy IP bit from saved MSR */
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_ProgramCheck:
-	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
 
 /* Floating Point Unit unavailable exception */
 	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
@@ -501,6 +486,7 @@ relocate_code:
 	mr	r9,  r4		/* Save copy of Global Data pointer */
 	mr	r10, r5		/* Save copy of Destination Address */
 
+	GET_GOT
 	mr	r3,  r5				/* Destination Address */
 	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address */
 	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
@@ -519,7 +505,7 @@ relocate_code:
 	sub	r15, r10, r4
 
 	/* First our own GOT */
-	add	r14, r14, r15
+	add	r12, r12, r15
 	/* then the one used by the C code */
 	add	r30, r30, r15
 
@@ -599,7 +585,7 @@ relocate_code:
 
 in_ram:
 	/*
-	 * Relocation Function, r14 point to got2+0x8000
+	 * Relocation Function, r12 point to got2+0x8000
 	 *
 	 * Adjust got2 pointers, no need to check for 0, this code
 	 * already puts a few entries in the table.
@@ -663,6 +649,8 @@ clear_bss:
 	 */
 	.globl	trap_init
 trap_init:
+	mflr	r4		/* save link register */
+	GET_GOT
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 
@@ -670,8 +658,6 @@ trap_init:
 
 	cmplw	0, r7, r8
 	bgelr			/* return if r7>=r8 - just in case */
-
-	mflr	r4		/* save link register */
 1:
 	lwz	r0, 0(r7)
 	stw	r0, 0(r9)
@@ -723,17 +709,3 @@ trap_init:
 
 	mtlr	r4			/* restore link register    */
 	blr
-
-	/*
-	 * Function: relocate entries for one exception vector
-	 */
-trap_reloc:
-	lwz	r0, 0(r7)		/* hdlr ...		*/
-	add	r0, r0, r3		/*  ... += dest_addr	*/
-	stw	r0, 0(r7)
-
-	lwz	r0, 4(r7)		/* int_return ...	*/
-	add	r0, r0, r3		/*  ... += dest_addr	*/
-	stw	r0, 4(r7)
-
-	blr

cpu/mpc5xx/config.mk

@@ -28,7 +28,7 @@
 #
 
 
-PLATFORM_RELFLAGS +=	-fPIC -ffixed-r14 -meabi
+PLATFORM_RELFLAGS +=	-fPIC -meabi
 
 PLATFORM_CPPFLAGS +=	-DCONFIG_5xx -ffixed-r2 -mpowerpc -msoft-float
 

cpu/mpc5xx/start.S

@@ -56,7 +56,7 @@
 /*
  * Set up GOT: Global Offset Table
  *
- * Use r14 to access the GOT
+ * Use r12 to access the GOT
  */
 	START_GOT
 	GOT_ENTRY(_GOT2_TABLE_)
@@ -217,28 +217,15 @@ Alignment:
 	mfspr	r5,DSISR
 	stw	r5,_DSISR(r21)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_Alignment:
-	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
 
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
 	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
+		MSR_KERNEL, COPY_EE)
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_ProgramCheck:
-	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
 
 	/* FPU on MPC5xx available. We will use it later.
 	*/
@@ -385,6 +372,7 @@ relocate_code:
 	mr	r9,  r4		/* Save copy of global data pointer in SRAM */
 	mr	r10, r5		/* Save copy of monitor destination Address in SRAM */
 
+	GET_GOT
 	mr	r3,  r5				/* Destination Address	*/
 	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
 	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
@@ -401,7 +389,7 @@ relocate_code:
 	sub	r15, r10, r4
 
 	/* First our own GOT */
-	add	r14, r14, r15
+	add	r12, r12, r15
 	/* the the one used by the C code */
 	add	r30, r30, r15
 
@@ -446,7 +434,7 @@ relocate_code:
 in_ram:
 
 	/*
-	 * Relocation Function, r14 point to got2+0x8000
+	 * Relocation Function, r12 point to got2+0x8000
 	 *
 	 * Adjust got2 pointers, no need to check for 0, this code
 	 * already puts a few entries in the table.
@@ -510,6 +498,8 @@ clear_bss:
 	 */
 	.globl	trap_init
 trap_init:
+	mflr	r4			/* save link register		*/
+	GET_GOT
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 
@@ -517,8 +507,6 @@ trap_init:
 
 	cmplw	0, r7, r8
 	bgelr				/* return if r7>=r8 - just in case */
-
-	mflr	r4			/* save link register		*/
 1:
 	lwz	r0, 0(r7)
 	stw	r0, 0(r9)
@@ -563,24 +551,6 @@ trap_init:
 	mtlr	r4			/* restore link register	*/
 	blr
 
-	/*
-	 * Function: relocate entries for one exception vector
-	 */
-trap_reloc:
-	lwz	r0, 0(r7)		/* hdlr ...			*/
-	add	r0, r0, r3		/*  ... += dest_addr		*/
-	stw	r0, 0(r7)
-
-	lwz	r0, 4(r7)		/* int_return ...		*/
-	add	r0, r0, r3		/*  ... += dest_addr		*/
-	stw	r0, 4(r7)
-
-	sync
-	isync
-
-	blr
-
-
 #if defined(CONFIG_PATI)
 /* Program the PLL */
 pll_prog_code_start:

cpu/mpc5xxx/config.mk

@@ -21,7 +21,7 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -meabi
 
 PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 \
 		     -mstring -mcpu=603e -mmultiple

cpu/mpc5xxx/cpu.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2003
+ * (C) Copyright 2000-2010
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -192,3 +192,21 @@ int cpu_eth_init(bd_t *bis)
 	return mpc5xxx_fec_initialize(bis);
 }
 #endif
+
+#if defined(CONFIG_WATCHDOG)
+void watchdog_reset(void)
+{
+	int re_enable = disable_interrupts();
+	reset_5xxx_watchdog();
+	if (re_enable) enable_interrupts();
+}
+
+void reset_5xxx_watchdog(void)
+{
+	volatile struct mpc5xxx_gpt *gpt0 =
+		(struct mpc5xxx_gpt *) MPC5XXX_GPT;
+
+	/* Trigger TIMER_0 by writing A5 to OCPW */
+	clrsetbits_be32(&gpt0->emsr, 0xff000000, 0xa5000000);
+}
+#endif	/* CONFIG_WATCHDOG */

cpu/mpc5xxx/cpu_init.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2009
+ * (C) Copyright 2000-2010
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -24,6 +24,7 @@
 #include <common.h>
 #include <mpc5xxx.h>
 #include <asm/io.h>
+#include <watchdog.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -45,6 +46,8 @@ void cpu_init_f (void)
 		(struct mpc5xxx_gpio *) MPC5XXX_GPIO;
 	volatile struct mpc5xxx_xlb *xlb =
 		(struct mpc5xxx_xlb *) MPC5XXX_XLBARB;
+	volatile struct mpc5xxx_gpt *gpt0 =
+		(struct mpc5xxx_gpt *) MPC5XXX_GPT;
 	unsigned long addecr = (1 << 25); /* Boot_CS */
 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_MGT5100)
 	addecr |= (1 << 22); /* SDRAM enable */
@@ -206,6 +209,15 @@ void cpu_init_f (void)
 	/* Enable piplining */
 	clrbits_be32(&xlb->config, (1 << 31));
 # endif
+
+#if defined(CONFIG_WATCHDOG)
+	/* Charge the watchdog timer - prescaler = 64k, count = 64k*/
+	out_be32(&gpt0->cir, 0x0000ffff);
+	out_be32(&gpt0->emsr, 0x9004);	/* wden|ce|timer_ms */
+
+	reset_5xxx_watchdog();
+#endif /* CONFIG_WATCHDOG */
+
 #endif	/* CONFIG_MPC5200 */
 }
 

cpu/mpc5xxx/start.S

@@ -56,7 +56,7 @@
 /*
  * Set up GOT: Global Offset Table
  *
- * Use r14 to access the GOT
+ * Use r12 to access the GOT
  */
 	START_GOT
 	GOT_ENTRY(_GOT2_TABLE_)
@@ -215,30 +215,15 @@ Alignment:
 	mfspr	r5,DSISR
 	stw	r5,_DSISR(r21)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
-	rlwimi	r20,r23,0,25,25		/* copy IP bit from saved MSR */
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_Alignment:
-	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
 
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
 	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
+		MSR_KERNEL, COPY_EE)
-	rlwimi	r20,r23,0,25,25		/* copy IP bit from saved MSR */
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_ProgramCheck:
-	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
 
 	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 
@@ -582,6 +567,7 @@ relocate_code:
 	mr	r9,  r4		/* Save copy of Global Data pointer	*/
 	mr	r10, r5		/* Save copy of Destination Address	*/
 
+	GET_GOT
 	mr	r3,  r5				/* Destination Address	*/
 	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
 	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
@@ -599,7 +585,7 @@ relocate_code:
 	sub	r15, r10, r4
 
 	/* First our own GOT */
-	add	r14, r14, r15
+	add	r12, r12, r15
 	/* then the one used by the C code */
 	add	r30, r30, r15
 
@@ -672,7 +658,7 @@ relocate_code:
 in_ram:
 
 	/*
-	 * Relocation Function, r14 point to got2+0x8000
+	 * Relocation Function, r12 point to got2+0x8000
 	 *
 	 * Adjust got2 pointers, no need to check for 0, this code
 	 * already puts a few entries in the table.
@@ -737,6 +723,8 @@ clear_bss:
 	 */
 	.globl	trap_init
 trap_init:
+	mflr	r4			/* save link register		*/
+	GET_GOT
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 
@@ -744,8 +732,6 @@ trap_init:
 
 	cmplw	0, r7, r8
 	bgelr				/* return if r7>=r8 - just in case */
-
-	mflr	r4			/* save link register		*/
 1:
 	lwz	r0, 0(r7)
 	stw	r0, 0(r9)
@@ -797,17 +783,3 @@ trap_init:
 
 	mtlr	r4			/* restore link register    */
 	blr
-
-	/*
-	 * Function: relocate entries for one exception vector
-	 */
-trap_reloc:
-	lwz	r0, 0(r7)		/* hdlr ...			*/
-	add	r0, r0, r3		/*  ... += dest_addr		*/
-	stw	r0, 0(r7)
-
-	lwz	r0, 4(r7)		/* int_return ...		*/
-	add	r0, r0, r3		/*  ... += dest_addr		*/
-	stw	r0, 4(r7)
-
-	blr

cpu/mpc8220/config.mk

@@ -21,7 +21,7 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -meabi
 
 PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 \
 		     -mstring -mcpu=603e -mmultiple

cpu/mpc8220/start.S

@@ -55,7 +55,7 @@
 /*
  * Set up GOT: Global Offset Table
  *
- * Use r14 to access the GOT
+ * Use r12 to access the GOT
  */
 	START_GOT
 	GOT_ENTRY(_GOT2_TABLE_)
@@ -176,30 +176,15 @@ Alignment:
 	mfspr	r5,DSISR
 	stw	r5,_DSISR(r21)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
-	rlwimi	r20,r23,0,16,16	    /* copy EE bit from saved MSR */
-	rlwimi	r20,r23,0,25,25	    /* copy IP bit from saved MSR */
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_Alignment:
-	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
 
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
 	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
-	rlwimi	r20,r23,0,16,16	    /* copy EE bit from saved MSR */
+		MSR_KERNEL, COPY_EE)
-	rlwimi	r20,r23,0,25,25	    /* copy IP bit from saved MSR */
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_ProgramCheck:
-	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
 
 	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 
@@ -547,6 +532,7 @@ relocate_code:
 	mr	r9,  r4	    /* Save copy of Global Data pointer */
 	mr	r10, r5	    /* Save copy of Destination Address */
 
+	GET_GOT
 	mr	r3,  r5	    /* Destination Address		*/
 	lis	r4, CONFIG_SYS_MONITOR_BASE@h	/* Source Address	*/
 	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
@@ -564,7 +550,7 @@ relocate_code:
 	sub	r15, r10, r4
 
 	/* First our own GOT */
-	add	r14, r14, r15
+	add	r12, r12, r15
 	/* then the one used by the C code */
 	add	r30, r30, r15
 
@@ -637,7 +623,7 @@ relocate_code:
 in_ram:
 
 	/*
-	 * Relocation Function, r14 point to got2+0x8000
+	 * Relocation Function, r12 point to got2+0x8000
 	 *
 	 * Adjust got2 pointers, no need to check for 0, this code
 	 * already puts a few entries in the table.
@@ -702,6 +688,8 @@ clear_bss:
 	 */
 	.globl	trap_init
 trap_init:
+	mflr	r4	    /* save link register		*/
+	GET_GOT
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 
@@ -709,8 +697,6 @@ trap_init:
 
 	cmplw	0, r7, r8
 	bgelr		    /* return if r7>=r8 - just in case	*/
-
-	mflr	r4	    /* save link register		*/
 1:
 	lwz	r0, 0(r7)
 	stw	r0, 0(r9)
@@ -762,17 +748,3 @@ trap_init:
 
 	mtlr	r4		    /* restore link register	    */
 	blr
-
-	/*
-	 * Function: relocate entries for one exception vector
-	 */
-trap_reloc:
-	lwz	r0, 0(r7)	    /* hdlr ...			    */
-	add	r0, r0, r3	    /*	... += dest_addr	    */
-	stw	r0, 0(r7)
-
-	lwz	r0, 4(r7)	    /* int_return ...		    */
-	add	r0, r0, r3	    /*	... += dest_addr	    */
-	stw	r0, 4(r7)
-
-	blr

cpu/mpc824x/config.mk

@@ -21,7 +21,7 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -meabi
 
 PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -mstring -mcpu=603e -msoft-float
 

cpu/mpc824x/start.S

@@ -63,7 +63,7 @@
 /*
  * Set up GOT: Global Offset Table
  *
- * Use r14 to access the GOT
+ * Use r12 to access the GOT
  */
 	START_GOT
 	GOT_ENTRY(_GOT2_TABLE_)
@@ -227,28 +227,15 @@ Alignment:
 	mfspr	r5,DSISR
 	stw	r5,_DSISR(r21)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_Alignment:
-	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
 
 /* Program check exception */
 	. = EXC_OFF_PROGRAM
 ProgramCheck:
 	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
+		MSR_KERNEL, COPY_EE)
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_ProgramCheck:
-	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
 
 	/* No FPU on MPC8xx. This exception is not supposed to happen.
 	*/
@@ -475,6 +462,7 @@ relocate_code:
 	mr	r9,  r4		/* Save copy of Global Data pointer	*/
 	mr	r10, r5		/* Save copy of Destination Address	*/
 
+	GET_GOT
 	mr	r3,  r5				/* Destination Address	*/
 #ifdef CONFIG_SYS_RAMBOOT
 	lis	r4, CONFIG_SYS_SDRAM_BASE@h		/* Source      Address	*/
@@ -497,7 +485,7 @@ relocate_code:
 	sub	r15, r10, r4
 
 	/* First our own GOT */
-	add	r14, r14, r15
+	add	r12, r12, r15
 	/* the the one used by the C code */
 	add	r30, r30, r15
 
@@ -577,7 +565,7 @@ relocate_code:
 in_ram:
 
 	/*
-	 * Relocation Function, r14 point to got2+0x8000
+	 * Relocation Function, r12 point to got2+0x8000
 	 *
 	 * Adjust got2 pointers, no need to check for 0, this code
 	 * already puts a few entries in the table.
@@ -642,6 +630,8 @@ clear_bss:
 	 */
 	.globl	trap_init
 trap_init:
+	mflr	r4			/* save link register		*/
+	GET_GOT
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 
@@ -649,8 +639,6 @@ trap_init:
 
 	cmplw	0, r7, r8
 	bgelr				/* return if r7>=r8 - just in case */
-
-	mflr	r4			/* save link register		*/
 1:
 	lwz	r0, 0(r7)
 	stw	r0, 0(r9)
@@ -695,20 +683,6 @@ trap_init:
 	mtlr	r4			/* restore link register	*/
 	blr
 
-	/*
-	 * Function: relocate entries for one exception vector
-	 */
-trap_reloc:
-	lwz	r0, 0(r7)		/* hdlr ...			*/
-	add	r0, r0, r3		/*  ... += dest_addr		*/
-	stw	r0, 0(r7)
-
-	lwz	r0, 4(r7)		/* int_return ...		*/
-	add	r0, r0, r3		/*  ... += dest_addr		*/
-	stw	r0, 4(r7)
-
-	blr
-
 	/* Setup the BAT registers.
 	 */
 setup_bats:

cpu/mpc8260/config.mk

@@ -21,7 +21,7 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -meabi
 
 PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 \
 		     -mstring -mcpu=603e -mmultiple

cpu/mpc8260/start.S

@@ -56,7 +56,7 @@
 /*
  * Set up GOT: Global Offset Table
  *
- * Use r14 to access the GOT
+ * Use r12 to access the GOT
  */
 	START_GOT
 	GOT_ENTRY(_GOT2_TABLE_)
@@ -286,30 +286,15 @@ Alignment:
 	mfspr	r5,DSISR
 	stw	r5,_DSISR(r21)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
-	rlwimi	r20,r23,0,25,25		/* copy IP bit from saved MSR */
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_Alignment:
-	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
 
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
 	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
+		MSR_KERNEL, COPY_EE)
-	rlwimi	r20,r23,0,25,25		/* copy IP bit from saved MSR */
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_ProgramCheck:
-	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
 
 	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 
@@ -665,7 +650,9 @@ init_debug:
 	/* RAM should now be operational */
 
 #define VEC_WRD_CNT	((_end_of_vectors - _start + EXC_OFF_SYS_RESET) / 4)
-
+	mflr	r3
+	GET_GOT
+	mtlr	r3
 	lwz	r3, GOT(_end_of_vectors)
 	rlwinm	r4, r3, 0, 18, 31	/* _end_of_vectors & 0x3FFF	*/
 	lis	r5, VEC_WRD_CNT@h
@@ -807,6 +794,7 @@ relocate_code:
 	mr	r9,  r4		/* Save copy of Global Data pointer	*/
 	mr	r10, r5		/* Save copy of Destination Address	*/
 
+	GET_GOT
 	mr	r3,  r5				/* Destination Address	*/
 	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
 	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
@@ -824,7 +812,7 @@ relocate_code:
 	sub	r15, r10, r4
 
 	/* First our own GOT */
-	add	r14, r14, r15
+	add	r12, r12, r15
 	/* then the one used by the C code */
 	add	r30, r30, r15
 
@@ -897,7 +885,7 @@ relocate_code:
 in_ram:
 
 	/*
-	 * Relocation Function, r14 point to got2+0x8000
+	 * Relocation Function, r12 point to got2+0x8000
 	 *
 	 * Adjust got2 pointers, no need to check for 0, this code
 	 * already puts a few entries in the table.
@@ -973,6 +961,8 @@ clear_bss:
 	 */
 	.globl	trap_init
 trap_init:
+	mflr	r4			/* save link register		*/
+	GET_GOT
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 
@@ -980,8 +970,6 @@ trap_init:
 
 	cmplw	0, r7, r8
 	bgelr				/* return if r7>=r8 - just in case */
-
-	mflr	r4			/* save link register		*/
 1:
 	lwz	r0, 0(r7)
 	stw	r0, 0(r9)
@@ -1033,17 +1021,3 @@ trap_init:
 
 	mtlr	r4			/* restore link register    */
 	blr
-
-	/*
-	 * Function: relocate entries for one exception vector
-	 */
-trap_reloc:
-	lwz	r0, 0(r7)		/* hdlr ...			*/
-	add	r0, r0, r3		/*  ... += dest_addr		*/
-	stw	r0, 0(r7)
-
-	lwz	r0, 4(r7)		/* int_return ...		*/
-	add	r0, r0, r3		/*  ... += dest_addr		*/
-	stw	r0, 4(r7)
-
-	blr

cpu/mpc83xx/config.mk

@@ -20,7 +20,7 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -meabi
 
 PLATFORM_CPPFLAGS += -DCONFIG_MPC83xx -DCONFIG_E300 \
 			-ffixed-r2 -msoft-float

cpu/mpc83xx/start.S

@@ -65,7 +65,7 @@
 /*
  * Set up GOT: Global Offset Table
  *
- * Use r14 to access the GOT
+ * Use r12 to access the GOT
  */
 	START_GOT
 	GOT_ENTRY(_GOT2_TABLE_)
@@ -338,30 +338,15 @@ Alignment:
 	mfspr	r5,DSISR
 	stw	r5,_DSISR(r21)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
-	rlwimi	r20,r23,0,25,25		/* copy IP bit from saved MSR */
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_Alignment:
-	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
 
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
 	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
+		MSR_KERNEL, COPY_EE)
-	rlwimi	r20,r23,0,25,25		/* copy IP bit from saved MSR */
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_ProgramCheck:
-	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
 
 	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 
@@ -845,6 +830,7 @@ relocate_code:
 	mr	r9,  r4		/* Save copy of Global Data pointer */
 	mr	r10, r5		/* Save copy of Destination Address */
 
+	GET_GOT
 	mr	r3,  r5				/* Destination Address */
 	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address */
 	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
@@ -863,7 +849,7 @@ relocate_code:
 	sub	r15, r10, r4
 
 	/* First our own GOT */
-	add	r14, r14, r15
+	add	r12, r12, r15
 	/* then the one used by the C code */
 	add	r30, r30, r15
 
@@ -945,7 +931,7 @@ relocate_code:
 in_ram:
 
 	/*
-	 * Relocation Function, r14 point to got2+0x8000
+	 * Relocation Function, r12 point to got2+0x8000
 	 *
 	 * Adjust got2 pointers, no need to check for 0, this code
 	 * already puts a few entries in the table.
@@ -1025,6 +1011,8 @@ clear_bss:
 	 */
 	.globl	trap_init
 trap_init:
+	mflr	r4		/* save link register */
+	GET_GOT
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 
@@ -1032,8 +1020,6 @@ trap_init:
 
 	cmplw	0, r7, r8
 	bgelr			/* return if r7>=r8 - just in case */
-
-	mflr	r4		/* save link register */
 1:
 	lwz	r0, 0(r7)
 	stw	r0, 0(r9)
@@ -1086,19 +1072,6 @@ trap_init:
 	mtlr	r4			/* restore link register    */
 	blr
 
-	/*
-	 * Function: relocate entries for one exception vector
-	 */
-trap_reloc:
-	lwz	r0, 0(r7)		/* hdlr ...		*/
-	add	r0, r0, r3		/*  ... += dest_addr	*/
-	stw	r0, 0(r7)
-
-	lwz	r0, 4(r7)		/* int_return ...	*/
-	add	r0, r0, r3		/*  ... += dest_addr	*/
-	stw	r0, 4(r7)
-
-	blr
 #endif /* !CONFIG_NAND_SPL */
 
 #ifdef CONFIG_SYS_INIT_RAM_LOCK

cpu/mpc85xx/config.mk

@@ -21,7 +21,7 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -meabi
 
 PLATFORM_CPPFLAGS += -ffixed-r2 -Wa,-me500 -msoft-float -mno-string
 

cpu/mpc85xx/fdt.c

@@ -331,6 +331,23 @@ static void ft_fixup_dpaa_clks(void *blob)
 #define ft_fixup_dpaa_clks(x)
 #endif
 
+#ifdef CONFIG_QE
+static void ft_fixup_qe_snum(void *blob)
+{
+	unsigned int svr;
+
+	svr = mfspr(SPRN_SVR);
+	if (SVR_SOC_VER(svr) == SVR_8569_E) {
+		if(IS_SVR_REV(svr, 1, 0))
+			do_fixup_by_compat_u32(blob, "fsl,qe",
+				"fsl,qe-num-snums", 46, 1);
+		else
+			do_fixup_by_compat_u32(blob, "fsl,qe",
+				"fsl,qe-num-snums", 76, 1);
+	}
+}
+#endif
+
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 	int off;
@@ -367,6 +384,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 		"bus-frequency", gd->lbc_clk, 1);
 #ifdef CONFIG_QE
 	ft_qe_setup(blob);
+	ft_fixup_qe_snum(blob);
 #endif
 
 #ifdef CONFIG_SYS_NS16550

cpu/mpc85xx/mp.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -68,6 +68,36 @@ int cpu_status(int nr)
 	return 0;
 }
 
+#ifdef CONFIG_FSL_CORENET
+int cpu_disable(int nr)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	setbits_be32(&gur->coredisrl, 1 << nr);
+
+	return 0;
+}
+#else
+int cpu_disable(int nr)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	switch (nr) {
+	case 0:
+		setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0);
+		break;
+	case 1:
+		setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1);
+		break;
+	default:
+		printf("Invalid cpu number for disable %d\n", nr);
+		return 1;
+	}
+
+	return 0;
+}
+#endif
+
 static u8 boot_entry_map[4] = {
 	0,
 	BOOT_ENTRY_PIR,

cpu/mpc85xx/speed.c

@@ -80,8 +80,8 @@ void get_sys_info (sys_info_t * sysInfo)
 	freqCC_PLL[2] = sysclk;
 	freqCC_PLL[3] = sysclk;
 
-	sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0xf;
+	sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
-	sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0xf);
+	sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0x1f);
 	freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
 	freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
 	freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
@@ -103,21 +103,21 @@ void get_sys_info (sys_info_t * sysInfo)
 
 #ifdef CONFIG_SYS_DPAA_PME
 	if (rcw_tmp & PME_CLK_SEL)
-		sysInfo->freqPME = sysInfo->freqSystemBus / 2;
-	else
 		sysInfo->freqPME = freqCC_PLL[2] / 2;
+	else
+		sysInfo->freqPME = sysInfo->freqSystemBus / 2;
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 	if (rcw_tmp & FM1_CLK_SEL)
-		sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
-	else
 		sysInfo->freqFMan[0] = freqCC_PLL[2] / 2;
+	else
+		sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
 #if (CONFIG_SYS_NUM_FMAN) == 2
 	if (rcw_tmp & FM2_CLK_SEL)
-		sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
-	else
 		sysInfo->freqFMan[1] = freqCC_PLL[2] / 2;
+	else
+		sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
 #endif
 #endif
 
@@ -170,7 +170,12 @@ void get_sys_info (sys_info_t * sysInfo)
 	}
 #endif
 	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
-#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
+#if defined(CONFIG_FSL_CORENET)
+		/* If this is corenet based SoC, bit-representation
+		 * for four times the clock divider values.
+		 */
+		lcrr_div *= 4;
+#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
     !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
 		/*
 		 * Yes, the entire PQ38 family use the same

cpu/mpc85xx/start.S

@@ -51,7 +51,7 @@
 /*
  * Set up GOT: Global Offset Table
  *
- * Use r14 to access the GOT
+ * Use r12 to access the GOT
  */
 	START_GOT
 	GOT_ENTRY(_GOT2_TABLE_)
@@ -415,28 +415,15 @@ Alignment:
 	mfspr	r5,DSISR
 	stw	r5,_DSISR(r21)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_Alignment:
-	.long	AlignmentException - _start + _START_OFFSET
-	.long	int_return - _start + _START_OFFSET
 
 /* Program check exception */
 	. = 0x0700
 ProgramCheck:
 	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
+		MSR_KERNEL, COPY_EE)
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_ProgramCheck:
-	.long	ProgramCheckException - _start + _START_OFFSET
-	.long	int_return - _start + _START_OFFSET
 
 	/* No FPU on MPC85xx.  This exception is not supposed to happen.
 	*/
@@ -884,6 +871,7 @@ relocate_code:
 	mr	r9,r4		/* Save copy of Init Data pointer	*/
 	mr	r10,r5		/* Save copy of Destination Address	*/
 
+	GET_GOT
 	mr	r3,r5				/* Destination Address	*/
 	lis	r4,CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
 	ori	r4,r4,CONFIG_SYS_MONITOR_BASE@l
@@ -901,7 +889,7 @@ relocate_code:
 	sub	r15,r10,r4
 
 	/* First our own GOT */
-	add	r14,r14,r15
+	add	r12,r12,r15
 	/* the the one used by the C code */
 	add	r30,r30,r15
 
@@ -971,7 +959,7 @@ relocate_code:
 in_ram:
 
 	/*
-	 * Relocation Function, r14 point to got2+0x8000
+	 * Relocation Function, r12 point to got2+0x8000
 	 *
 	 * Adjust got2 pointers, no need to check for 0, this code
 	 * already puts a few entries in the table.
@@ -1037,6 +1025,8 @@ clear_bss:
 	 */
 	.globl	trap_init
 trap_init:
+	mflr	r4			/* save link register		*/
+	GET_GOT
 	lwz	r7,GOT(_start_of_vectors)
 	lwz	r8,GOT(_end_of_vectors)
 
@@ -1044,8 +1034,6 @@ trap_init:
 
 	cmplw	0,r7,r8
 	bgelr				/* return if r7>=r8 - just in case */
-
-	mflr	r4			/* save link register		*/
 1:
 	lwz	r0,0(r7)
 	stw	r0,0(r9)
@@ -1089,20 +1077,6 @@ trap_init:
 	mtlr	r4			/* restore link register	*/
 	blr
 
-	/*
-	 * Function: relocate entries for one exception vector
-	 */
-trap_reloc:
-	lwz	r0,0(r7)		/* hdlr ...			*/
-	add	r0,r0,r3		/*  ... += dest_addr		*/
-	stw	r0,0(r7)
-
-	lwz	r0,4(r7)		/* int_return ...		*/
-	add	r0,r0,r3		/*  ... += dest_addr		*/
-	stw	r0,4(r7)
-
-	blr
-
 .globl unlock_ram_in_cache
 unlock_ram_in_cache:
 	/* invalidate the INIT_RAM section */

cpu/mpc86xx/config.mk

@@ -21,7 +21,7 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -meabi
 
 PLATFORM_CPPFLAGS += -ffixed-r2 -mstring
 PLATFORM_CPPFLAGS += -maltivec -mabi=altivec -msoft-float

cpu/mpc86xx/mp.c

@@ -1,3 +1,25 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
@@ -24,6 +46,26 @@ int cpu_status(int nr)
 	return 0;
 }
 
+int cpu_disable(int nr)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+
+	switch (nr) {
+	case 0:
+		setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU0);
+		break;
+	case 1:
+		setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU1);
+		break;
+	default:
+		printf("Invalid cpu number for disable %d\n", nr);
+		return 1;
+	}
+
+	return 0;
+}
+
 int cpu_release(int nr, int argc, char *argv[])
 {
 	/* dummy function so common/cmd_mp.c will build

cpu/mpc86xx/start.S

@@ -52,7 +52,7 @@
 /*
  * Set up GOT: Global Offset Table
  *
- * Use r14 to access the GOT
+ * Use r12 to access the GOT
  */
 	START_GOT
 	GOT_ENTRY(_GOT2_TABLE_)
@@ -121,28 +121,15 @@ Alignment:
 	mfspr	r5,DSISR
 	stw	r5,_DSISR(r21)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_Alignment:
-	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
 
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
 	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
+		MSR_KERNEL, COPY_EE)
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_ProgramCheck:
-	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
 
 	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 
@@ -643,6 +630,7 @@ relocate_code:
 	mr	r9,  r4		/* Save copy of Global Data pointer	*/
 	mr	r10, r5		/* Save copy of Destination Address	*/
 
+	GET_GOT
 	mr	r3,  r5				/* Destination Address	*/
 	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
 	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
@@ -660,7 +648,7 @@ relocate_code:
 	sub	r15, r10, r4
 
 	/* First our own GOT */
-	add	r14, r14, r15
+	add	r12, r12, r15
 	/* then the one used by the C code */
 	add	r30, r30, r15
 
@@ -721,7 +709,7 @@ relocate_code:
 
 in_ram:
 	/*
-	 * Relocation Function, r14 point to got2+0x8000
+	 * Relocation Function, r12 point to got2+0x8000
 	 *
 	 * Adjust got2 pointers, no need to check for 0, this code
 	 * already puts a few entries in the table.
@@ -788,6 +776,8 @@ in_ram:
 	 */
 	.globl	trap_init
 trap_init:
+	mflr	r4			/* save link register		*/
+	GET_GOT
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 
@@ -795,8 +785,6 @@ trap_init:
 
 	cmplw	0, r7, r8
 	bgelr				/* return if r7>=r8 - just in case */
-
-	mflr	r4			/* save link register		*/
 1:
 	lwz	r0, 0(r7)
 	stw	r0, 0(r9)
@@ -848,23 +836,6 @@ trap_init:
 	mtlr	r4			/* restore link register	*/
 	blr
 
-	/*
-	 * Function: relocate entries for one exception vector
-	 */
-trap_reloc:
-	lwz	r0, 0(r7)		/* hdlr ...			*/
-	add	r0, r0, r3		/*  ... += dest_addr		*/
-	stw	r0, 0(r7)
-
-	lwz	r0, 4(r7)		/* int_return ...		*/
-	add	r0, r0, r3		/*  ... += dest_addr		*/
-	stw	r0, 4(r7)
-
-	sync
-	isync
-
-	blr
-
 .globl enable_ext_addr
 enable_ext_addr:
 	mfspr	r0, HID0

cpu/mpc8xx/config.mk

@@ -21,6 +21,6 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -meabi
 
 PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -mstring -mcpu=860 -msoft-float

cpu/mpc8xx/start.S

@@ -63,7 +63,7 @@
 /*
  * Set up GOT: Global Offset Table
  *
- * Use r14 to access the GOT
+ * Use r12 to access the GOT
  */
 	START_GOT
 	GOT_ENTRY(_GOT2_TABLE_)
@@ -231,28 +231,15 @@ Alignment:
 	mfspr	r5,DSISR
 	stw	r5,_DSISR(r21)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_Alignment:
-	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
 
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
 	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
+		MSR_KERNEL, COPY_EE)
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_ProgramCheck:
-	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
-	.long	int_return - _start + EXC_OFF_SYS_RESET
 
 	/* No FPU on MPC8xx.  This exception is not supposed to happen.
 	*/
@@ -495,6 +482,7 @@ relocate_code:
 	mr	r9,  r4		/* Save copy of Global Data pointer	*/
 	mr	r10, r5		/* Save copy of Destination Address	*/
 
+	GET_GOT
 	mr	r3,  r5				/* Destination Address	*/
 	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
 	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
@@ -512,7 +500,7 @@ relocate_code:
 	sub	r15, r10, r4
 
 	/* First our own GOT */
-	add	r14, r14, r15
+	add	r12, r12, r15
 	/* then the one used by the C code */
 	add	r30, r30, r15
 
@@ -577,7 +565,7 @@ relocate_code:
 in_ram:
 
 	/*
-	 * Relocation Function, r14 point to got2+0x8000
+	 * Relocation Function, r12 point to got2+0x8000
 	 *
 	 * Adjust got2 pointers, no need to check for 0, this code
 	 * already puts a few entries in the table.
@@ -642,6 +630,8 @@ clear_bss:
 	 */
 	.globl	trap_init
 trap_init:
+	mflr	r4			/* save link register		*/
+	GET_GOT
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 
@@ -649,8 +639,6 @@ trap_init:
 
 	cmplw	0, r7, r8
 	bgelr				/* return if r7>=r8 - just in case */
-
-	mflr	r4			/* save link register		*/
 1:
 	lwz	r0, 0(r7)
 	stw	r0, 0(r9)
@@ -694,20 +682,3 @@ trap_init:
 
 	mtlr	r4			/* restore link register	*/
 	blr
-
-	/*
-	 * Function: relocate entries for one exception vector
-	 */
-trap_reloc:
-	lwz	r0, 0(r7)		/* hdlr ...			*/
-	add	r0, r0, r3		/*  ... += dest_addr		*/
-	stw	r0, 0(r7)
-
-	lwz	r0, 4(r7)		/* int_return ...		*/
-	add	r0, r0, r3		/*  ... += dest_addr		*/
-	stw	r0, 4(r7)
-
-	sync
-	isync
-
-	blr

cpu/ppc4xx/config.mk

@@ -21,7 +21,7 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -meabi
 PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -mstring -msoft-float
 
 cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')

cpu/ppc4xx/start.S

@@ -228,7 +228,7 @@
 /*
  * Set up GOT: Global Offset Table
  *
- * Use r14 to access the GOT
+ * Use r12 to access the GOT
  */
 #if !defined(CONFIG_NAND_SPL)
 	START_GOT
@@ -574,28 +574,15 @@ Alignment:
 	mfspr	r5,DSISR
 	stw	r5,_DSISR(r21)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_Alignment:
-	.long	AlignmentException - _start + _START_OFFSET
-	.long	int_return - _start + _START_OFFSET
 
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
 	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r20,MSR_KERNEL
+	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
-	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
+		MSR_KERNEL, COPY_EE)
-	lwz	r6,GOT(transfer_to_handler)
-	mtlr	r6
-	blrl
-.L_ProgramCheck:
-	.long	ProgramCheckException - _start + _START_OFFSET
-	.long	int_return - _start + _START_OFFSET
 
 #ifdef CONFIG_440
 	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
@@ -1502,6 +1489,7 @@ relocate_code:
 	mr	r9,  r4		/* Save copy of Init Data pointer	*/
 	mr	r10, r5		/* Save copy of Destination Address	*/
 
+	GET_GOT
 	mr	r3,  r5				/* Destination Address	*/
 	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
 	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
@@ -1519,7 +1507,7 @@ relocate_code:
 	sub	r15, r10, r4
 
 	/* First our own GOT */
-	add	r14, r14, r15
+	add	r12, r12, r15
 	/* then the one used by the C code */
 	add	r30, r30, r15
 
@@ -1584,7 +1572,7 @@ relocate_code:
 in_ram:
 
 	/*
-	 * Relocation Function, r14 point to got2+0x8000
+	 * Relocation Function, r12 point to got2+0x8000
 	 *
 	 * Adjust got2 pointers, no need to check for 0, this code
 	 * already puts a few entries in the table.
@@ -1658,6 +1646,8 @@ clear_bss:
 	 */
 	.globl	trap_init
 trap_init:
+	mflr	r4			/* save link register		*/
+	GET_GOT
 	lwz	r7, GOT(_start_of_vectors)
 	lwz	r8, GOT(_end_of_vectors)
 
@@ -1665,8 +1655,6 @@ trap_init:
 
 	cmplw	0, r7, r8
 	bgelr				/* return if r7>=r8 - just in case */
-
-	mflr	r4			/* save link register		*/
 1:
 	lwz	r0, 0(r7)
 	stw	r0, 0(r9)
@@ -1742,20 +1730,6 @@ __440_msr_continue:
 	mtlr	r4			/* restore link register	*/
 	blr
 
-	/*
-	 * Function: relocate entries for one exception vector
-	 */
-trap_reloc:
-	lwz	r0, 0(r7)		/* hdlr ...			*/
-	add	r0, r0, r3		/*  ... += dest_addr		*/
-	stw	r0, 0(r7)
-
-	lwz	r0, 4(r7)		/* int_return ...		*/
-	add	r0, r0, r3		/*  ... += dest_addr		*/
-	stw	r0, 4(r7)
-
-	blr
-
 #if defined(CONFIG_440)
 /*----------------------------------------------------------------------------+
 | dcbz_area.

doc/README.imximage

@@ -0,0 +1,188 @@
+---------------------------------------------
+Imximage Boot Image generation using mkimage
+---------------------------------------------
+
+This document describes how to set up a U-Boot image
+that can be booted by Freescale MX25, MX35 and MX51
+processors via internal boot mode.
+
+These processors can boot directly from NAND, SPI flash and SD card flash
+using its internal boot ROM support. They can boot from an internal
+UART, if booting from device media fails.
+Booting from NOR flash does not require to use this image type.
+
+For more details refer Chapter 2 - System Boot and section 2.14
+(flash header description) of the processor's manual.
+
+This implementation does not use at the moment the secure boot feature
+of the processor. The image is generated disabling all security fields.
+
+Command syntax:
+--------------
+./tools/mkimage -l <mx u-boot_file>
+		to list the imx image file details
+
+./tools/mkimage -T imximage \
+		-n <board specific configuration file> \
+		-e <execution address> -d <u-boot binary>  <output image file>
+
+For example, for the mx51evk board:
+./tools/mkimage -n ./board/freescale/mx51evk/imximage.cfg \
+		-T imximage -e 0x97800000  \
+		-d u-boot.bin u-boot.imx
+
+You can generate directly the image when you compile u-boot with:
+
+$ make u-boot.imx
+
+The output image can be flashed on the board SPI flash or on a SD card.
+In both cases, you have to copy the image at the offset required for the
+chosen media devices (0x400 for both SPI flash or SD card).
+
+Please check Freescale documentation for further details.
+
+Board specific configuration file specifications:
+-------------------------------------------------
+1. This file must present in the $(BOARDDIR) and the name should be
+	imximage.cfg (since this is used in Makefile).
+2. This file can have empty lines and lines starting with "#" as first
+	character to put comments.
+3. This file can have configuration command lines as mentioned below,
+	any other information in this file is treated as invalid.
+
+Configuration command line syntax:
+---------------------------------
+1. Each command line is must have two strings, first one command or address
+	and second one data string
+2. Following are the valid command strings and associated data strings:-
+	Command string		data string
+	--------------		-----------
+	BOOT_FROM		nand/spi/sd/onenand
+				Example:
+				BOOT_FROM spi
+	DATA			type address value
+
+				type: word=4, halfword=2, byte=1
+				address: physycal register address
+				value: value to be set in register
+				All values are in in hexadecimal.
+				Example (write to IOMUXC):
+				DATA 4 0x73FA88a0 0x200
+
+The processor support up to 60 register programming commands. An error
+is generated if more commands are found in the configuration file.
+
+3. All commands are optional to program.
+
+Setup a SD Card for booting
+--------------------------------
+
+The following example prepare a SD card with u-boot and a FAT partition
+to be used to stored the kernel to be booted.
+I will set the SD in the most compatible mode, setting it with
+255 heads and 63 sectors, as suggested from several documentation and
+howto on line (I took as reference the preparation of a SD Card for the
+Beagleboard, running u-boot as bootloader).
+
+You should start clearing the partitions table on the SD card. Because
+the u-boot image must be stored at the offset 0x400, it must be assured
+that there is no partition at that address. A new SD card is already
+formatted with FAT filesystem and the partition starts from the first
+cylinder, so we need to change it.
+
+You can do all steps with fdisk. If the device for the SD card is
+/dev/mmcblk0, the following commands make the job:
+
+1. Start the fdisk utility (as superuser)
+	fdisk /dev/mmcblk0
+
+2. Clear the actual partition
+
+Command (m for help): o
+
+3. Print card info:
+
+Command (m for help): p
+Disk /dev/mmcblk0: 1981 MB, 1981284352 bytes
+
+In my case, I have a 2 GB card. I need the size to set later the correct value
+for the cylinders.
+
+4. Go to expert mode:
+
+Command (m for help): x
+
+5. Set card geometry
+
+Expert command (m for help): h
+Number of heads (1-256, default 4): 255
+
+Expert command (m for help): s
+Number of sectors (1-63, default 16): 63
+Warning: setting sector offset for DOS compatiblity
+
+We have set 255 heads, 63 sector. We have to set the cylinder.
+The value to be set can be calculated with:
+
+	cilynder = <total size> / <heads> / <sectors> / <blocksize>
+
+in this example,
+	1981284352 / 255 / 63 / 512 = 239.x = 239
+
+
+Expert command (m for help): c
+Number of cylinders (1-1048576, default 60032): 239
+
+6. Leave the expert mode
+Expert command (m for help): r
+
+7. Set up a partition
+
+Now set a partition table to store the kernel or whatever you want. Of course,
+you can set additional partitions to store rootfs, data, etc.
+In my example I want to set a single partition. I must take care
+to not overwrite the space where I will put u-boot.
+
+Command (m for help): n
+Command action
+   e   extended
+   p   primary partition (1-4)
+p
+Partition number (1-4): 1
+First cylinder (1-239, default 1): 3
+Last cylinder, +cylinders or +size{K,M,G} (3-239, default 239): +100M
+
+Command (m for help): p
+
+Disk /dev/mmcblk0: 1967 MB, 1967128576 bytes
+255 heads, 63 sectors/track, 239 cylinders
+Units = cylinders of 16065 * 512 = 8225280 bytes
+Disk identifier: 0xb712a870
+
+        Device Boot      Start         End      Blocks   Id  System
+/dev/mmcblk0p1               3          16      112455   83  Linux
+
+I have set 100MB, leaving the first 2 sectors free. I will copy u-boot
+there.
+
+8. Write the partition table and exit.
+
+Command (m for help): w
+The partition table has been altered!
+
+Calling ioctl() to re-read partition table.
+
+9. Copy u-boot.imx on the SD card
+
+I use dd:
+
+dd if=u-boot.imx of=/dev/mmcblk0 bs=512 seek=2
+
+This command copies the u-boot image at the address 0x400, as required
+by the processor.
+
+Now remove your card from the PC and go to the target. If evrything went right,
+the u-boot prompt should come after power on.
+
+------------------------------------------------
+Author: Stefano babic <sbabic@denx.de>

drivers/net/Makefile

@@ -37,6 +37,7 @@ COBJS-$(CONFIG_DNET) += dnet.o
 COBJS-$(CONFIG_E1000) += e1000.o
 COBJS-$(CONFIG_EEPRO100) += eepro100.o
 COBJS-$(CONFIG_ENC28J60) += enc28j60.o
+COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o
 COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o
 COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
 COBJS-$(CONFIG_FTMAC100) += ftmac100.o

drivers/net/ep93xx_eth.c

@@ -0,0 +1,653 @@
+/*
+ * Cirrus Logic EP93xx ethernet MAC / MII driver.
+ *
+ * Copyright (C) 2010, 2009
+ * Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet Driver,
+ * which is
+ *
+ * (C) Copyright 2002 2003
+ * Adam Bezanson, Network Audio Technologies, Inc.
+ * <bezanson@netaudiotech.com>
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <command.h>
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <linux/types.h>
+#include "ep93xx_eth.h"
+
+#define GET_PRIV(eth_dev)	((struct ep93xx_priv *)(eth_dev)->priv)
+#define GET_REGS(eth_dev)	(GET_PRIV(eth_dev)->regs)
+
+/* ep93xx_miiphy ops forward declarations */
+static int ep93xx_miiphy_read(char * const dev, unsigned char const addr,
+			unsigned char const reg, unsigned short * const value);
+static int ep93xx_miiphy_write(char * const dev, unsigned char const addr,
+			unsigned char const reg, unsigned short const value);
+
+#if defined(EP93XX_MAC_DEBUG)
+/**
+ * Dump ep93xx_mac values to the terminal.
+ */
+static void dump_dev(struct eth_device *dev)
+{
+	struct ep93xx_priv *priv = GET_PRIV(dev);
+	int i;
+
+	printf("\ndump_dev()\n");
+	printf("  rx_dq.base	     %p\n", priv->rx_dq.base);
+	printf("  rx_dq.current	     %p\n", priv->rx_dq.current);
+	printf("  rx_dq.end	     %p\n", priv->rx_dq.end);
+	printf("  rx_sq.base	     %p\n", priv->rx_sq.base);
+	printf("  rx_sq.current	     %p\n", priv->rx_sq.current);
+	printf("  rx_sq.end	     %p\n", priv->rx_sq.end);
+
+	for (i = 0; i < NUMRXDESC; i++)
+		printf("  rx_buffer[%2.d]      %p\n", i, NetRxPackets[i]);
+
+	printf("  tx_dq.base	     %p\n", priv->tx_dq.base);
+	printf("  tx_dq.current	     %p\n", priv->tx_dq.current);
+	printf("  tx_dq.end	     %p\n", priv->tx_dq.end);
+	printf("  tx_sq.base	     %p\n", priv->tx_sq.base);
+	printf("  tx_sq.current	     %p\n", priv->tx_sq.current);
+	printf("  tx_sq.end	     %p\n", priv->tx_sq.end);
+}
+
+/**
+ * Dump all RX status queue entries to the terminal.
+ */
+static void dump_rx_status_queue(struct eth_device *dev)
+{
+	struct ep93xx_priv *priv = GET_PRIV(dev);
+	int i;
+
+	printf("\ndump_rx_status_queue()\n");
+	printf("  descriptor address	 word1		 word2\n");
+	for (i = 0; i < NUMRXDESC; i++) {
+		printf("  [ %p ]	     %08X	 %08X\n",
+			priv->rx_sq.base + i,
+			(priv->rx_sq.base + i)->word1,
+			(priv->rx_sq.base + i)->word2);
+	}
+}
+
+/**
+ * Dump all RX descriptor queue entries to the terminal.
+ */
+static void dump_rx_descriptor_queue(struct eth_device *dev)
+{
+	struct ep93xx_priv *priv = GET_PRIV(dev);
+	int i;
+
+	printf("\ndump_rx_descriptor_queue()\n");
+	printf("  descriptor address	 word1		 word2\n");
+	for (i = 0; i < NUMRXDESC; i++) {
+		printf("  [ %p ]	     %08X	 %08X\n",
+			priv->rx_dq.base + i,
+			(priv->rx_dq.base + i)->word1,
+			(priv->rx_dq.base + i)->word2);
+	}
+}
+
+/**
+ * Dump all TX descriptor queue entries to the terminal.
+ */
+static void dump_tx_descriptor_queue(struct eth_device *dev)
+{
+	struct ep93xx_priv *priv = GET_PRIV(dev);
+	int i;
+
+	printf("\ndump_tx_descriptor_queue()\n");
+	printf("  descriptor address	 word1		 word2\n");
+	for (i = 0; i < NUMTXDESC; i++) {
+		printf("  [ %p ]	     %08X	 %08X\n",
+			priv->tx_dq.base + i,
+			(priv->tx_dq.base + i)->word1,
+			(priv->tx_dq.base + i)->word2);
+	}
+}
+
+/**
+ * Dump all TX status queue entries to the terminal.
+ */
+static void dump_tx_status_queue(struct eth_device *dev)
+{
+	struct ep93xx_priv *priv = GET_PRIV(dev);
+	int i;
+
+	printf("\ndump_tx_status_queue()\n");
+	printf("  descriptor address	 word1\n");
+	for (i = 0; i < NUMTXDESC; i++) {
+		printf("  [ %p ]	     %08X\n",
+			priv->rx_sq.base + i,
+			(priv->rx_sq.base + i)->word1);
+	}
+}
+#else
+#define dump_dev(x)
+#define dump_rx_descriptor_queue(x)
+#define dump_rx_status_queue(x)
+#define dump_tx_descriptor_queue(x)
+#define dump_tx_status_queue(x)
+#endif	/* defined(EP93XX_MAC_DEBUG) */
+
+/**
+ * Reset the EP93xx MAC by twiddling the soft reset bit and spinning until
+ * it's cleared.
+ */
+static void ep93xx_mac_reset(struct eth_device *dev)
+{
+	struct mac_regs *mac = GET_REGS(dev);
+	uint32_t value;
+
+	debug("+ep93xx_mac_reset");
+
+	value = readl(&mac->selfctl);
+	value |= SELFCTL_RESET;
+	writel(value, &mac->selfctl);
+
+	while (readl(&mac->selfctl) & SELFCTL_RESET)
+		; /* noop */
+
+	debug("-ep93xx_mac_reset");
+}
+
+/* Eth device open */
+static int ep93xx_eth_open(struct eth_device *dev, bd_t *bd)
+{
+	struct ep93xx_priv *priv = GET_PRIV(dev);
+	struct mac_regs *mac = GET_REGS(dev);
+	uchar *mac_addr = dev->enetaddr;
+	int i;
+
+	debug("+ep93xx_eth_open");
+
+	/* Reset the MAC */
+	ep93xx_mac_reset(dev);
+
+	/* Reset the descriptor queues' current and end address values */
+	priv->tx_dq.current = priv->tx_dq.base;
+	priv->tx_dq.end = (priv->tx_dq.base + NUMTXDESC);
+
+	priv->tx_sq.current = priv->tx_sq.base;
+	priv->tx_sq.end = (priv->tx_sq.base + NUMTXDESC);
+
+	priv->rx_dq.current = priv->rx_dq.base;
+	priv->rx_dq.end = (priv->rx_dq.base + NUMRXDESC);
+
+	priv->rx_sq.current = priv->rx_sq.base;
+	priv->rx_sq.end = (priv->rx_sq.base + NUMRXDESC);
+
+	/*
+	 * Set the transmit descriptor and status queues' base address,
+	 * current address, and length registers.  Set the maximum frame
+	 * length and threshold. Enable the transmit descriptor processor.
+	 */
+	writel((uint32_t)priv->tx_dq.base, &mac->txdq.badd);
+	writel((uint32_t)priv->tx_dq.base, &mac->txdq.curadd);
+	writel(sizeof(struct tx_descriptor) * NUMTXDESC, &mac->txdq.blen);
+
+	writel((uint32_t)priv->tx_sq.base, &mac->txstsq.badd);
+	writel((uint32_t)priv->tx_sq.base, &mac->txstsq.curadd);
+	writel(sizeof(struct tx_status) * NUMTXDESC, &mac->txstsq.blen);
+
+	writel(0x00040000, &mac->txdthrshld);
+	writel(0x00040000, &mac->txststhrshld);
+
+	writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), &mac->maxfrmlen);
+	writel(BMCTL_TXEN, &mac->bmctl);
+
+	/*
+	 * Set the receive descriptor and status queues' base address,
+	 * current address, and length registers.  Enable the receive
+	 * descriptor processor.
+	 */
+	writel((uint32_t)priv->rx_dq.base, &mac->rxdq.badd);
+	writel((uint32_t)priv->rx_dq.base, &mac->rxdq.curadd);
+	writel(sizeof(struct rx_descriptor) * NUMRXDESC, &mac->rxdq.blen);
+
+	writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.badd);
+	writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.curadd);
+	writel(sizeof(struct rx_status) * NUMRXDESC, &mac->rxstsq.blen);
+
+	writel(0x00040000, &mac->rxdthrshld);
+
+	writel(BMCTL_RXEN, &mac->bmctl);
+
+	writel(0x00040000, &mac->rxststhrshld);
+
+	/* Wait until the receive descriptor processor is active */
+	while (!(readl(&mac->bmsts) & BMSTS_RXACT))
+		; /* noop */
+
+	/*
+	 * Initialize the RX descriptor queue. Clear the TX descriptor queue.
+	 * Clear the RX and TX status queues. Enqueue the RX descriptor and
+	 * status entries to the MAC.
+	 */
+	for (i = 0; i < NUMRXDESC; i++) {
+		/* set buffer address */
+		(priv->rx_dq.base + i)->word1 = (uint32_t)NetRxPackets[i];
+
+		/* set buffer length, clear buffer index and NSOF */
+		(priv->rx_dq.base + i)->word2 = PKTSIZE_ALIGN;
+	}
+
+	memset(priv->tx_dq.base, 0,
+		(sizeof(struct tx_descriptor) * NUMTXDESC));
+	memset(priv->rx_sq.base, 0,
+		(sizeof(struct rx_status) * NUMRXDESC));
+	memset(priv->tx_sq.base, 0,
+		(sizeof(struct tx_status) * NUMTXDESC));
+
+	writel(NUMRXDESC, &mac->rxdqenq);
+	writel(NUMRXDESC, &mac->rxstsqenq);
+
+	/* Set the primary MAC address */
+	writel(AFP_IAPRIMARY, &mac->afp);
+	writel(mac_addr[0] | (mac_addr[1] << 8) |
+		(mac_addr[2] << 16) | (mac_addr[3] << 24),
+		&mac->indad);
+	writel(mac_addr[4] | (mac_addr[5] << 8), &mac->indad_upper);
+
+	/* Turn on RX and TX */
+	writel(RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON |
+		RXCTL_RCRCA | RXCTL_MA, &mac->rxctl);
+	writel(TXCTL_STXON, &mac->txctl);
+
+	/* Dump data structures if we're debugging */
+	dump_dev(dev);
+	dump_rx_descriptor_queue(dev);
+	dump_rx_status_queue(dev);
+	dump_tx_descriptor_queue(dev);
+	dump_tx_status_queue(dev);
+
+	debug("-ep93xx_eth_open");
+
+	return 1;
+}
+
+/**
+ * Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL
+ * registers.
+ */
+static void ep93xx_eth_close(struct eth_device *dev)
+{
+	struct mac_regs *mac = GET_REGS(dev);
+
+	debug("+ep93xx_eth_close");
+
+	writel(0x00000000, &mac->rxctl);
+	writel(0x00000000, &mac->txctl);
+
+	debug("-ep93xx_eth_close");
+}
+
+/**
+ * Copy a frame of data from the MAC into the protocol layer for further
+ * processing.
+ */
+static int ep93xx_eth_rcv_packet(struct eth_device *dev)
+{
+	struct mac_regs *mac = GET_REGS(dev);
+	struct ep93xx_priv *priv = GET_PRIV(dev);
+	int len = -1;
+
+	debug("+ep93xx_eth_rcv_packet");
+
+	if (RX_STATUS_RFP(priv->rx_sq.current)) {
+		if (RX_STATUS_RWE(priv->rx_sq.current)) {
+			/*
+			 * We have a good frame. Extract the frame's length
+			 * from the current rx_status_queue entry, and copy
+			 * the frame's data into NetRxPackets[] of the
+			 * protocol stack. We track the total number of
+			 * bytes in the frame (nbytes_frame) which will be
+			 * used when we pass the data off to the protocol
+			 * layer via NetReceive().
+			 */
+			len = RX_STATUS_FRAME_LEN(priv->rx_sq.current);
+
+			NetReceive((uchar *)priv->rx_dq.current->word1,	len);
+
+			debug("reporting %d bytes...\n", len);
+		} else {
+			/* Do we have an erroneous packet? */
+			error("packet rx error, status %08X %08X",
+				priv->rx_sq.current->word1,
+				priv->rx_sq.current->word2);
+			dump_rx_descriptor_queue(dev);
+			dump_rx_status_queue(dev);
+		}
+
+		/*
+		 * Clear the associated status queue entry, and
+		 * increment our current pointers to the next RX
+		 * descriptor and status queue entries (making sure
+		 * we wrap properly).
+		 */
+		memset((void *)priv->rx_sq.current, 0,
+			sizeof(struct rx_status));
+
+		priv->rx_sq.current++;
+		if (priv->rx_sq.current >= priv->rx_sq.end)
+			priv->rx_sq.current = priv->rx_sq.base;
+
+		priv->rx_dq.current++;
+		if (priv->rx_dq.current >= priv->rx_dq.end)
+			priv->rx_dq.current = priv->rx_dq.base;
+
+		/*
+		 * Finally, return the RX descriptor and status entries
+		 * back to the MAC engine, and loop again, checking for
+		 * more descriptors to process.
+		 */
+		writel(1, &mac->rxdqenq);
+		writel(1, &mac->rxstsqenq);
+	} else {
+		len = 0;
+	}
+
+	debug("-ep93xx_eth_rcv_packet %d", len);
+	return len;
+}
+
+/**
+ * Send a block of data via ethernet.
+ */
+static int ep93xx_eth_send_packet(struct eth_device *dev,
+				volatile void * const packet, int const length)
+{
+	struct mac_regs *mac = GET_REGS(dev);
+	struct ep93xx_priv *priv = GET_PRIV(dev);
+	int ret = -1;
+
+	debug("+ep93xx_eth_send_packet");
+
+	/* Parameter check */
+	BUG_ON(packet == NULL);
+
+	/*
+	 * Initialize the TX descriptor queue with the new packet's info.
+	 * Clear the associated status queue entry. Enqueue the packet
+	 * to the MAC for transmission.
+	 */
+
+	/* set buffer address */
+	priv->tx_dq.current->word1 = (uint32_t)packet;
+
+	/* set buffer length and EOF bit */
+	priv->tx_dq.current->word2 = length | TX_DESC_EOF;
+
+	/* clear tx status */
+	priv->tx_sq.current->word1 = 0;
+
+	/* enqueue the TX descriptor */
+	writel(1, &mac->txdqenq);
+
+	/* wait for the frame to become processed */
+	while (!TX_STATUS_TXFP(priv->tx_sq.current))
+		; /* noop */
+
+	if (!TX_STATUS_TXWE(priv->tx_sq.current)) {
+		error("packet tx error, status %08X",
+			priv->tx_sq.current->word1);
+		dump_tx_descriptor_queue(dev);
+		dump_tx_status_queue(dev);
+
+		/* TODO: Add better error handling? */
+		goto eth_send_out;
+	}
+
+	ret = 0;
+	/* Fall through */
+
+eth_send_out:
+	debug("-ep93xx_eth_send_packet %d", ret);
+	return ret;
+}
+
+#if defined(CONFIG_MII)
+int ep93xx_miiphy_initialize(bd_t * const bd)
+{
+	miiphy_register("ep93xx_eth0", ep93xx_miiphy_read, ep93xx_miiphy_write);
+	return 0;
+}
+#endif
+
+/**
+ * Initialize the EP93xx MAC.  The MAC hardware is reset.  Buffers are
+ * allocated, if necessary, for the TX and RX descriptor and status queues,
+ * as well as for received packets.  The EP93XX MAC hardware is initialized.
+ * Transmit and receive operations are enabled.
+ */
+int ep93xx_eth_initialize(u8 dev_num, int base_addr)
+{
+	int ret = -1;
+	struct eth_device *dev;
+	struct ep93xx_priv *priv;
+
+	debug("+ep93xx_eth_initialize");
+
+	priv = malloc(sizeof(*priv));
+	if (!priv) {
+		error("malloc() failed");
+		goto eth_init_failed_0;
+	}
+	memset(priv, 0, sizeof(*priv));
+
+	priv->regs = (struct mac_regs *)base_addr;
+
+	priv->tx_dq.base = calloc(NUMTXDESC,
+				sizeof(struct tx_descriptor));
+	if (priv->tx_dq.base == NULL) {
+		error("calloc() failed");
+		goto eth_init_failed_1;
+	}
+
+	priv->tx_sq.base = calloc(NUMTXDESC,
+				sizeof(struct tx_status));
+	if (priv->tx_sq.base == NULL) {
+		error("calloc() failed");
+		goto eth_init_failed_2;
+	}
+
+	priv->rx_dq.base = calloc(NUMRXDESC,
+				sizeof(struct rx_descriptor));
+	if (priv->rx_dq.base == NULL) {
+		error("calloc() failed");
+		goto eth_init_failed_3;
+	}
+
+	priv->rx_sq.base = calloc(NUMRXDESC,
+				sizeof(struct rx_status));
+	if (priv->rx_sq.base == NULL) {
+		error("calloc() failed");
+		goto eth_init_failed_4;
+	}
+
+	dev = malloc(sizeof *dev);
+	if (dev == NULL) {
+		error("malloc() failed");
+		goto eth_init_failed_5;
+	}
+	memset(dev, 0, sizeof *dev);
+
+	dev->iobase = base_addr;
+	dev->priv = priv;
+	dev->init = ep93xx_eth_open;
+	dev->halt = ep93xx_eth_close;
+	dev->send = ep93xx_eth_send_packet;
+	dev->recv = ep93xx_eth_rcv_packet;
+
+	sprintf(dev->name, "ep93xx_eth-%hu", dev_num);
+
+	eth_register(dev);
+
+	/* Done! */
+	ret = 1;
+	goto eth_init_done;
+
+eth_init_failed_5:
+	free(priv->rx_sq.base);
+	/* Fall through */
+
+eth_init_failed_4:
+	free(priv->rx_dq.base);
+	/* Fall through */
+
+eth_init_failed_3:
+	free(priv->tx_sq.base);
+	/* Fall through */
+
+eth_init_failed_2:
+	free(priv->tx_dq.base);
+	/* Fall through */
+
+eth_init_failed_1:
+	free(priv);
+	/* Fall through */
+
+eth_init_failed_0:
+	/* Fall through */
+
+eth_init_done:
+	debug("-ep93xx_eth_initialize %d", ret);
+	return ret;
+}
+
+#if defined(CONFIG_MII)
+
+/**
+ * Maximum MII address we support
+ */
+#define MII_ADDRESS_MAX			31
+
+/**
+ * Maximum MII register address we support
+ */
+#define MII_REGISTER_MAX		31
+
+/**
+ * Read a 16-bit value from an MII register.
+ */
+static int ep93xx_miiphy_read(char * const dev, unsigned char const addr,
+			unsigned char const reg, unsigned short * const value)
+{
+	struct mac_regs *mac = (struct mac_regs *)MAC_BASE;
+	int ret = -1;
+	uint32_t self_ctl;
+
+	debug("+ep93xx_miiphy_read");
+
+	/* Parameter checks */
+	BUG_ON(dev == NULL);
+	BUG_ON(addr > MII_ADDRESS_MAX);
+	BUG_ON(reg > MII_REGISTER_MAX);
+	BUG_ON(value == NULL);
+
+	/*
+	 * Save the current SelfCTL register value.  Set MAC to suppress
+	 * preamble bits.  Wait for any previous MII command to complete
+	 * before issuing the new command.
+	 */
+	self_ctl = readl(&mac->selfctl);
+#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
+	writel(self_ctl & ~(1 << 8), &mac->selfctl);
+#endif	/* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
+
+	while (readl(&mac->miists) & MIISTS_BUSY)
+		; /* noop */
+
+	/*
+	 * Issue the MII 'read' command.  Wait for the command to complete.
+	 * Read the MII data value.
+	 */
+	writel(MIICMD_OPCODE_READ | ((uint32_t)addr << 5) | (uint32_t)reg,
+		&mac->miicmd);
+	while (readl(&mac->miists) & MIISTS_BUSY)
+		; /* noop */
+
+	*value = (unsigned short)readl(&mac->miidata);
+
+	/* Restore the saved SelfCTL value and return. */
+	writel(self_ctl, &mac->selfctl);
+
+	ret = 0;
+	/* Fall through */
+
+	debug("-ep93xx_miiphy_read");
+	return ret;
+}
+
+/**
+ * Write a 16-bit value to an MII register.
+ */
+static int ep93xx_miiphy_write(char * const dev, unsigned char const addr,
+			unsigned char const reg, unsigned short const value)
+{
+	struct mac_regs *mac = (struct mac_regs *)MAC_BASE;
+	int ret = -1;
+	uint32_t self_ctl;
+
+	debug("+ep93xx_miiphy_write");
+
+	/* Parameter checks */
+	BUG_ON(dev == NULL);
+	BUG_ON(addr > MII_ADDRESS_MAX);
+	BUG_ON(reg > MII_REGISTER_MAX);
+
+	/*
+	 * Save the current SelfCTL register value.  Set MAC to suppress
+	 * preamble bits.  Wait for any previous MII command to complete
+	 * before issuing the new command.
+	 */
+	self_ctl = readl(&mac->selfctl);
+#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
+	writel(self_ctl & ~(1 << 8), &mac->selfctl);
+#endif	/* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
+
+	while (readl(&mac->miists) & MIISTS_BUSY)
+		; /* noop */
+
+	/* Issue the MII 'write' command.  Wait for the command to complete. */
+	writel((uint32_t)value, &mac->miidata);
+	writel(MIICMD_OPCODE_WRITE | ((uint32_t)addr << 5) | (uint32_t)reg,
+		&mac->miicmd);
+	while (readl(&mac->miists) & MIISTS_BUSY)
+		; /* noop */
+
+	/* Restore the saved SelfCTL value and return. */
+	writel(self_ctl, &mac->selfctl);
+
+	ret = 0;
+	/* Fall through */
+
+	debug("-ep93xx_miiphy_write");
+	return ret;
+}
+#endif	/* defined(CONFIG_MII) */

drivers/net/ep93xx_eth.h

@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _EP93XX_ETH_H
+#define _EP93XX_ETH_H
+
+#include <net.h>
+
+/**
+ * #define this to dump device status and queue info during initialization and
+ * following errors.
+ */
+#undef EP93XX_MAC_DEBUG
+
+/**
+ * Number of descriptor and status entries in our RX queues.
+ * It must be power of 2 !
+ */
+#define NUMRXDESC		PKTBUFSRX
+
+/**
+ * Number of descriptor and status entries in our TX queues.
+ */
+#define NUMTXDESC		1
+
+/**
+ * 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT)
+ */
+#define TXSTARTMAX		944
+
+/**
+ * Receive descriptor queue entry
+ */
+struct rx_descriptor {
+	uint32_t word1;
+	uint32_t word2;
+};
+
+/**
+ * Receive status queue entry
+ */
+struct rx_status {
+	uint32_t word1;
+	uint32_t word2;
+};
+
+#define RX_STATUS_RWE(rx_status) ((rx_status->word1 >> 30) & 0x01)
+#define RX_STATUS_RFP(rx_status) ((rx_status->word1 >> 31) & 0x01)
+#define RX_STATUS_FRAME_LEN(rx_status) (rx_status->word2 & 0xFFFF)
+
+/**
+ * Transmit descriptor queue entry
+ */
+struct tx_descriptor {
+	uint32_t word1;
+	uint32_t word2;
+};
+
+#define TX_DESC_EOF (1 << 31)
+
+/**
+ * Transmit status queue entry
+ */
+struct tx_status {
+	uint32_t word1;
+};
+
+#define TX_STATUS_TXWE(tx_status) (((tx_status)->word1 >> 30) & 0x01)
+#define TX_STATUS_TXFP(tx_status) (((tx_status)->word1 >> 31) & 0x01)
+
+/**
+ * Transmit descriptor queue
+ */
+struct tx_descriptor_queue {
+	struct tx_descriptor *base;
+	struct tx_descriptor *current;
+	struct tx_descriptor *end;
+};
+
+/**
+ * Transmit status queue
+ */
+struct tx_status_queue {
+	struct tx_status *base;
+	volatile struct tx_status *current;
+	struct tx_status *end;
+};
+
+/**
+ * Receive descriptor queue
+ */
+struct rx_descriptor_queue {
+	struct rx_descriptor *base;
+	struct rx_descriptor *current;
+	struct rx_descriptor *end;
+};
+
+/**
+ * Receive status queue
+ */
+struct rx_status_queue {
+	struct rx_status *base;
+	volatile struct rx_status *current;
+	struct rx_status *end;
+};
+
+/**
+ * EP93xx MAC private data structure
+ */
+struct ep93xx_priv {
+	struct rx_descriptor_queue	rx_dq;
+	struct rx_status_queue		rx_sq;
+	void				*rx_buffer[NUMRXDESC];
+
+	struct tx_descriptor_queue	tx_dq;
+	struct tx_status_queue		tx_sq;
+
+	struct mac_regs			*regs;
+};
+
+#endif

drivers/pci/pci_indirect.c

@@ -59,7 +59,8 @@ indirect_##rw##_config_##size(struct pci_controller *hose,               \
 	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);       \
 	return 0;                                                        \
 }
-#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
+#elif defined(CONFIG_440GX)  || defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
+      defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #define INDIRECT_PCI_OP(rw, size, type, op, mask)			 \
 static int								 \
 indirect_##rw##_config_##size(struct pci_controller *hose,		 \

drivers/spi/Makefile

@@ -29,6 +29,7 @@ COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
 COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
 COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
 COBJS-$(CONFIG_CF_SPI) += cf_spi.o
+COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
 COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
 COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
 COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o

drivers/spi/davinci_spi.c

@@ -0,0 +1,223 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Driver for SPI controller on DaVinci. Based on atmel_spi.c
+ * by Atmel Corporation
+ *
+ * Copyright (C) 2007 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <spi.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include "davinci_spi.h"
+
+void spi_init()
+{
+	/* do nothing */
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+			unsigned int max_hz, unsigned int mode)
+{
+	struct davinci_spi_slave	*ds;
+
+	if (!spi_cs_is_valid(bus, cs))
+		return NULL;
+
+	ds = malloc(sizeof(*ds));
+	if (!ds)
+		return NULL;
+
+	ds->slave.bus = bus;
+	ds->slave.cs = cs;
+	ds->regs = (struct davinci_spi_regs *)CONFIG_SYS_SPI_BASE;
+	ds->freq = max_hz;
+
+	return &ds->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	struct davinci_spi_slave *ds = to_davinci_spi(slave);
+
+	free(ds);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	struct davinci_spi_slave *ds = to_davinci_spi(slave);
+	unsigned int scalar, data1_reg_val = 0;
+
+	/* Enable the SPI hardware */
+	writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
+	udelay(1000);
+	writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
+
+	/* Set master mode, powered up and not activated */
+	writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
+
+	/* CS, CLK, SIMO and SOMI are functional pins */
+	writel((SPIPC0_EN0FUN_MASK | SPIPC0_CLKFUN_MASK |
+		SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
+
+	/* setup format */
+	scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
+
+	/*
+	 * Use following format:
+	 *   character length = 8,
+	 *   clock signal delayed by half clk cycle,
+	 *   clock low in idle state - Mode 0,
+	 *   MSB shifted out first
+	 */
+	writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
+		(1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
+
+	/* hold cs active at end of transfer until explicitly de-asserted */
+	data1_reg_val = (1 << SPIDAT1_CSHOLD_SHIFT) |
+			(slave->cs << SPIDAT1_CSNR_SHIFT);
+	writel(data1_reg_val, &ds->regs->dat1);
+
+	/*
+	 * Including a minor delay. No science here. Should be good even with
+	 * no delay
+	 */
+	writel((50 << SPI_C2TDELAY_SHIFT) |
+		(50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
+
+	/* default chip select register */
+	writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
+
+	/* no interrupts */
+	writel(0, &ds->regs->int0);
+	writel(0, &ds->regs->lvl);
+
+	/* enable SPI */
+	writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
+
+	return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+	struct davinci_spi_slave *ds = to_davinci_spi(slave);
+
+	/* Disable the SPI hardware */
+	writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+		const void *dout, void *din, unsigned long flags)
+{
+	struct davinci_spi_slave *ds = to_davinci_spi(slave);
+	unsigned int	len, data1_reg_val = readl(&ds->regs->dat1);
+	int		ret, i;
+	const u8	*txp = dout; /* dout can be NULL for read operation */
+	u8		*rxp = din;  /* din can be NULL for write operation */
+
+	ret = 0;
+
+	if (bitlen == 0)
+		/* Finish any previously submitted transfers */
+		goto out;
+
+	/*
+	 * It's not clear how non-8-bit-aligned transfers are supposed to be
+	 * represented as a stream of bytes...this is a limitation of
+	 * the current SPI interface - here we terminate on receiving such a
+	 * transfer request.
+	 */
+	if (bitlen % 8) {
+		/* Errors always terminate an ongoing transfer */
+		flags |= SPI_XFER_END;
+		goto out;
+	}
+
+	len = bitlen / 8;
+
+	/* do an empty read to clear the current contents */
+	readl(&ds->regs->buf);
+
+	/* keep writing and reading 1 byte until done */
+	for (i = 0; i < len; i++) {
+		/* wait till TXFULL is asserted */
+		while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK);
+
+		/* write the data */
+		data1_reg_val &= ~0xFFFF;
+		if (txp) {
+			data1_reg_val |= *txp;
+			txp++;
+		}
+
+		/*
+		 * Write to DAT1 is required to keep the serial transfer going.
+		 * We just terminate when we reach the end.
+		 */
+		if ((i == (len - 1)) && (flags & SPI_XFER_END)) {
+			/* clear CS hold */
+			writel(data1_reg_val &
+				~(1 << SPIDAT1_CSHOLD_SHIFT), &ds->regs->dat1);
+		} else {
+			/* enable CS hold */
+			data1_reg_val |= ((1 << SPIDAT1_CSHOLD_SHIFT) |
+					(slave->cs << SPIDAT1_CSNR_SHIFT));
+			writel(data1_reg_val, &ds->regs->dat1);
+		}
+
+		/* read the data - wait for data availability */
+		while (readl(&ds->regs->buf) & SPIBUF_RXEMPTY_MASK);
+
+		if (rxp) {
+			*rxp = readl(&ds->regs->buf) & 0xFF;
+			rxp++;
+		} else {
+			/* simply drop the read character */
+			readl(&ds->regs->buf);
+		}
+	}
+	return 0;
+
+out:
+	if (flags & SPI_XFER_END) {
+		writel(data1_reg_val &
+			~(1 << SPIDAT1_CSHOLD_SHIFT), &ds->regs->dat1);
+	}
+	return 0;
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	/* do nothing */
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	/* do nothing */
+}
+

drivers/spi/davinci_spi.h

@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Register definitions for the DaVinci SPI Controller
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _DAVINCI_SPI_H_
+#define _DAVINCI_SPI_H_
+
+struct davinci_spi_regs {
+	dv_reg	gcr0;		/* 0x00 */
+	dv_reg	gcr1;		/* 0x04 */
+	dv_reg	int0;		/* 0x08 */
+	dv_reg	lvl;		/* 0x0c */
+	dv_reg	flg;		/* 0x10 */
+	dv_reg	pc0;		/* 0x14 */
+	dv_reg	pc1;		/* 0x18 */
+	dv_reg	pc2;		/* 0x1c */
+	dv_reg	pc3;		/* 0x20 */
+	dv_reg	pc4;		/* 0x24 */
+	dv_reg	pc5;		/* 0x28 */
+	dv_reg	rsvd[3];
+	dv_reg	dat0;		/* 0x38 */
+	dv_reg	dat1;		/* 0x3c */
+	dv_reg	buf;		/* 0x40 */
+	dv_reg	emu;		/* 0x44 */
+	dv_reg	delay;		/* 0x48 */
+	dv_reg	def;		/* 0x4c */
+	dv_reg	fmt0;		/* 0x50 */
+	dv_reg	fmt1;		/* 0x54 */
+	dv_reg	fmt2;		/* 0x58 */
+	dv_reg	fmt3;		/* 0x5c */
+	dv_reg	intvec0;	/* 0x60 */
+	dv_reg	intvec1;	/* 0x64 */
+};
+
+#define BIT(x)			(1 << (x))
+
+/* SPIGCR0 */
+#define SPIGCR0_SPIENA_MASK	0x1
+#define SPIGCR0_SPIRST_MASK	0x0
+
+/* SPIGCR0 */
+#define SPIGCR1_CLKMOD_MASK	BIT(1)
+#define SPIGCR1_MASTER_MASK	BIT(0)
+#define SPIGCR1_SPIENA_MASK	BIT(24)
+
+/* SPIPC0 */
+#define SPIPC0_DIFUN_MASK	BIT(11)		/* SIMO */
+#define SPIPC0_DOFUN_MASK	BIT(10)		/* SOMI */
+#define SPIPC0_CLKFUN_MASK	BIT(9)		/* CLK */
+#define SPIPC0_EN0FUN_MASK	BIT(0)
+
+/* SPIFMT0 */
+#define SPIFMT_SHIFTDIR_SHIFT	20
+#define SPIFMT_POLARITY_SHIFT	17
+#define SPIFMT_PHASE_SHIFT	16
+#define SPIFMT_PRESCALE_SHIFT	8
+
+/* SPIDAT1 */
+#define SPIDAT1_CSHOLD_SHIFT	28
+#define SPIDAT1_CSNR_SHIFT	16
+
+/* SPIDELAY */
+#define SPI_C2TDELAY_SHIFT	24
+#define SPI_T2CDELAY_SHIFT	16
+
+/* SPIBUF */
+#define SPIBUF_RXEMPTY_MASK	BIT(31)
+#define SPIBUF_TXFULL_MASK	BIT(29)
+
+/* SPIDEF */
+#define SPIDEF_CSDEF0_MASK	BIT(0)
+
+struct davinci_spi_slave {
+	struct spi_slave slave;
+	struct davinci_spi_regs *regs;
+	unsigned int freq;
+};
+
+static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave)
+{
+	return container_of(slave, struct davinci_spi_slave, slave);
+}
+
+#endif /* _DAVINCI_SPI_H_ */

include/asm-arm/arch-ep93xx/ep93xx.h

@@ -0,0 +1,595 @@
+/*
+ * Cirrus Logic EP93xx register definitions.
+ *
+ * Copyright (C) 2009
+ * Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006
+ * Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is
+ *
+ * Copyright (C) 2004 Ray Lehtiniemi
+ * Copyright (C) 2003 Cirrus Logic, Inc
+ * Copyright (C) 1999 ARM Limited.
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#define EP93XX_AHB_BASE			0x80000000
+#define EP93XX_APB_BASE			0x80800000
+
+/*
+ * 0x80000000 - 0x8000FFFF: DMA
+ */
+#define DMA_OFFSET			0x000000
+#define DMA_BASE			(EP93XX_AHB_BASE | DMA_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct dma_channel {
+	uint32_t control;
+	uint32_t interrupt;
+	uint32_t ppalloc;
+	uint32_t status;
+	uint32_t reserved0;
+	uint32_t remain;
+	uint32_t reserved1[2];
+	uint32_t maxcnt0;
+	uint32_t base0;
+	uint32_t current0;
+	uint32_t reserved2;
+	uint32_t maxcnt1;
+	uint32_t base1;
+	uint32_t current1;
+	uint32_t reserved3;
+};
+
+struct dma_regs {
+	struct dma_channel m2p_channel_0;
+	struct dma_channel m2p_channel_1;
+	struct dma_channel m2p_channel_2;
+	struct dma_channel m2p_channel_3;
+	struct dma_channel m2m_channel_0;
+	struct dma_channel m2m_channel_1;
+	struct dma_channel reserved0[2];
+	struct dma_channel m2p_channel_5;
+	struct dma_channel m2p_channel_4;
+	struct dma_channel m2p_channel_7;
+	struct dma_channel m2p_channel_6;
+	struct dma_channel m2p_channel_9;
+	struct dma_channel m2p_channel_8;
+	uint32_t channel_arbitration;
+	uint32_t reserved[15];
+	uint32_t global_interrupt;
+};
+#endif
+
+/*
+ * 0x80010000 - 0x8001FFFF: Ethernet MAC
+ */
+#define MAC_OFFSET			0x010000
+#define MAC_BASE			(EP93XX_AHB_BASE | MAC_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct mac_queue {
+	uint32_t badd;
+	union { /* deal with half-word aligned registers */
+		uint32_t blen;
+		union {
+			uint16_t filler;
+			uint16_t curlen;
+		};
+	};
+	uint32_t curadd;
+};
+
+struct mac_regs {
+	uint32_t rxctl;
+	uint32_t txctl;
+	uint32_t testctl;
+	uint32_t reserved0;
+	uint32_t miicmd;
+	uint32_t miidata;
+	uint32_t miists;
+	uint32_t reserved1;
+	uint32_t selfctl;
+	uint32_t inten;
+	uint32_t intstsp;
+	uint32_t intstsc;
+	uint32_t reserved2[2];
+	uint32_t diagad;
+	uint32_t diagdata;
+	uint32_t gt;
+	uint32_t fct;
+	uint32_t fcf;
+	uint32_t afp;
+	union {
+		struct {
+			uint32_t indad;
+			uint32_t indad_upper;
+		};
+		uint32_t hashtbl;
+	};
+	uint32_t reserved3[2];
+	uint32_t giintsts;
+	uint32_t giintmsk;
+	uint32_t giintrosts;
+	uint32_t giintfrc;
+	uint32_t txcollcnt;
+	uint32_t rxmissnct;
+	uint32_t rxruntcnt;
+	uint32_t reserved4;
+	uint32_t bmctl;
+	uint32_t bmsts;
+	uint32_t rxbca;
+	uint32_t reserved5;
+	struct mac_queue rxdq;
+	uint32_t rxdqenq;
+	struct mac_queue rxstsq;
+	uint32_t rxstsqenq;
+	struct mac_queue txdq;
+	uint32_t txdqenq;
+	struct mac_queue txstsq;
+	uint32_t reserved6;
+	uint32_t rxbufthrshld;
+	uint32_t txbufthrshld;
+	uint32_t rxststhrshld;
+	uint32_t txststhrshld;
+	uint32_t rxdthrshld;
+	uint32_t txdthrshld;
+	uint32_t maxfrmlen;
+	uint32_t maxhdrlen;
+};
+#endif
+
+#define SELFCTL_RWP		(1 << 7)
+#define SELFCTL_GPO0		(1 << 5)
+#define SELFCTL_PUWE		(1 << 4)
+#define SELFCTL_PDWE		(1 << 3)
+#define SELFCTL_MIIL		(1 << 2)
+#define SELFCTL_RESET		(1 << 0)
+
+#define INTSTS_RWI		(1 << 30)
+#define INTSTS_RXMI		(1 << 29)
+#define INTSTS_RXBI		(1 << 28)
+#define INTSTS_RXSQI		(1 << 27)
+#define INTSTS_TXLEI		(1 << 26)
+#define INTSTS_ECIE		(1 << 25)
+#define INTSTS_TXUHI		(1 << 24)
+#define INTSTS_MOI		(1 << 18)
+#define INTSTS_TXCOI		(1 << 17)
+#define INTSTS_RXROI		(1 << 16)
+#define INTSTS_MIII		(1 << 12)
+#define INTSTS_PHYI		(1 << 11)
+#define INTSTS_TI		(1 << 10)
+#define INTSTS_AHBE		(1 << 8)
+#define INTSTS_OTHER		(1 << 4)
+#define INTSTS_TXSQ		(1 << 3)
+#define INTSTS_RXSQ		(1 << 2)
+
+#define BMCTL_MT		(1 << 13)
+#define BMCTL_TT		(1 << 12)
+#define BMCTL_UNH		(1 << 11)
+#define BMCTL_TXCHR		(1 << 10)
+#define BMCTL_TXDIS		(1 << 9)
+#define BMCTL_TXEN		(1 << 8)
+#define BMCTL_EH2		(1 << 6)
+#define BMCTL_EH1		(1 << 5)
+#define BMCTL_EEOB		(1 << 4)
+#define BMCTL_RXCHR		(1 << 2)
+#define BMCTL_RXDIS		(1 << 1)
+#define BMCTL_RXEN		(1 << 0)
+
+#define BMSTS_TXACT		(1 << 7)
+#define BMSTS_TP		(1 << 4)
+#define BMSTS_RXACT		(1 << 3)
+#define BMSTS_QID_MASK		0x07
+#define BMSTS_QID_RXDATA	0x00
+#define BMSTS_QID_TXDATA	0x01
+#define BMSTS_QID_RXSTS		0x02
+#define BMSTS_QID_TXSTS		0x03
+#define BMSTS_QID_RXDESC	0x04
+#define BMSTS_QID_TXDESC	0x05
+
+#define AFP_MASK		0x07
+#define AFP_IAPRIMARY		0x00
+#define AFP_IASECONDARY1	0x01
+#define AFP_IASECONDARY2	0x02
+#define AFP_IASECONDARY3	0x03
+#define AFP_TX			0x06
+#define AFP_HASH		0x07
+
+#define RXCTL_PAUSEA		(1 << 20)
+#define RXCTL_RXFCE1		(1 << 19)
+#define RXCTL_RXFCE0		(1 << 18)
+#define RXCTL_BCRC		(1 << 17)
+#define RXCTL_SRXON		(1 << 16)
+#define RXCTL_RCRCA		(1 << 13)
+#define RXCTL_RA		(1 << 12)
+#define RXCTL_PA		(1 << 11)
+#define RXCTL_BA		(1 << 10)
+#define RXCTL_MA		(1 << 9)
+#define RXCTL_IAHA		(1 << 8)
+#define RXCTL_IA3		(1 << 3)
+#define RXCTL_IA2		(1 << 2)
+#define RXCTL_IA1		(1 << 1)
+#define RXCTL_IA0		(1 << 0)
+
+#define TXCTL_DEFDIS		(1 << 7)
+#define TXCTL_MBE		(1 << 6)
+#define TXCTL_ICRC		(1 << 5)
+#define TXCTL_TPD		(1 << 4)
+#define TXCTL_OCOLL		(1 << 3)
+#define TXCTL_SP		(1 << 2)
+#define TXCTL_PB		(1 << 1)
+#define TXCTL_STXON		(1 << 0)
+
+#define MIICMD_REGAD_MASK	(0x001F)
+#define MIICMD_PHYAD_MASK	(0x03E0)
+#define MIICMD_OPCODE_MASK	(0xC000)
+#define MIICMD_PHYAD_8950	(0x0000)
+#define MIICMD_OPCODE_READ	(0x8000)
+#define MIICMD_OPCODE_WRITE	(0x4000)
+
+#define MIISTS_BUSY		(1 << 0)
+
+/*
+ * 0x80020000 - 0x8002FFFF: USB OHCI
+ */
+#define USB_OFFSET			0x020000
+#define USB_BASE			(EP93XX_AHB_BASE | USB_OFFSET)
+
+/*
+ * 0x80030000 - 0x8003FFFF: Raster engine
+ */
+#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315))
+#define RASTER_OFFSET			0x030000
+#define RASTER_BASE			(EP93XX_AHB_BASE | RASTER_OFFSET)
+#endif
+
+/*
+ * 0x80040000 - 0x8004FFFF: Graphics accelerator
+ */
+#if defined(CONFIG_EP9315)
+#define GFX_OFFSET			0x040000
+#define GFX_BASE			(EP93XX_AHB_BASE | GFX_OFFSET)
+#endif
+
+/*
+ * 0x80050000 - 0x8005FFFF: Reserved
+ */
+
+/*
+ * 0x80060000 - 0x8006FFFF: SDRAM controller
+ */
+#define SDRAM_OFFSET			0x060000
+#define SDRAM_BASE			(EP93XX_AHB_BASE | SDRAM_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct sdram_regs {
+	uint32_t reserved;
+	uint32_t glconfig;
+	uint32_t refrshtimr;
+	uint32_t bootsts;
+	uint32_t devcfg0;
+	uint32_t devcfg1;
+	uint32_t devcfg2;
+	uint32_t devcfg3;
+};
+#endif
+
+#define SDRAM_DEVCFG_EXTBUSWIDTH	(1 << 2)
+#define SDRAM_DEVCFG_BANKCOUNT		(1 << 3)
+#define SDRAM_DEVCFG_SROMLL		(1 << 5)
+#define SDRAM_DEVCFG_CASLAT_2		0x00010000
+#define SDRAM_DEVCFG_RASTOCAS_2		0x00200000
+
+#define GLCONFIG_INIT			(1 << 0)
+#define GLCONFIG_MRS			(1 << 1)
+#define GLCONFIG_SMEMBUSY		(1 << 5)
+#define GLCONFIG_LCR			(1 << 6)
+#define GLCONFIG_REARBEN		(1 << 7)
+#define GLCONFIG_CLKSHUTDOWN		(1 << 30)
+#define GLCONFIG_CKE			(1 << 31)
+
+/*
+ * 0x80070000 - 0x8007FFFF: Reserved
+ */
+
+/*
+ * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA
+ */
+#define SMC_OFFSET			0x080000
+#define SMC_BASE			(EP93XX_AHB_BASE | SMC_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct smc_regs {
+	uint32_t bcr0;
+	uint32_t bcr1;
+	uint32_t bcr2;
+	uint32_t bcr3;
+	uint32_t reserved0[2];
+	uint32_t bcr6;
+	uint32_t bcr7;
+#if defined(CONFIG_EP9315)
+	uint32_t pcattribute;
+	uint32_t pccommon;
+	uint32_t pcio;
+	uint32_t reserved1[5];
+	uint32_t pcmciactrl;
+#endif
+};
+#endif
+
+#define SMC_BCR_IDCY_SHIFT	0
+#define SMC_BCR_WST1_SHIFT	5
+#define SMC_BCR_BLE		(1 << 10)
+#define SMC_BCR_WST2_SHIFT	11
+#define SMC_BCR_MW_SHIFT	28
+
+/*
+ * 0x80090000 - 0x8009FFFF: Boot ROM
+ */
+
+/*
+ * 0x800A0000 - 0x800AFFFF: IDE interface
+ */
+
+/*
+ * 0x800B0000 - 0x800BFFFF: VIC1
+ */
+
+/*
+ * 0x800C0000 - 0x800CFFFF: VIC2
+ */
+
+/*
+ * 0x800D0000 - 0x800FFFFF: Reserved
+ */
+
+/*
+ * 0x80800000 - 0x8080FFFF: Reserved
+ */
+
+/*
+ * 0x80810000 - 0x8081FFFF: Timers
+ */
+#define TIMER_OFFSET		0x010000
+#define TIMER_BASE		(EP93XX_APB_BASE | TIMER_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct timer {
+	uint32_t load;
+	uint32_t value;
+	uint32_t control;
+	uint32_t clear;
+};
+
+struct timer4 {
+	uint32_t value_low;
+	uint32_t value_high;
+};
+
+struct timer_regs {
+	struct timer timer1;
+	uint32_t reserved0[4];
+	struct timer timer2;
+	uint32_t reserved1[12];
+	struct timer4 timer4;
+	uint32_t reserved2[6];
+	struct timer timer3;
+};
+#endif
+
+/*
+ * 0x80820000 - 0x8082FFFF: I2S
+ */
+#define I2S_OFFSET		0x020000
+#define I2S_BASE		(EP93XX_APB_BASE | I2S_OFFSET)
+
+/*
+ * 0x80830000 - 0x8083FFFF: Security
+ */
+#define SECURITY_OFFSET		0x030000
+#define SECURITY_BASE		(EP93XX_APB_BASE | SECURITY_OFFSET)
+
+#define EXTENSIONID		(SECURITY_BASE + 0x2714)
+
+/*
+ * 0x80840000 - 0x8084FFFF: GPIO
+ */
+#define GPIO_OFFSET		0x040000
+#define GPIO_BASE		(EP93XX_APB_BASE | GPIO_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct gpio_int {
+	uint32_t inttype1;
+	uint32_t inttype2;
+	uint32_t eoi;
+	uint32_t inten;
+	uint32_t intsts;
+	uint32_t rawintsts;
+	uint32_t db;
+};
+
+struct gpio_regs {
+	uint32_t padr;
+	uint32_t pbdr;
+	uint32_t pcdr;
+	uint32_t pddr;
+	uint32_t paddr;
+	uint32_t pbddr;
+	uint32_t pcddr;
+	uint32_t pdddr;
+	uint32_t pedr;
+	uint32_t peddr;
+	uint32_t reserved0[2];
+	uint32_t pfdr;
+	uint32_t pfddr;
+	uint32_t pgdr;
+	uint32_t pgddr;
+	uint32_t phdr;
+	uint32_t phddr;
+	uint32_t reserved1;
+	uint32_t finttype1;
+	uint32_t finttype2;
+	uint32_t reserved2;
+	struct gpio_int pfint;
+	uint32_t reserved3[10];
+	struct gpio_int paint;
+	struct gpio_int pbint;
+	uint32_t eedrive;
+};
+#endif
+
+/*
+ * 0x80850000 - 0x8087FFFF: Reserved
+ */
+
+/*
+ * 0x80880000 - 0x8088FFFF: AAC
+ */
+#define AAC_OFFSET		0x080000
+#define AAC_BASE		(EP93XX_APB_BASE | AAC_OFFSET)
+
+/*
+ * 0x80890000 - 0x8089FFFF: Reserved
+ */
+
+/*
+ * 0x808A0000 - 0x808AFFFF: SPI
+ */
+#define SPI_OFFSET		0x0A0000
+#define SPI_BASE		(EP93XX_APB_BASE | SPI_OFFSET)
+
+/*
+ * 0x808B0000 - 0x808BFFFF: IrDA
+ */
+#define IRDA_OFFSET		0x0B0000
+#define IRDA_BASE		(EP93XX_APB_BASE | IRDA_OFFSET)
+
+/*
+ * 0x808C0000 - 0x808CFFFF: UART1
+ */
+#define UART1_OFFSET		0x0C0000
+#define UART1_BASE		(EP93XX_APB_BASE | UART1_OFFSET)
+
+/*
+ * 0x808D0000 - 0x808DFFFF: UART2
+ */
+#define UART2_OFFSET		0x0D0000
+#define UART2_BASE		(EP93XX_APB_BASE | UART2_OFFSET)
+
+/*
+ * 0x808E0000 - 0x808EFFFF: UART3
+ */
+#define UART3_OFFSET		0x0E0000
+#define UART3_BASE		(EP93XX_APB_BASE | UART3_OFFSET)
+
+/*
+ * 0x808F0000 - 0x808FFFFF: Key Matrix
+ */
+#define KEY_OFFSET		0x0F0000
+#define KEY_BASE		(EP93XX_APB_BASE | KEY_OFFSET)
+
+/*
+ * 0x80900000 - 0x8090FFFF: Touchscreen
+ */
+#define TOUCH_OFFSET		0x900000
+#define TOUCH_BASE		(EP93XX_APB_BASE | TOUCH_OFFSET)
+
+/*
+ * 0x80910000 - 0x8091FFFF: Pulse Width Modulation
+ */
+#define PWM_OFFSET		0x910000
+#define PWM_BASE		(EP93XX_APB_BASE | PWM_OFFSET)
+
+/*
+ * 0x80920000 - 0x8092FFFF: Real time clock
+ */
+#define RTC_OFFSET		0x920000
+#define RTC_BASE		(EP93XX_APB_BASE | RTC_OFFSET)
+
+/*
+ * 0x80930000 - 0x8093FFFF: Syscon
+ */
+#define SYSCON_OFFSET		0x930000
+#define SYSCON_BASE		(EP93XX_APB_BASE | SYSCON_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct syscon_regs {
+	uint32_t pwrsts;
+	uint32_t pwrcnt;
+	uint32_t halt;
+	uint32_t stby;
+	uint32_t reserved0[2];
+	uint32_t teoi;
+	uint32_t stfclr;
+	uint32_t clkset1;
+	uint32_t clkset2;
+	uint32_t reserved1[6];
+	uint32_t scratch0;
+	uint32_t scratch1;
+	uint32_t reserved2[2];
+	uint32_t apbwait;
+	uint32_t bustmstrarb;
+	uint32_t bootmodeclr;
+	uint32_t reserved3[9];
+	uint32_t devicecfg;
+	uint32_t vidclkdiv;
+	uint32_t mirclkdiv;
+	uint32_t i2sclkdiv;
+	uint32_t keytchclkdiv;
+	uint32_t chipid;
+	uint32_t syscfg;
+	uint32_t reserved4[8];
+	uint32_t sysswlock;
+};
+#else
+#define SYSCON_SCRATCH0		(SYSCON_BASE + 0x0040)
+#endif
+
+#define SYSCON_PWRCNT_UART_BAUD			(1 << 29)
+
+#define SYSCON_CLKSET_PLL_X2IPD_SHIFT		0
+#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT		5
+#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT		11
+#define SYSCON_CLKSET_PLL_PS_SHIFT		16
+#define SYSCON_CLKSET1_PCLK_DIV_SHIFT		18
+#define SYSCON_CLKSET1_HCLK_DIV_SHIFT		20
+#define SYSCON_CLKSET1_NBYP1			(1 << 23)
+#define SYSCON_CLKSET1_FCLK_DIV_SHIFT		25
+
+#define SYSCON_CLKSET2_PLL2_EN			(1 << 18)
+#define SYSCON_CLKSET2_NBYP2			(1 << 19)
+#define SYSCON_CLKSET2_USB_DIV_SHIFT		28
+
+#define SYSCON_CHIPID_REV_MASK			0xF0000000
+#define SYSCON_DEVICECFG_SWRST			(1 << 31)
+
+/*
+ * 0x80930000 - 0x8093FFFF: Watchdog Timer
+ */
+#define WATCHDOG_OFFSET		0x940000
+#define WATCHDOG_BASE		(EP93XX_APB_BASE | WATCHDOG_OFFSET)
+
+/*
+ * 0x80950000 - 0x9000FFFF: Reserved
+ */

include/asm-arm/arch-omap3/cpu.h

@@ -136,6 +136,10 @@ struct gpmc {
 	u32 ecc8_result;	/* 0x21C */
 	u32 ecc9_result;	/* 0x220 */
 };
+
+/* Used for board specific gpmc initialization */
+extern struct gpmc *gpmc_cfg;
+
 #else /* __ASSEMBLY__ */
 #define GPMC_CONFIG1		0x00
 #define GPMC_CONFIG2		0x04

include/asm-ppc/immap_86xx.h

@@ -1186,17 +1186,8 @@ typedef struct ccsr_rio {
 typedef struct ccsr_gur {
 	uint	porpllsr;	/* 0xe0000 - POR PLL ratio status register */
 	uint	porbmsr;	/* 0xe0004 - POR boot mode status register */
-#define MPC8610_PORBMSR_HA      0x00070000
-#define MPC8610_PORBMSR_HA_SHIFT	16
-#define MPC8641_PORBMSR_HA      0x00060000
-#define MPC8641_PORBMSR_HA_SHIFT	17
 	uint	porimpscr;	/* 0xe0008 - POR I/O impedance status and control register */
 	uint	pordevsr;	/* 0xe000c - POR I/O device status regsiter */
-#define MPC8610_PORDEVSR_IO_SEL		0x00380000
-#define MPC8610_PORDEVSR_IO_SEL_SHIFT		19
-#define MPC8641_PORDEVSR_IO_SEL		0x000F0000
-#define MPC8641_PORDEVSR_IO_SEL_SHIFT		16
-#define MPC86xx_PORDEVSR_CORE1TE	0x00000080 /* ASMP (Core1 addr trans) */
 	uint	pordbgmsr;	/* 0xe0010 - POR debug mode status register */
 	char	res1[12];
 	uint	gpporcr;	/* 0xe0020 - General-purpose POR configuration register */
@@ -1210,11 +1201,6 @@ typedef struct ccsr_gur {
 	uint	pmuxcr;		/* 0xe0060 - Alternate function signal multiplex control */
 	char	res6[12];
 	uint	devdisr;	/* 0xe0070 - Device disable control */
-#define MPC86xx_DEVDISR_PCIEX1	0x80000000
-#define MPC86xx_DEVDISR_PCIEX2	0x40000000
-#define MPC86xx_DEVDISR_PCI1	0x80000000
-#define MPC86xx_DEVDISR_PCIE1	0x40000000
-#define MPC86xx_DEVDISR_PCIE2	0x20000000
 	char	res7[12];
 	uint	powmgtcsr;	/* 0xe0080 - Power management status and control register */
 	char	res8[12];
@@ -1225,7 +1211,6 @@ typedef struct ccsr_gur {
 	uint	svr;		/* 0xe00a4 - System version register */
 	char	res10a[8];
 	uint	rstcr;		/* 0xe00b0 - Reset control register */
-#define MPC86xx_RSTCR_HRST_REQ	0x00000002
 	char	res10b[1868];
 	uint	clkdvdr;	/* 0xe0800 - Clock Divide register */
 	char	res10c[796];
@@ -1250,6 +1235,24 @@ typedef struct ccsr_gur {
 	char	res16[184];
 } ccsr_gur_t;
 
+#define MPC8610_PORBMSR_HA      0x00070000
+#define MPC8610_PORBMSR_HA_SHIFT	16
+#define MPC8641_PORBMSR_HA      0x00060000
+#define MPC8641_PORBMSR_HA_SHIFT	17
+#define MPC8610_PORDEVSR_IO_SEL		0x00380000
+#define MPC8610_PORDEVSR_IO_SEL_SHIFT		19
+#define MPC8641_PORDEVSR_IO_SEL		0x000F0000
+#define MPC8641_PORDEVSR_IO_SEL_SHIFT		16
+#define MPC86xx_PORDEVSR_CORE1TE	0x00000080 /* ASMP (Core1 addr trans) */
+#define MPC86xx_DEVDISR_PCIEX1	0x80000000
+#define MPC86xx_DEVDISR_PCIEX2	0x40000000
+#define MPC86xx_DEVDISR_PCI1	0x80000000
+#define MPC86xx_DEVDISR_PCIE1	0x40000000
+#define MPC86xx_DEVDISR_PCIE2	0x20000000
+#define MPC86xx_DEVDISR_CPU0	0x00008000
+#define MPC86xx_DEVDISR_CPU1	0x00004000
+#define MPC86xx_RSTCR_HRST_REQ	0x00000002
+
 /*
  * Watchdog register block(0xe_4000-0xe_4fff)
  */

include/common.h

@@ -123,6 +123,11 @@ typedef volatile unsigned char	vu_char;
 #define debugX(level,fmt,args...)
 #endif	/* DEBUG */
 
+#define error(fmt, args...) do {					\
+		printf("ERROR: " fmt "\nat %s:%d/%s()\n",		\
+			##args, __FILE__, __LINE__, __func__);		\
+} while (0)
+
 #ifndef BUG
 #define BUG() do { \
 	printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
@@ -502,7 +507,8 @@ ulong	get_PCI_freq (void);
 #endif
 #if defined(CONFIG_S3C24X0) || \
     defined(CONFIG_LH7A40X) || \
-    defined(CONFIG_S3C6400)
+    defined(CONFIG_S3C6400) || \
+    defined(CONFIG_EP93XX)
 ulong	get_FCLK (void);
 ulong	get_HCLK (void);
 ulong	get_PCLK (void);
@@ -712,6 +718,7 @@ void show_boot_progress(int val);
 #ifdef CONFIG_MP
 int cpu_status(int nr);
 int cpu_reset(int nr);
+int cpu_disable(int nr);
 int cpu_release(int nr, int argc, char *argv[]);
 #endif
 

include/config_defaults.h

@@ -14,4 +14,7 @@
 #define CONFIG_BOOTM_NETBSD 1
 #define CONFIG_BOOTM_RTEMS 1
 
+#define CONFIG_GZIP 1
+#define CONFIG_ZLIB 1
+
 #endif

include/configs/MPC8569MDS.h

@@ -51,6 +51,11 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_CLK_FREQ	66666666
 #define CONFIG_DDR_CLK_FREQ	CONFIG_SYS_CLK_FREQ
 
+#ifdef CONFIG_MK_ATM
+#define CONFIG_PQ_MDS_PIB
+#define CONFIG_PQ_MDS_PIB_ATM
+#endif
+
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */

include/configs/P1_P2_RDB.h

@@ -203,6 +203,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 
 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+#define CONFIG_HWCONFIG
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR      0xffd00000	/* stack in RAM */

include/configs/devkit8000.h

@@ -297,7 +297,6 @@
 #define CONFIG_ENV_OFFSET		boot_flash_off
 
 #ifndef __ASSEMBLY__
-extern struct gpmc *gpmc_cfg;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

include/configs/edb93xx.h

@@ -0,0 +1,270 @@
+/*
+ * U-boot - Configuration file for Cirrus Logic EDB93xx boards
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_MK_edb9301
+#define CONFIG_EDB9301
+#elif defined(CONFIG_MK_edb9302)
+#define CONFIG_EDB9302
+#elif defined(CONFIG_MK_edb9302a)
+#define CONFIG_EDB9302A
+#elif defined(CONFIG_MK_edb9307)
+#define CONFIG_EDB9307
+#elif defined(CONFIG_MK_edb9307a)
+#define CONFIG_EDB9307A
+#elif defined(CONFIG_MK_edb9312)
+#define CONFIG_EDB9312
+#elif defined(CONFIG_MK_edb9315)
+#define CONFIG_EDB9315
+#elif defined(CONFIG_MK_edb9315a)
+#define CONFIG_EDB9315A
+#else
+#error "no board defined"
+#endif
+
+/* Initial environment and monitor configuration options. */
+#define CONFIG_BOOTDELAY		2
+#define CONFIG_CMDLINE_TAG		1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_BOOTARGS		"root=/dev/nfs console=ttyAM0,115200 ip=dhcp"
+#define CONFIG_BOOTFILE		"edb93xx.img"
+
+#define CONFIG_SYS_HUSH_PARSER		1
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+#ifdef CONFIG_EDB9301
+#define CONFIG_EP9301
+#define CONFIG_MACH_TYPE		MACH_TYPE_EDB9301
+#define CONFIG_SYS_PROMPT		"EDB9301> "
+#define CONFIG_ENV_SECT_SIZE		0x00020000
+#elif defined(CONFIG_EDB9302)
+#define CONFIG_EP9302
+#define CONFIG_MACH_TYPE		MACH_TYPE_EDB9302
+#define CONFIG_SYS_PROMPT		"EDB9302> "
+#define CONFIG_ENV_SECT_SIZE		0x00020000
+#elif defined(CONFIG_EDB9302A)
+#define CONFIG_EP9302
+#define CONFIG_MACH_TYPE		MACH_TYPE_EDB9302A
+#define CONFIG_SYS_PROMPT		"EDB9302A> "
+#define CONFIG_ENV_SECT_SIZE		0x00020000
+#elif defined(CONFIG_EDB9307)
+#define CONFIG_EP9307
+#define CONFIG_MACH_TYPE		MACH_TYPE_EDB9307
+#define CONFIG_SYS_PROMPT		"EDB9307> "
+#define CONFIG_ENV_SECT_SIZE		0x00040000
+#elif defined(CONFIG_EDB9307A)
+#define CONFIG_EP9307
+#define CONFIG_MACH_TYPE		MACH_TYPE_EDB9307A
+#define CONFIG_SYS_PROMPT		"EDB9307A> "
+#define CONFIG_ENV_SECT_SIZE		0x00040000
+#elif defined(CONFIG_EDB9312)
+#define CONFIG_EP9312
+#define CONFIG_MACH_TYPE		MACH_TYPE_EDB9312
+#define CONFIG_SYS_PROMPT		"EDB9312> "
+#define CONFIG_ENV_SECT_SIZE		0x00040000
+#elif defined(CONFIG_EDB9315)
+#define CONFIG_EP9315
+#define CONFIG_MACH_TYPE		MACH_TYPE_EDB9315
+#define CONFIG_SYS_PROMPT		"EDB9315> "
+#define CONFIG_ENV_SECT_SIZE		0x00040000
+#elif defined(CONFIG_EDB9315A)
+#define CONFIG_EP9315
+#define CONFIG_MACH_TYPE		MACH_TYPE_EDB9315A
+#define CONFIG_SYS_PROMPT		"EDB9315A> "
+#define CONFIG_ENV_SECT_SIZE		0x00040000
+#else
+#error "no board defined"
+#endif
+
+/* High-level configuration options */
+#define CONFIG_ARM920T		1		/* This is an ARM920T core... */
+#define CONFIG_EP93XX 		1		/* in a Cirrus Logic 93xx SoC */
+
+#define CONFIG_SYS_CLK_FREQ	14745600	/* EP93xx has a 14.7456 clock */
+#define CONFIG_SYS_HZ		1000		/* decr freq: 1 ms ticks      */
+#undef  CONFIG_USE_IRQ				/* Don't need IRQ/FIQ         */
+
+/* Monitor configuration */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#undef CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+
+#define CONFIG_SYS_LONGHELP			/* Enable "long" help in mon */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O buffer size */
+/* Print buffer size */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+/* Boot argument buffer size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_MAXARGS	16		/* Max number of command args */
+
+/* Serial port hardware configuration */
+#define CONFIG_PL010_SERIAL
+#define CONFIG_CONS_INDEX		0
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_SERIAL0		0x808C0000
+#define CONFIG_SYS_SERIAL1		0x808D0000
+#define CONFIG_PL01x_PORTS	{(void *)CONFIG_SYS_SERIAL0, \
+			(void *)CONFIG_SYS_SERIAL1}
+
+/* Status LED */
+#define CONFIG_STATUS_LED		1 /* Status LED enabled	*/
+#define CONFIG_BOARD_SPECIFIC_LED	1
+#define STATUS_LED_GREEN		0
+#define STATUS_LED_RED			1
+/* Green */
+#define STATUS_LED_BIT			STATUS_LED_GREEN
+#define STATUS_LED_STATE		STATUS_LED_ON
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
+/* Red */
+#define STATUS_LED_BIT1			STATUS_LED_RED
+#define STATUS_LED_STATE1		STATUS_LED_OFF
+#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 2)
+/* Optional value */
+#define STATUS_LED_BOOT			STATUS_LED_BIT
+
+/* Network hardware configuration */
+#define CONFIG_DRIVER_EP93XX_MAC
+#define CONFIG_MII_SUPPRESS_PREAMBLE
+#define CONFIG_MII
+#define CONFIG_PHY_ADDR		1
+#define CONFIG_NET_MULTI
+#undef  CONFIG_NETCONSOLE
+
+/* SDRAM configuration */
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302)
+/*
+ * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
+ * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
+ * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
+ */
+#define CONFIG_NR_DRAM_BANKS		4
+#define PHYS_SDRAM_1			0x00000000
+#define PHYS_SDRAM_SIZE_1		0x00800000
+#define PHYS_SDRAM_2			0x01000000
+#define PHYS_SDRAM_SIZE_2		0x00800000
+#define PHYS_SDRAM_3			0x04000000
+#define PHYS_SDRAM_SIZE_3		0x00800000
+#define PHYS_SDRAM_4			0x05000000
+#define PHYS_SDRAM_SIZE_4		0x00800000
+#define CONFIG_EDB93XX_SDCS3
+#define CONFIG_SYS_MEMTEST_START	0x00100000
+#define CONFIG_SYS_MEMTEST_END		0x007fffff
+
+#elif defined(CONFIG_EDB9302A)
+/*
+ * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
+ * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
+ * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
+ */
+#define CONFIG_NR_DRAM_BANKS		4
+#define PHYS_SDRAM_1			0xc0000000
+#define PHYS_SDRAM_SIZE_1		0x00800000
+#define PHYS_SDRAM_2			0xc1000000
+#define PHYS_SDRAM_SIZE_2		0x00800000
+#define PHYS_SDRAM_3			0xc4000000
+#define PHYS_SDRAM_SIZE_3		0x00800000
+#define PHYS_SDRAM_4			0xc5000000
+#define PHYS_SDRAM_SIZE_4		0x00800000
+#define CONFIG_EDB93XX_SDCS0
+#define CONFIG_SYS_MEMTEST_START	0xc0100000
+#define CONFIG_SYS_MEMTEST_END		0xc07fffff
+
+#elif defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \
+	defined(CONFIG_EDB9315)
+/*
+ * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of
+ * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of
+ * 64 MB of SDRAM.
+ */
+#define CONFIG_NR_DRAM_BANKS		2
+#define PHYS_SDRAM_1			0x00000000
+#define PHYS_SDRAM_SIZE_1		0x02000000
+#define PHYS_SDRAM_2			0x04000000
+#define PHYS_SDRAM_SIZE_2		0x02000000
+#define CONFIG_EDB93XX_SDCS3
+#define CONFIG_SYS_MEMTEST_START	0x00100000
+#define CONFIG_SYS_MEMTEST_END		0x01e00000
+
+#elif defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A)
+/*
+ * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung
+ * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM.
+ */
+#define CONFIG_NR_DRAM_BANKS		2
+#define PHYS_SDRAM_1			0xc0000000
+#define PHYS_SDRAM_SIZE_1		0x02000000
+#define PHYS_SDRAM_2			0xc4000000
+#define PHYS_SDRAM_SIZE_2		0x02000000
+#define CONFIG_EDB93XX_SDCS0
+#define CONFIG_SYS_MEMTEST_START	0xc0100000
+#define CONFIG_SYS_MEMTEST_END		0xc1e00000
+#endif
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR   (PHYS_SDRAM_1 + 0x01000000)
+
+/* Must match kernel config */
+#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
+
+/* Run-time memory allocatons */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+#define CONFIG_STACKSIZE		(128 * 1024)
+
+#if defined(CONFIG_USE_IRQ)
+#define CONFIG_STACKSIZE_IRQ	(4 * 1024)
+#define CONFIG_STACKSIZE_FIQ	(4 * 1024)
+#endif
+
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
+
+/* -----------------------------------------------------------------------------
+ * FLASH and environment organization
+ *
+ * The EDB9301 and EDB9302(a) have 1 bank of flash memory at 0x60000000
+ * consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit data bus,
+ * for a total of 16 MB of CFI-compatible flash.
+ *
+ * The EDB9307(a), EDB9312, and EDB9315(a) have 1 bank of flash memory at
+ * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit
+ * data bus, for a total of 32 MB of CFI-compatible flash.
+ *
+ *                            EDB9301/02(a)          EDB9307(a)/12/15(a)
+ * 0x60000000 - 0x0003FFFF    u-boot                 u-boot
+ * 0x60040000 - 0x0005FFFF    environment #1         environment #1
+ * 0x60060000 - 0x0007FFFF    environment #2         environment #1 (continued)
+ * 0x60080000 - 0x0009FFFF    unused                 environment #2
+ * 0x600A0000 - 0x000BFFFF    unused                 environment #2 (continued)
+ * 0x600C0000 - 0x00FFFFFF    unused                 unused
+ * 0x61000000 - 0x01FFFFFF    not present            unused
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+#define PHYS_FLASH_1			0x60000000
+#define CONFIG_SYS_FLASH_BASE		(PHYS_FLASH_1)
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+
+#define CONFIG_ENV_OVERWRITE		/* Vendor params unprotected */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			0x60040000
+
+#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+
+#endif /* !defined (__CONFIG_H) */

include/configs/kilauea.h

@@ -47,6 +47,7 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
 #define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
+#define CONFIG_BOARD_TYPES
 #define CONFIG_BOARD_EMAC_COUNT
 
 /*-----------------------------------------------------------------------
@@ -520,9 +521,22 @@
 #define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_NAND_ADDR | 0x1e000)
 #endif
 
-/* Memory Bank 2 (FPGA) initialization						*/
+/* Memory Bank 2 (FPGA) initialization					*/
-#define CONFIG_SYS_EBC_PB2AP           0x9400C800
+#define CONFIG_SYS_EBC_PB2AP		(EBC_BXAP_BME_ENABLED |		\
-#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA_BASE | 0x18000)
+					 EBC_BXAP_FWT_ENCODE(6) |	\
+					 EBC_BXAP_BWT_ENCODE(1) |	\
+					 EBC_BXAP_BCE_DISABLE |		\
+					 EBC_BXAP_BCT_2TRANS |		\
+					 EBC_BXAP_CSN_ENCODE(0) |	\
+					 EBC_BXAP_OEN_ENCODE(0) |	\
+					 EBC_BXAP_WBN_ENCODE(3) |	\
+					 EBC_BXAP_WBF_ENCODE(1) |	\
+					 EBC_BXAP_TH_ENCODE(4) |	\
+					 EBC_BXAP_RE_DISABLED |		\
+					 EBC_BXAP_SOR_DELAYED |		\
+					 EBC_BXAP_BEM_WRITEONLY |	\
+					 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB2CR	(CONFIG_SYS_FPGA_BASE | 0x18000)
 
 #define CONFIG_SYS_EBC_CFG		0x7FC00000 /*  EBC0_CFG */
 
@@ -571,7 +585,7 @@
  * Some Kilauea stuff..., mainly fpga registers
  */
 #define CONFIG_SYS_FPGA_REG_BASE		CONFIG_SYS_FPGA_BASE
-#define CONFIG_SYS_FPGA_FIFO_BASE		(in32(CONFIG_SYS_FPGA_BASE) | (1 << 10))
+#define CONFIG_SYS_FPGA_FIFO_BASE		(CONFIG_SYS_FPGA_BASE | (1 << 10))
 
 /* interrupt */
 #define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT	0x80000000
@@ -602,4 +616,8 @@
 #define CONFIG_SYS_FPGA_USER_LED0		0x00000200
 #define CONFIG_SYS_FPGA_USER_LED1		0x00000100
 
+#define CONFIG_SYS_FPGA_MAGIC_MASK		0xffff0000
+#define CONFIG_SYS_FPGA_MAGIC			0xabcd0000
+#define CONFIG_SYS_FPGA_VER_MASK		0x0000ff00
+
 #endif	/* __CONFIG_H */

include/configs/kmeter1.h

@@ -33,6 +33,8 @@
 /* include common defines/options for all Keymile boards */
 #include "keymile-common.h"
 
+#define CONFIG_KM_UBI_PARTITION_NAME	"ubi0"
+
 #define MTDIDS_DEFAULT		"nor0=boot"
 #define MTDPARTS_DEFAULT	\
 	"mtdparts=boot:768k(u-boot),128k(env),128k(envred),"	\
@@ -449,11 +451,6 @@
 
 #define CONFIG_PRAM	512	/* protected RAM [KBytes] */
 
-#define MTDIDS_DEFAULT		"nor2=app"
-#define MTDPARTS_DEFAULT \
-	"mtdparts=app:256k(u-boot),128k(env),128k(envred),"	\
-	"1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var),768k(cfg)"
-
 /*
  * Environment Configuration
  */

include/configs/netstar.h

@@ -149,7 +149,6 @@
 #define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_IMI
-#define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_LOADB
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_NAND
@@ -158,8 +157,6 @@
 #define CONFIG_CMD_RUN
 
 
-#define CONFIG_JFFS2_NAND	1	/* jffs2 on nand support */
-
 /*
  * BOOTP options
  */

include/configs/omap3_beagle.h

@@ -326,7 +326,6 @@
 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
 
 #ifndef __ASSEMBLY__
-extern struct gpmc *gpmc_cfg;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

include/configs/omap3_evm.h

@@ -330,7 +330,6 @@
 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
 
 #ifndef __ASSEMBLY__
-extern struct gpmc *gpmc_cfg;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

include/configs/omap3_overo.h

@@ -295,7 +295,6 @@
 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
 
 #ifndef __ASSEMBLY__
-extern struct gpmc *gpmc_cfg;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

include/configs/omap3_pandora.h

@@ -287,7 +287,6 @@
 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
 
 #ifndef __ASSEMBLY__
-extern struct gpmc *gpmc_cfg;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

include/configs/omap3_sdp3430.h

@@ -361,7 +361,6 @@
 /*--------------------------------------------------------------------------*/
 
 #ifndef __ASSEMBLY__
-extern struct gpmc *gpmc_cfg;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

include/configs/omap3_zoom1.h

@@ -311,7 +311,6 @@
 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
 
 #ifndef __ASSEMBLY__
-extern struct gpmc *gpmc_cfg;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

include/configs/omap3_zoom2.h

@@ -270,7 +270,6 @@
 #define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
 
 #ifndef __ASSEMBLY__
-extern struct gpmc *gpmc_cfg;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

include/configs/otc570.h

@@ -0,0 +1,246 @@
+/*
+ * (C) Copyright 2010
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the esd OTC570 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Common stuff */
+#define CONFIG_OTC570			1	/* Board is esd OTC570 */
+#define CONFIG_ARM926EJS		1	/* This is an ARM926EJS Core */
+#define CONFIG_AT91SAM9263		1	/* It's an AT91SAM9263 SoC */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq */
+#define CONFIG_DISPLAY_BOARDINFO	1
+#define CONFIG_DISPLAY_CPUINFO		1	/* display cpu info and speed */
+#define CONFIG_PREBOOT				/* enable preboot variable */
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_SERIAL_TAG		1
+#define CONFIG_REVISION_TAG		1
+#undef CONFIG_USE_IRQ				/* don't need IRQ/FIQ stuff */
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_MISC_INIT_R		1	/* Call misc_init_r */
+
+#define CONFIG_ARCH_CPU_INIT
+
+/*
+ * Hardware drivers
+ */
+
+/* Console output */
+#define CONFIG_ATMEL_USART		1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3			1	/* USART 3 is DBGU */
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK	1
+
+/* LCD */
+#define CONFIG_LCD			1
+#define LCD_BPP				LCD_COLOR8
+
+#undef CONFIG_SPLASH_SCREEN
+
+#ifndef CONFIG_SPLASH_SCREEN
+#define CONFIG_LCD_LOGO			1
+#define CONFIG_LCD_INFO			1
+#undef CONFIG_LCD_INFO_BELOW_LOGO
+#endif /* CONFIG_SPLASH_SCREEN */
+
+#undef LCD_TEST_PATTERN
+#define CONFIG_SYS_WHITE_ON_BLACK	1
+#define CONFIG_ATMEL_LCD		1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+#define CONFIG_OTC570_LCD_BASE		0x23E00000	/* LCD is in SDRAM */
+#define CONFIG_CMD_BMP			1
+
+/* RTC and I2C stuff */
+#define CONFIG_RTC_DS1338		1
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#undef CONFIG_HARD_I2C
+#define CONFIG_SOFT_I2C			1
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+#ifdef CONFIG_SOFT_I2C
+#define CONFIG_I2C_CMD_TREE		1
+#define CONFIG_I2C_MULTI_BUS		1
+/* Enable peripheral clock and configure data and clock pins for pio */
+#define I2C_INIT { \
+	at91_sys_write(AT91_PMC_PCER,	1 << AT91SAM9263_ID_PIOB |	\
+					1 << AT91SAM9263_ID_PIOCDE);	\
+	at91_set_gpio_output(AT91_PIN_PB4, 0);				\
+	at91_set_gpio_output(AT91_PIN_PB5, 0);				\
+}
+/* Configure data pin as output */
+#define I2C_ACTIVE			at91_set_gpio_output(AT91_PIN_PB4, 0)
+/* Configure data pin as input */
+#define I2C_TRISTATE			at91_set_gpio_input(AT91_PIN_PB4, 0)
+/* Read data pin */
+#define I2C_READ			at91_get_gpio_value(AT91_PIN_PB4)
+/* Set data pin */
+#define I2C_SDA(bit)			at91_set_gpio_value(AT91_PIN_PB4, bit)
+/* Set clock pin */
+#define I2C_SCL(bit)			at91_set_gpio_value(AT91_PIN_PB5, bit)
+#define I2C_DELAY			udelay(2) /* 1/4 I2C clock duration */
+#endif /* CONFIG_SOFT_I2C */
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK	1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE	1
+#define CONFIG_BOOTP_BOOTPATH		1
+#define CONFIG_BOOTP_GATEWAY		1
+#define CONFIG_BOOTP_HOSTNAME		1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_PING			1
+#define CONFIG_CMD_DHCP			1
+#define CONFIG_CMD_NAND			1
+#define CONFIG_CMD_USB			1
+#define CONFIG_CMD_I2C			1
+#define CONFIG_CMD_DATE			1
+
+/* LED */
+#define CONFIG_AT91_LED			1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS			1
+#define PHYS_SDRAM				0x20000000
+
+/* DataFlash */
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_HAS_DATAFLASH			1
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+#define AT91_SPI_CLK				15000000
+#define DATAFLASH_TCSS				(0x1a << 16)
+#define DATAFLASH_TCHS				(0x1 << 24)
+
+/* NOR flash is not populated, disable it */
+#define CONFIG_SYS_NO_FLASH			1
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			0x40000000
+#define CONFIG_SYS_NAND_DBW_8			1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PD15
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PA22
+#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB				1
+#define CONFIG_RMII				1
+#define CONFIG_NET_MULTI			1
+#define CONFIG_NET_RETRY_COUNT			20
+#undef CONFIG_RESET_PHY_R
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW			1
+#define CONFIG_DOS_PARTITION			1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE			1
+#define CONFIG_CMD_FAT				1
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000 /* load address */
+
+#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
+
+#define CONFIG_SYS_USE_DATAFLASH		1
+#undef CONFIG_SYS_USE_NANDFLASH
+
+/* CAN */
+#define CONFIG_AT91_CAN				1
+
+/* hw-controller addresses */
+#define CONFIG_ET1100_BASE			0x70000000
+
+/* bootstrap + u-boot + env in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_DATAFLASH	1
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
+					0x8400)
+#define CONFIG_ENV_OFFSET		0x4200
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
+					CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE			0x4200
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + \
+					128*1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif

include/fsl_esdhc.h

@@ -32,7 +32,7 @@
 #define SYSCTL			0x0002e02c
 #define SYSCTL_INITA		0x08000000
 #define SYSCTL_TIMEOUT_MASK	0x000f0000
-#define SYSCTL_CLOCK_MASK	0x00000fff
+#define SYSCTL_CLOCK_MASK	0x0000fff0
 #define SYSCTL_PEREN		0x00000004
 #define SYSCTL_HCKEN		0x00000002
 #define SYSCTL_IPGEN		0x00000001

include/image.h

@@ -156,6 +156,7 @@
 #define IH_TYPE_FILESYSTEM	7	/* Filesystem Image (any type)	*/
 #define IH_TYPE_FLATDT		8	/* Binary Flat Device Tree Blob	*/
 #define IH_TYPE_KWBIMAGE	9	/* Kirkwood Boot Image		*/
+#define IH_TYPE_IMXIMAGE	10	/* Freescale IMXBoot Image	*/
 
 /*
  * Compression Types

include/netdev.h

@@ -49,6 +49,7 @@ int davinci_emac_initialize(void);
 int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
 int e1000_initialize(bd_t *bis);
 int eepro100_initialize(bd_t *bis);
+int ep93xx_eth_initialize(u8 dev_num, int base_addr);
 int eth_3com_initialize (bd_t * bis);
 int fec_initialize (bd_t *bis);
 int fecmxc_initialize (bd_t *bis);