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https://source.denx.de/u-boot/u-boot.git
synced 2026-05-04 20:26:13 +02:00
usb: dwc2: Replace uint<x>_t types with u<x>
Updates all instances of uint8_t, uint16_t, and uint32_t to u8, u16, and u32 respectively, ensuring consistent use of kernel-preferred types and resolving checkpatch.pl warnings. Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Tested-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Link: https://lore.kernel.org/r/20250110-dwc2-dev-v4-8-987f4fd6f8b2@pigmoral.tech Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
This commit is contained in:
Kongyang Liu
Mattijs Korpershoek
parent
c5d685b899
commit
bd88148a1b
@ -466,8 +466,8 @@ static void reconfig_usbd(struct dwc2_udc *dev)
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/* 2. Soft-reset OTG Core and then unreset again. */
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int i;
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unsigned int uTemp;
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uint32_t dflt_gusbcfg;
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uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz;
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u32 dflt_gusbcfg;
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u32 rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz;
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u32 max_hw_ep;
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int pdata_hw_ep;
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@ -39,16 +39,16 @@
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struct dwc2_priv {
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#if CONFIG_IS_ENABLED(DM_USB)
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uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
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uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
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u8 aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
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u8 status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
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#ifdef CONFIG_DM_REGULATOR
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struct udevice *vbus_supply;
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#endif
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struct phy phy;
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struct clk_bulk clks;
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#else
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uint8_t *aligned_buffer;
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uint8_t *status_buffer;
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u8 *aligned_buffer;
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u8 *status_buffer;
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#endif
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u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
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u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
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@ -67,10 +67,10 @@ struct dwc2_priv {
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#if !CONFIG_IS_ENABLED(DM_USB)
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/* We need cacheline-aligned buffers for DMA transfers and dcache support */
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DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
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ARCH_DMA_MINALIGN);
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DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
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ARCH_DMA_MINALIGN);
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DEFINE_ALIGN_BUFFER(u8, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
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ARCH_DMA_MINALIGN);
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DEFINE_ALIGN_BUFFER(u8, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
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ARCH_DMA_MINALIGN);
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static struct dwc2_priv local;
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#endif
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@ -85,7 +85,7 @@ static struct dwc2_priv local;
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*/
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static void init_fslspclksel(struct dwc2_core_regs *regs)
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{
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uint32_t phyclk;
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u32 phyclk;
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#if (DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
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phyclk = HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
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@ -95,9 +95,9 @@ static void init_fslspclksel(struct dwc2_core_regs *regs)
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#endif
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#ifdef DWC2_ULPI_FS_LS
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uint32_t hwcfg2 = readl(®s->global_regs.ghwcfg2);
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uint32_t hval = FIELD_GET(GHWCFG2_HS_PHY_TYPE_MASK, ghwcfg2);
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uint32_t fval = FIELD_GET(GHWCFG2_FS_PHY_TYPE_MASK, ghwcfg2);
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u32 hwcfg2 = readl(®s->global_regs.ghwcfg2);
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u32 hval = FIELD_GET(GHWCFG2_HS_PHY_TYPE_MASK, ghwcfg2);
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u32 fval = FIELD_GET(GHWCFG2_FS_PHY_TYPE_MASK, ghwcfg2);
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if (hval == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI && fval == GHWCFG2_HS_PHY_TYPE_UTMI)
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phyclk = HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
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@ -172,9 +172,9 @@ static int dwc_vbus_supply_exit(struct udevice *dev)
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static void dwc_otg_core_host_init(struct udevice *dev,
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struct dwc2_core_regs *regs)
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{
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uint32_t nptxfifosize = 0;
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uint32_t ptxfifosize = 0;
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uint32_t hprt0 = 0;
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u32 nptxfifosize = 0;
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u32 ptxfifosize = 0;
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u32 hprt0 = 0;
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int i, ret, num_channels;
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/* Restart the Phy Clock */
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@ -253,9 +253,9 @@ static void dwc_otg_core_init(struct udevice *dev)
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{
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struct dwc2_priv *priv = dev_get_priv(dev);
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struct dwc2_core_regs *regs = priv->regs;
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uint32_t ahbcfg = 0;
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uint32_t usbcfg = 0;
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uint8_t brst_sz = DWC2_DMA_BURST_SIZE;
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u32 ahbcfg = 0;
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u32 usbcfg = 0;
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u8 brst_sz = DWC2_DMA_BURST_SIZE;
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/* Common Initialization */
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usbcfg = readl(®s->global_regs.gusbcfg);
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@ -347,9 +347,9 @@ static void dwc_otg_core_init(struct udevice *dev)
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usbcfg = readl(®s->global_regs.gusbcfg);
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usbcfg &= ~(GUSBCFG_ULPI_FS_LS | GUSBCFG_ULPI_CLK_SUSP_M);
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#ifdef DWC2_ULPI_FS_LS
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uint32_t hwcfg2 = readl(®s->global_regs.ghwcfg2);
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uint32_t hval = FIELD_GET(GHWCFG2_HS_PHY_TYPE_MASK, ghwcfg2);
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uint32_t fval = FIELD_GET(GHWCFG2_FS_PHY_TYPE_MASK, ghwcfg2);
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u32 hwcfg2 = readl(®s->global_regs.ghwcfg2);
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u32 hval = FIELD_GET(GHWCFG2_HS_PHY_TYPE_MASK, ghwcfg2);
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u32 fval = FIELD_GET(GHWCFG2_FS_PHY_TYPE_MASK, ghwcfg2);
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if (hval == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI && fval == GHWCFG2_HS_PHY_TYPE_UTMI) {
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usbcfg |= GUSBCFG_ULPI_FS_LS;
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@ -402,9 +402,9 @@ static void dwc_otg_core_init(struct udevice *dev)
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* @param regs Programming view of DWC_otg controller
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* @param hc Information needed to initialize the host channel
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*/
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static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
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struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
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uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
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static void dwc_otg_hc_init(struct dwc2_core_regs *regs, u8 hc_num,
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struct usb_device *dev, u8 dev_addr, u8 ep_num,
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u8 ep_is_in, u8 ep_type, u16 max_packet)
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{
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struct dwc2_hc_regs *hc_regs = ®s->host_regs.hc[hc_num];
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u32 hcchar = FIELD_PREP(HCCHAR_DEVADDR_MASK, dev_addr) |
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@ -427,9 +427,9 @@ static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
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}
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static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
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uint8_t hub_devnum, uint8_t hub_port)
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u8 hub_devnum, u8 hub_port)
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{
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uint32_t hcsplt = 0;
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u32 hcsplt = 0;
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hcsplt = HCSPLT_SPLTENA;
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hcsplt |= FIELD_PREP(HCSPLT_HUBADDR_MASK, hub_devnum);
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@ -447,24 +447,24 @@ static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
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struct usb_device *dev, void *buffer,
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int txlen, struct devrequest *cmd)
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{
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uint32_t hprt0 = 0;
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uint32_t port_status = 0;
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uint32_t port_change = 0;
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u32 hprt0 = 0;
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u32 port_status = 0;
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u32 port_change = 0;
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int len = 0;
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int stat = 0;
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switch (cmd->requesttype & ~USB_DIR_IN) {
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case 0:
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*(uint16_t *)buffer = cpu_to_le16(1);
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*(u16 *)buffer = cpu_to_le16(1);
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len = 2;
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break;
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case USB_RECIP_INTERFACE:
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case USB_RECIP_ENDPOINT:
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*(uint16_t *)buffer = cpu_to_le16(0);
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*(u16 *)buffer = cpu_to_le16(0);
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len = 2;
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break;
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case USB_TYPE_CLASS:
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*(uint32_t *)buffer = cpu_to_le32(0);
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*(u32 *)buffer = cpu_to_le32(0);
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len = 4;
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break;
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case USB_RECIP_OTHER | USB_TYPE_CLASS:
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@ -498,7 +498,7 @@ static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
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if (hprt0 & HPRT0_OVRCURRCHG)
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port_change |= USB_PORT_STAT_C_OVERCURRENT;
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*(uint32_t *)buffer = cpu_to_le32(port_status |
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*(u32 *)buffer = cpu_to_le32(port_status |
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(port_change << 16));
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len = 4;
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break;
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@ -519,11 +519,11 @@ static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
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struct devrequest *cmd)
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{
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unsigned char data[32];
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uint32_t dsc;
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u32 dsc;
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int len = 0;
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int stat = 0;
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uint16_t wValue = cpu_to_le16(cmd->value);
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uint16_t wLength = cpu_to_le16(cmd->length);
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u16 wValue = cpu_to_le16(cmd->value);
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u16 wLength = cpu_to_le16(cmd->length);
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switch (cmd->requesttype & ~USB_DIR_IN) {
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case 0:
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@ -606,7 +606,7 @@ static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
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switch (cmd->requesttype & ~USB_DIR_IN) {
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case 0:
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*(uint8_t *)buffer = 0x01;
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*(u8 *)buffer = 0x01;
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len = 1;
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break;
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default:
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@ -650,8 +650,8 @@ static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
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struct dwc2_core_regs *regs = priv->regs;
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int len = 0;
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int stat = 0;
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uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
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uint16_t wValue = cpu_to_le16(cmd->value);
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u16 bmrtype_breq = cmd->requesttype | (cmd->request << 8);
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u16 wValue = cpu_to_le16(cmd->value);
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switch (bmrtype_breq & ~USB_DIR_IN) {
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case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
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@ -724,10 +724,10 @@ static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
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return stat;
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}
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int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
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int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, u32 *sub, u8 *toggle)
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{
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int ret;
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uint32_t hcint, hctsiz;
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u32 hcint, hctsiz;
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ret = wait_for_bit_le32(&hc_regs->hcint, HCINTMSK_CHHLTD, true,
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2000, false);
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@ -764,7 +764,7 @@ static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
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int xfer_len, int *actual_len, int odd_frame)
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{
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int ret = 0;
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uint32_t sub;
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u32 sub;
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debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
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*pid, xfer_len, num_packets);
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@ -834,10 +834,10 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
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int ret = 0;
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int do_split = 0;
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int complete_split = 0;
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uint32_t xfer_len;
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uint32_t num_packets;
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u32 xfer_len;
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u32 num_packets;
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int stop_transfer = 0;
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uint32_t max_xfer_len;
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u32 max_xfer_len;
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int ssplit_frame_num = 0;
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debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
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@ -859,9 +859,9 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
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/* Check if the target is a FS/LS device behind a HS hub */
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if (dev->speed != USB_SPEED_HIGH) {
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uint8_t hub_addr;
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uint8_t hub_port;
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uint32_t hprt0 = readl(®s->host_regs.hprt0);
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u8 hub_addr;
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u8 hub_port;
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u32 hprt0 = readl(®s->host_regs.hprt0);
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if (FIELD_GET(HPRT0_SPD_MASK, hprt0) == HPRT0_SPD_HIGH_SPEED) {
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usb_find_usb2_hub_address_port(dev, &hub_addr,
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@ -876,7 +876,7 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
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do {
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int actual_len = 0;
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uint32_t hcint;
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u32 hcint;
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int odd_frame = 0;
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xfer_len = len - done;
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@ -1083,7 +1083,7 @@ static int dwc2_reset(struct udevice *dev)
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static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
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{
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struct dwc2_core_regs *regs = priv->regs;
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uint32_t snpsid;
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u32 snpsid;
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int i, j;
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int ret;
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