Xilinx fixes for v2020.04-rc4

- Fix link good bit handling in dp83867
 - Rename generic Zynq defconfig
 - Fix zybo z7 low leve setup
 - Fix error path in zynq_gem driver and fix 64bit usage
 - Fix invalid clock name quieries for Versal
 - Fix zynq/zynqmp SPL low level configuration via DT selection
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCXlywqgAKCRDKSWXLKUoM
 IWNzAJ0fVSiXix2p49pKgI8N0f0SU/QPAACfTE+auG3EEmq7WfoXXvK+bzsI4eQ=
 =oFil
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2020.04-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx fixes for v2020.04-rc4

- Fix link good bit handling in dp83867
- Rename generic Zynq defconfig
- Fix zybo z7 low leve setup
- Fix error path in zynq_gem driver and fix 64bit usage
- Fix invalid clock name quieries for Versal
- Fix zynq/zynqmp SPL low level configuration via DT selection

board/xilinx/zynq/MAINTAINERS

@@ -5,3 +5,4 @@ F:	arch/arm/dts/zynq-*
 F:	board/xilinx/zynq/
 F:	include/configs/zynq*.h
 F:	configs/zynq_*_defconfig
+F:	configs/xilinx_zynq_*

board/xilinx/zynq/Makefile

@@ -13,6 +13,11 @@ spl/board/xilinx/zynq/ps_init_gpl.o board/xilinx/zynq/ps_init_gpl.o: $(PS_INIT_F
 	$(CC) $(c_flags) -I $(srctree)/$(src) -c -o $@ $^
 endif
 
+DEVICE_TREE ?= $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%)
+ifeq ($(DEVICE_TREE),)
+DEVICE_TREE := unset
+endif
+
 ifeq ($(init-objs),)
 hw-platform-y :=$(shell echo $(DEVICE_TREE))
 init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/ps7_init_gpl.c),\

board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c

@@ -219,8 +219,8 @@ static unsigned long ps7_mio_init_data_3_0[] = {
 	EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00001201U),
 	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000012E0U),
 	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000012E1U),
-	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000200U),
-	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000200U),
 	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U),
 	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U),
 	EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002F0037U),

board/xilinx/zynqmp/Makefile

@@ -13,6 +13,11 @@ spl/board/xilinx/zynqmp/ps_init_gpl.o board/xilinx/zynqmp/ps_init_gpl.o: $(PS_IN
 	$(CC) $(c_flags) -I $(srctree)/$(src) -c -o $@ $^
 endif
 
+DEVICE_TREE ?= $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%)
+ifeq ($(DEVICE_TREE),)
+DEVICE_TREE := unset
+endif
+
 ifeq ($(init-objs),)
 hw-platform-y :=$(shell echo $(DEVICE_TREE))
 init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\

configs/zynq_zybo_z7_defconfig

@@ -6,7 +6,7 @@ CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xe0001000
-CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_DEBUG_UART=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_SYS_CUSTOM_LDSCRIPT=y

drivers/clk/clk_versal.c

@@ -571,6 +571,12 @@ static void versal_get_clock_info(void)
 			continue;
 
 		clock[i].valid = attr & CLK_VALID_MASK;
+
+		/* skip query for Invalid clock */
+		ret = versal_is_valid_clock(i);
+		if (ret != CLK_VALID_MASK)
+			continue;
+
 		clock[i].type = ((attr >> CLK_TYPE_SHIFT) & 0x1) ?
 				CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT;
 		nodetype = (attr >> NODE_TYPE_SHIFT) & NODE_CLASS_MASK;

drivers/mtd/nand/raw/arasan_nfc.c

@@ -1120,12 +1120,15 @@ static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
 static void arasan_check_ondie(struct mtd_info *mtd)
 {
 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
-	struct nand_config *nand = nand_get_controller_data(nand_chip);
+	struct nand_drv *info = nand_get_controller_data(nand_chip);
+	struct nand_config *nand = &info->config;
 	u8 maf_id, dev_id;
 	u8 get_feature[4];
 	u8 set_feature[4] = {ENABLE_ONDIE_ECC, 0x00, 0x00, 0x00};
 	u32 i;
 
+	nand_chip->select_chip(mtd, 0);
+
 	/* Send the command for reading device ID */
 	nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
 	nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0, -1);
@@ -1150,10 +1153,12 @@ static void arasan_check_ondie(struct mtd_info *mtd)
 		for (i = 0; i < 4; i++)
 			get_feature[i] = nand_chip->read_byte(mtd);
 
-		if (get_feature[0] & ENABLE_ONDIE_ECC)
+		if (get_feature[0] & ENABLE_ONDIE_ECC) {
 			nand->on_die_ecc_enabled = true;
-		else
+			printf("On-DIE ECC Enabled\n");
+		} else {
 			printf("%s: Unable to enable OnDie ECC\n", __func__);
+		}
 
 		/* Use the BBT pattern descriptors */
 		nand_chip->bbt_td = &bbt_main_descr;

drivers/net/phy/dp83867.c

@@ -65,6 +65,7 @@
 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT		14
 #define DP83867_PHYCR_FIFO_DEPTH_MASK		GENMASK(15, 14)
 #define DP83867_PHYCR_RESERVED_MASK	BIT(11)
+#define DP83867_PHYCR_FORCE_LINK_GOOD	BIT(10)
 #define DP83867_MDI_CROSSOVER		5
 #define DP83867_MDI_CROSSOVER_MDIX	2
 #define DP83867_PHYCTRL_SGMIIEN			0x0800
@@ -284,6 +285,9 @@ static int dp83867_config(struct phy_device *phydev)
 		val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
 		val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
 
+		/* Do not force link good */
+		val &= ~DP83867_PHYCR_FORCE_LINK_GOOD;
+
 		/* The code below checks if "port mirroring" N/A MODE4 has been
 		 * enabled during power on bootstrap.
 		 *

drivers/net/zynq_gem.c

@@ -655,14 +655,16 @@ static int zynq_gem_probe(struct udevice *dev)
 		return -ENOMEM;
 
 	memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
-	u32 addr = (ulong)priv->rxbuffers;
+	ulong addr = (ulong)priv->rxbuffers;
 	flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
 	barrier();
 
 	/* Align bd_space to MMU_SECTION_SHIFT */
 	bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
-	if (!bd_space)
+	if (!bd_space) {
-		return -ENOMEM;
+		ret = -ENOMEM;
+		goto err1;
+	}
 
 	mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
 					BD_SPACE, DCACHE_OFF);
@@ -674,7 +676,7 @@ static int zynq_gem_probe(struct udevice *dev)
 	ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
 	if (ret < 0) {
 		dev_err(dev, "failed to get clock\n");
-		return -EINVAL;
+		goto err1;
 	}
 
 	priv->bus = mdio_alloc();
@@ -684,9 +686,19 @@ static int zynq_gem_probe(struct udevice *dev)
 
 	ret = mdio_register_seq(priv->bus, dev->seq);
 	if (ret)
+		goto err2;
+
+	ret = zynq_phy_init(dev);
+	if (ret)
+		goto err2;
+
 	return ret;
 
-	return zynq_phy_init(dev);
+err2:
+	free(priv->rxbuffers);
+err1:
+	free(priv->tx_bd);
+	return ret;
 }
 
 static int zynq_gem_remove(struct udevice *dev)

include/configs/zynq-common.h

@@ -41,8 +41,6 @@
 # define CONFIG_BOOTP_MAY_FAIL
 #endif
 
-/* QSPI */
-
 /* NOR */
 #ifdef CONFIG_MTD_NOR_FLASH
 # define CONFIG_SYS_FLASH_BASE		0xE2000000