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video: rockchip: dw_mipi_dsi: Fix GRF access

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Use proper register base and access method to access GRF registers.
GRF registers start at a completely different base, and need special
access method, that sets the change mask in the 16 MSBs.

Signed-off-by: Ondrej Jirman <megi@xff.cz>
This commit is contained in:
Ondrej Jirman 2023-05-22 23:47:08 +02:00 committed by Anatolij Gustschin
parent 7c5f278a03
commit bd6375c551
1 changed files with 10 additions and 6 deletions
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16
drivers/video/rockchip/dw_mipi_dsi_rockchip.c
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@ -18,6 +18,7 @@
#include <panel.h> #include <panel.h>
#include <phy-mipi-dphy.h> #include <phy-mipi-dphy.h>
#include <reset.h> #include <reset.h>
#include <syscon.h>
#include <video_bridge.h> #include <video_bridge.h>
#include <dm/device_compat.h> #include <dm/device_compat.h>
#include <dm/lists.h> #include <dm/lists.h>
@ -30,6 +31,9 @@
#include <dm/device-internal.h> #include <dm/device-internal.h>
#include <linux/bitops.h> #include <linux/bitops.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
#define USEC_PER_SEC 1000000L #define USEC_PER_SEC 1000000L
/* /*
@ -197,6 +201,7 @@ struct dw_rockchip_dsi_priv {
struct mipi_dsi_device device; struct mipi_dsi_device device;
void __iomem *base; void __iomem *base;
struct udevice *panel; struct udevice *panel;
void __iomem *grf;
/* Optional external dphy */ /* Optional external dphy */
struct phy phy; struct phy phy;
@ -752,16 +757,13 @@ static int dw_mipi_dsi_rockchip_set_bl(struct udevice *dev, int percent)
static void dw_mipi_dsi_rockchip_config(struct dw_rockchip_dsi_priv *dsi) static void dw_mipi_dsi_rockchip_config(struct dw_rockchip_dsi_priv *dsi)
{ {
if (dsi->cdata->lanecfg1_grf_reg) if (dsi->cdata->lanecfg1_grf_reg)
dsi_write(dsi, dsi->cdata->lanecfg1_grf_reg, rk_setreg(dsi->grf + dsi->cdata->lanecfg1_grf_reg, dsi->cdata->lanecfg1);
dsi->cdata->lanecfg1);
if (dsi->cdata->lanecfg2_grf_reg) if (dsi->cdata->lanecfg2_grf_reg)
dsi_write(dsi, dsi->cdata->lanecfg2_grf_reg, rk_setreg(dsi->grf + dsi->cdata->lanecfg2_grf_reg, dsi->cdata->lanecfg2);
dsi->cdata->lanecfg2);
if (dsi->cdata->enable_grf_reg) if (dsi->cdata->enable_grf_reg)
dsi_write(dsi, dsi->cdata->enable_grf_reg, rk_setreg(dsi->grf + dsi->cdata->enable_grf_reg, dsi->cdata->enable);
dsi->cdata->enable);
} }
static int dw_mipi_dsi_rockchip_bind(struct udevice *dev) static int dw_mipi_dsi_rockchip_bind(struct udevice *dev)
@ -794,6 +796,8 @@ static int dw_mipi_dsi_rockchip_probe(struct udevice *dev)
return -EINVAL; return -EINVAL;
} }
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
i = 0; i = 0;
while (cdata[i].reg) { while (cdata[i].reg) {
if (cdata[i].reg == (fdt_addr_t)priv->base) { if (cdata[i].reg == (fdt_addr_t)priv->base) {