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arch: arm: mach-k3: j784s4_init: Set CTRL_MMR for AUDIO_REFCLK1 clk_sel

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The default value for the mux to select the parent clock,
AUDIO_REFCLK1_CTRL_CLK_SEL is '11111' (31) but the mux input for 31
is marked as 'Reserved' so the ti-sci-clk call for get-parent fails.
Mark it to a valid value, '11100' (28) for MAIN_PLL4_HSDIV2_CLKOUT
to get rid of the linux failures during boot-time like:
"[    1.573193] ti-sci-clk 44083000.system-controller:clock-controller:
 get-parent failed for dev=157, clk=34, ret=-19"

Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
This commit is contained in:
Jayesh Choudhary 2025-01-06 15:34:00 +05:30 committed by Tom Rini
parent b77791a11a
commit bb28b4906e
1 changed files with 5 additions and 0 deletions
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5
arch/arm/mach-k3/j784s4/j784s4_init.c
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@ -23,6 +23,9 @@
#define J784S4_MAX_DDR_CONTROLLERS 4 #define J784S4_MAX_DDR_CONTROLLERS 4
#define CTRL_MMR_CFG0_AUDIO_REFCLK1_CTRL 0x001082e4
#define AUDIO_REFCLK1_DEFAULT 0x1c
/* NAVSS North Bridge (NB) */ /* NAVSS North Bridge (NB) */
#define NAVSS0_NBSS_NB0_CFG_MMRS 0x03702000 #define NAVSS0_NBSS_NB0_CFG_MMRS 0x03702000
#define NAVSS0_NBSS_NB1_CFG_MMRS 0x03703000 #define NAVSS0_NBSS_NB1_CFG_MMRS 0x03703000
@ -201,6 +204,8 @@ void k3_spl_init(void)
remove_fwl_configs(navss_cbass0_fwls, ARRAY_SIZE(navss_cbass0_fwls)); remove_fwl_configs(navss_cbass0_fwls, ARRAY_SIZE(navss_cbass0_fwls));
} }
writel(AUDIO_REFCLK1_DEFAULT, (uintptr_t)CTRL_MMR_CFG0_AUDIO_REFCLK1_CTRL);
/* Output System Firmware version info */ /* Output System Firmware version info */
k3_sysfw_print_ver(); k3_sysfw_print_ver();
} }