mirrors/u-boot
1
0
Fork 0
mirror of https://source.denx.de/u-boot/u-boot.git synced 2026-05-05 20:56:12 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity

board: use lowercase hex prefix style

Browse Source 
Use consistent lowercase hex prefix style in board/*

Does not change auto-generated files in xilinx/zynq/*/ps7_init_gpl.c

Signed-off-by: E Shattow <e@freeshell.de>
This commit is contained in:
E Shattow 2025-06-06 15:44:57 -07:00 committed by Tom Rini
parent 9f208a3e70
commit ba7634c6b6
3 changed files with 17 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
board/freescale/common/qixis.h
View File

@ -136,8 +136,8 @@ void qixis_write_i2c(unsigned int reg, u8 value);
#define QIXIS_SDCLKIN 0x08
#define QIXIS_SDCLKOUT 0x02
#define QIXIS_DAT5_6_7 0X02
#define QIXIS_DAT4 0X01
#define QIXIS_DAT5_6_7 0x02
#define QIXIS_DAT4 0x01
#define QIXIS_EVDD_BY_SDHC_VS 0x0c

28
board/gateworks/gw_ventana/gw_ventana_spl.c
View File

@ -366,34 +366,34 @@ static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0X00480047,
.p0_mpwldectrl1 = 0X003D003F,
.p0_mpwldectrl0 = 0x00480047,
.p0_mpwldectrl1 = 0x003D003F,
/* Read DQS Gating calibration */
.p0_mpdgctrl0 = 0X423E0241,
.p0_mpdgctrl1 = 0X022B022C,
.p0_mpdgctrl0 = 0x423E0241,
.p0_mpdgctrl1 = 0x022B022C,
/* Read Calibration: DQS delay relative to DQ read access */
.p0_mprddlctl = 0X49454A4A,
.p0_mprddlctl = 0x49454A4A,
/* Write Calibration: DQ/DM delay relative to DQS write access */
.p0_mpwrdlctl = 0X2E372C32,
.p0_mpwrdlctl = 0x2E372C32,
};
static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0X00220021,
.p0_mpwldectrl1 = 0X00200030,
.p1_mpwldectrl0 = 0X002D0027,
.p1_mpwldectrl1 = 0X00150026,
.p0_mpwldectrl0 = 0x00220021,
.p0_mpwldectrl1 = 0x00200030,
.p1_mpwldectrl0 = 0x002D0027,
.p1_mpwldectrl1 = 0x00150026,
/* Read DQS Gating calibration */
.p0_mpdgctrl0 = 0x43330342,
.p0_mpdgctrl1 = 0x0339034A,
.p1_mpdgctrl0 = 0x032F0325,
.p1_mpdgctrl1 = 0x032F022E,
/* Read Calibration: DQS delay relative to DQ read access */
.p0_mprddlctl = 0X3A2E3437,
.p1_mprddlctl = 0X35312F3F,
.p0_mprddlctl = 0x3A2E3437,
.p1_mprddlctl = 0x35312F3F,
/* Write Calibration: DQ/DM delay relative to DQS write access */
.p0_mpwrdlctl = 0X33363B37,
.p1_mpwrdlctl = 0X40304239,
.p0_mpwrdlctl = 0x33363B37,
.p1_mpwrdlctl = 0x40304239,
};
static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = {

2
board/kontron/sl-mx6ul/spl.c
View File

@ -204,7 +204,7 @@ static struct mx6_ddr3_cfg mem_512M_ddr = {
static struct mx6_mmdc_calibration mx6_mmcd_512M_calib = {
.p0_mpwldectrl0 = 0x00000000,
.p0_mpdgctrl0 = 0X01440144,
.p0_mpdgctrl0 = 0x01440144,
.p0_mprddlctl = 0x40405454,
.p0_mpwrdlctl = 0x40404E4C,
};