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arm: dts: ls2080a: add label to pcie nodes in dts

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Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Wasim Khan 2020-09-28 16:26:08 +05:30 committed by Priyanka Jain
parent 2adb7970cb
commit ba45dd21f3
1 changed files with 6 additions and 5 deletions
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11
arch/arm/dts/fsl-ls2080a.dtsi
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@ -1,7 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11 // SPDX-License-Identifier: GPL-2.0+ OR X11
/* /*
* Freescale ls2080a SOC common device tree source * NXP ls2080a SOC common device tree source
* *
* Copyright 2020 NXP
* Copyright 2013-2015 Freescale Semiconductor, Inc. * Copyright 2013-2015 Freescale Semiconductor, Inc.
*/ */
@ -133,7 +134,7 @@
dr_mode = "host"; dr_mode = "host";
}; };
pcie@3400000 { pcie1: pcie@3400000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie"; compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
0x00 0x03480000 0x0 0x80000 /* lut registers */ 0x00 0x03480000 0x0 0x80000 /* lut registers */
@ -148,7 +149,7 @@
0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
}; };
pcie@3500000 { pcie2: pcie@3500000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie"; compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
0x00 0x03580000 0x0 0x80000 /* lut registers */ 0x00 0x03580000 0x0 0x80000 /* lut registers */
@ -163,7 +164,7 @@
0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
}; };
pcie@3600000 { pcie3: pcie@3600000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie"; compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
0x00 0x03680000 0x0 0x80000 /* lut registers */ 0x00 0x03680000 0x0 0x80000 /* lut registers */
@ -178,7 +179,7 @@
0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
}; };
pcie@3700000 { pcie4: pcie@3700000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie"; compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */ reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */
0x00 0x03780000 0x0 0x80000 /* lut registers */ 0x00 0x03780000 0x0 0x80000 /* lut registers */