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spi: airoha: add support of dual/quad wires spi modes to exec_op() handler
Booting without this patch and disabled dirmap support results in [ 2.980719] spi-nand spi0.0: Micron SPI NAND was found. [ 2.986040] spi-nand spi0.0: 256 MiB, block size: 128 KiB, page size: 2048, OOB size: 128 [ 2.994709] 2 fixed-partitions partitions found on MTD device spi0.0 [ 3.001075] Creating 2 MTD partitions on "spi0.0": [ 3.005862] 0x000000000000-0x000000020000 : "bl2" [ 3.011272] 0x000000020000-0x000010000000 : "ubi" ... [ 6.195594] ubi0: attaching mtd1 [ 13.338398] ubi0: scanning is finished [ 13.342188] ubi0 error: ubi_read_volume_table: the layout volume was not found [ 13.349784] ubi0 error: ubi_attach_mtd_dev: failed to attach mtd1, error -22 [ 13.356897] UBI error: cannot attach mtd1 If dirmap is disabled or not supported in the spi driver, the dirmap requests will be executed via exec_op() handler. Thus, if the hardware supports dual/quad spi modes, then corresponding requests will be sent to exec_op() handler. Current driver does not support such requests, so error is arrised. As result the flash can't be read/write. This patch adds support of dual and quad wires spi modes to exec_op() handler. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
This commit is contained in:
Mikhail Kshevetskiy
Michael Trimarchi
parent
ba54a70f5c
commit
ba04299ff7
@ -186,6 +186,14 @@
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#define SPI_NAND_OP_RESET 0xff
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#define SPI_NAND_OP_DIE_SELECT 0xc2
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/* SNAND FIFO commands */
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#define SNAND_FIFO_TX_BUSWIDTH_SINGLE 0x08
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#define SNAND_FIFO_TX_BUSWIDTH_DUAL 0x09
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#define SNAND_FIFO_TX_BUSWIDTH_QUAD 0x0a
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#define SNAND_FIFO_RX_BUSWIDTH_SINGLE 0x0c
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#define SNAND_FIFO_RX_BUSWIDTH_DUAL 0x0e
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#define SNAND_FIFO_RX_BUSWIDTH_QUAD 0x0f
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#define SPI_NAND_CACHE_SIZE (SZ_4K + SZ_256)
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#define SPI_MAX_TRANSFER_SIZE 511
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@ -380,10 +388,26 @@ static int airoha_snand_set_mode(struct airoha_snand_priv *priv,
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return regmap_write(priv->regmap_ctrl, REG_SPI_CTRL_DUMMY, 0);
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}
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static int airoha_snand_write_data(struct airoha_snand_priv *priv, u8 cmd,
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const u8 *data, int len)
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static int airoha_snand_write_data(struct airoha_snand_priv *priv,
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const u8 *data, int len, int buswidth)
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{
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int i, data_len;
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u8 cmd;
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switch (buswidth) {
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case 0:
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case 1:
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cmd = SNAND_FIFO_TX_BUSWIDTH_SINGLE;
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break;
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case 2:
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cmd = SNAND_FIFO_TX_BUSWIDTH_DUAL;
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break;
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case 4:
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cmd = SNAND_FIFO_TX_BUSWIDTH_QUAD;
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break;
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default:
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return -EINVAL;
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}
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for (i = 0; i < len; i += data_len) {
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int err;
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@ -402,16 +426,32 @@ static int airoha_snand_write_data(struct airoha_snand_priv *priv, u8 cmd,
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return 0;
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}
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static int airoha_snand_read_data(struct airoha_snand_priv *priv, u8 *data,
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int len)
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static int airoha_snand_read_data(struct airoha_snand_priv *priv,
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u8 *data, int len, int buswidth)
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{
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int i, data_len;
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u8 cmd;
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switch (buswidth) {
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case 0:
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case 1:
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cmd = SNAND_FIFO_RX_BUSWIDTH_SINGLE;
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break;
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case 2:
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cmd = SNAND_FIFO_RX_BUSWIDTH_DUAL;
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break;
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case 4:
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cmd = SNAND_FIFO_RX_BUSWIDTH_QUAD;
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break;
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default:
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return -EINVAL;
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}
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for (i = 0; i < len; i += data_len) {
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int err;
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data_len = min(len - i, SPI_MAX_TRANSFER_SIZE);
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err = airoha_snand_set_fifo_op(priv, 0xc, data_len);
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err = airoha_snand_set_fifo_op(priv, cmd, data_len);
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if (err)
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return err;
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@ -525,6 +565,38 @@ static int airoha_snand_nfi_config(struct airoha_snand_priv *priv)
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SPI_NFI_CUS_SEC_SIZE, val);
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}
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static bool airoha_snand_is_page_ops(const struct spi_mem_op *op)
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{
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if (op->addr.nbytes != 2)
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return false;
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if (op->addr.buswidth != 1 && op->addr.buswidth != 2 &&
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op->addr.buswidth != 4)
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return false;
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switch (op->data.dir) {
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case SPI_MEM_DATA_IN:
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if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth > 0xf)
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return false;
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/* quad in / quad out */
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if (op->addr.buswidth == 4)
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return op->data.buswidth == 4;
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if (op->addr.buswidth == 2)
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return op->data.buswidth == 2;
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/* standard spi */
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return op->data.buswidth == 4 || op->data.buswidth == 2 ||
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op->data.buswidth == 1;
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case SPI_MEM_DATA_OUT:
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return !op->dummy.nbytes && op->addr.buswidth == 1 &&
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(op->data.buswidth == 4 || op->data.buswidth == 1);
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default:
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return false;
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}
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}
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static bool airoha_snand_supports_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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@ -534,6 +606,9 @@ static bool airoha_snand_supports_op(struct spi_slave *slave,
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if (op->cmd.buswidth != 1)
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return false;
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if (airoha_snand_is_page_ops(op))
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return true;
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return (!op->addr.nbytes || op->addr.buswidth == 1) &&
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(!op->dummy.nbytes || op->dummy.buswidth == 1) &&
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(!op->data.nbytes || op->data.buswidth == 1);
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@ -542,13 +617,29 @@ static bool airoha_snand_supports_op(struct spi_slave *slave,
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static int airoha_snand_exec_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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u8 data[8], cmd, opcode = op->cmd.opcode;
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struct udevice *bus = slave->dev->parent;
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struct airoha_snand_priv *priv;
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int op_len, addr_len, dummy_len;
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u8 buf[20], *data;
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int i, err;
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priv = dev_get_priv(bus);
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op_len = op->cmd.nbytes;
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addr_len = op->addr.nbytes;
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dummy_len = op->dummy.nbytes;
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if (op_len + dummy_len + addr_len > sizeof(buf))
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return -EIO;
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data = buf;
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for (i = 0; i < op_len; i++)
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*data++ = op->cmd.opcode >> (8 * (op_len - i - 1));
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for (i = 0; i < addr_len; i++)
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*data++ = op->addr.val >> (8 * (addr_len - i - 1));
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for (i = 0; i < dummy_len; i++)
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*data++ = 0xff;
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/* switch to manual mode */
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err = airoha_snand_set_mode(priv, SPI_MODE_MANUAL);
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if (err < 0)
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@ -559,40 +650,40 @@ static int airoha_snand_exec_op(struct spi_slave *slave,
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return err;
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/* opcode */
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err = airoha_snand_write_data(priv, 0x8, &opcode, sizeof(opcode));
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data = buf;
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err = airoha_snand_write_data(priv, data, op_len,
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op->cmd.buswidth);
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if (err)
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return err;
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/* addr part */
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cmd = opcode == SPI_NAND_OP_GET_FEATURE ? 0x11 : 0x8;
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put_unaligned_be64(op->addr.val, data);
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for (i = ARRAY_SIZE(data) - op->addr.nbytes;
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i < ARRAY_SIZE(data); i++) {
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err = airoha_snand_write_data(priv, cmd, &data[i],
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sizeof(data[0]));
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data += op_len;
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if (addr_len) {
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err = airoha_snand_write_data(priv, data, addr_len,
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op->addr.buswidth);
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if (err)
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return err;
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}
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/* dummy */
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data[0] = 0xff;
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for (i = 0; i < op->dummy.nbytes; i++) {
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err = airoha_snand_write_data(priv, 0x8, &data[0],
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sizeof(data[0]));
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data += addr_len;
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if (dummy_len) {
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err = airoha_snand_write_data(priv, data, dummy_len,
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op->dummy.buswidth);
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if (err)
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return err;
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}
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/* data */
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if (op->data.dir == SPI_MEM_DATA_IN) {
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err = airoha_snand_read_data(priv, op->data.buf.in,
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op->data.nbytes);
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if (err)
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return err;
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} else {
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err = airoha_snand_write_data(priv, 0x8, op->data.buf.out,
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op->data.nbytes);
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if (op->data.nbytes) {
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if (op->data.dir == SPI_MEM_DATA_IN)
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err = airoha_snand_read_data(priv, op->data.buf.in,
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op->data.nbytes,
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op->data.buswidth);
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else
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err = airoha_snand_write_data(priv, op->data.buf.out,
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op->data.nbytes,
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op->data.buswidth);
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if (err)
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return err;
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}
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