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imx8mp: icore-edimm2.2: Convert to DM_PMIC
Convert the board to use DM_PMIC instead of the legacy SPL I2C/PMIC handling. Changes include: - Enable DM_PMIC, DM_PMIC_PCA9450, and SPL_DM_PMIC_PCA9450 in defconfig. - Drop legacy SPL I2C and PMIC options. - Remove manual I2C1 pad setup and legacy power_pca9450_init() usage. - Use DM-based pmic_get() with the DT node "pmic@25". - Update PMIC register programming to use struct udevice API. Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan
Fabio Estevam
parent
c93520a4ba
commit
b94d20f66e
@ -22,6 +22,18 @@
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bootph-pre-ram;
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};
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&pca9450 {
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bootph-all;
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};
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&pinctrl_i2c1 {
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bootph-all;
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};
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&pinctrl_pmic {
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bootph-all;
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};
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&pinctrl_uart2 {
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bootph-pre-ram;
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};
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@ -63,7 +75,7 @@
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};
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&i2c1 {
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bootph-pre-ram;
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bootph-all;
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};
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&i2c2 {
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@ -118,3 +130,7 @@
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phy-reset-duration = <15>;
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phy-reset-post-delay = <100>;
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
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bootph-all;
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};
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@ -16,9 +16,6 @@
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#include <asm/arch/imx8mp_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/arch/ddr.h>
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#include <power/pmic.h>
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#include <power/pca9450.h>
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@ -33,36 +30,22 @@ void spl_dram_init(void)
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ddr_init(&dram_timing);
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}
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#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
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.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
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.gp = IMX_GPIO_NR(5, 14),
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},
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.sda = {
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.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
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.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
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.gp = IMX_GPIO_NR(5, 15),
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},
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};
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#if CONFIG_IS_ENABLED(POWER_LEGACY)
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#define I2C_PMIC 0
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#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
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int power_init_board(void)
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{
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struct pmic *p;
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struct udevice *dev;
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int ret;
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ret = power_pca9450_init(I2C_PMIC, 0x25);
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if (ret)
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printf("power init failed");
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p = pmic_get("PCA9450");
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pmic_probe(p);
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ret = pmic_get("pmic@25", &dev);
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if (ret == -ENODEV) {
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puts("No pmic@25\n");
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return 0;
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}
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if (ret < 0)
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return ret;
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/* BUCKxOUT_DVS0/1 control BUCK123 output */
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pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
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pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
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#ifdef CONFIG_IMX8M_LPDDR4
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/*
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@ -73,22 +56,22 @@ int power_init_board(void)
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*/
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#ifdef CONFIG_IMX8M_VDD_SOC_850MV
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/* set DVS0 to 0.85v for special case*/
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pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
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#else
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pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
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#endif
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pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
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pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
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pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
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/* Kernel uses OD/OD freq for SOC */
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/* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
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pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
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pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
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#elif defined(CONFIG_IMX8M_DDR4)
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/* DDR4 runs at 3200MTS, uses default ND 0.85v for VDD_SOC and VDD_ARM */
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pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
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pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
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/* Set NVCC_DRAM to 1.2v for DDR4 */
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pmic_reg_write(p, PCA9450_BUCK6OUT, 0x18);
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pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x18);
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#endif
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return 0;
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@ -136,8 +119,6 @@ void board_init_f(ulong dummy)
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enable_tzc380();
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setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
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power_init_board();
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/* DDR initialization */
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@ -7,9 +7,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_ENV_SIZE=0x1000
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CONFIG_ENV_OFFSET=0x400000
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CONFIG_SYS_I2C_MXC_I2C1=y
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CONFIG_SYS_I2C_MXC_I2C2=y
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CONFIG_SYS_I2C_MXC_I2C3=y
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CONFIG_DM_GPIO=y
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CONFIG_DEFAULT_DEVICE_TREE="imx8mp-icore-mx8mp-edimm2.2"
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CONFIG_TARGET_IMX8MP_ICORE_MX8MP=y
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@ -78,8 +75,6 @@ CONFIG_CLK_IMX8MP=y
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CONFIG_MXC_GPIO=y
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CONFIG_DM_PCA953X=y
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CONFIG_DM_I2C=y
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# CONFIG_SPL_DM_I2C is not set
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CONFIG_SPL_SYS_I2C_LEGACY=y
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CONFIG_LED=y
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CONFIG_LED_GPIO=y
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CONFIG_SUPPORT_EMMC_BOOT=y
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@ -98,12 +93,13 @@ CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_PINCTRL_IMX8M=y
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CONFIG_SPL_POWER_LEGACY=y
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CONFIG_POWER_PCA9450=y
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CONFIG_DM_PMIC=y
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CONFIG_DM_PMIC_PCA9450=y
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CONFIG_SPL_DM_PMIC_PCA9450=y
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CONFIG_DM_REGULATOR=y
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CONFIG_DM_REGULATOR_PCA9450=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_GPIO=y
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CONFIG_SPL_POWER_I2C=y
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CONFIG_DM_SERIAL=y
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CONFIG_MXC_UART=y
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CONFIG_SYSRESET=y
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