From c3d31af6d6c2cd63d4de173a00a72c7f009e6443 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Wed, 19 Feb 2020 09:45:37 +0800 Subject: [PATCH 001/237] rockchip: video: Use ofnode_decode_display_timing() to parse timing Use ofnode_decode_display_timing() instead of fdtdec_decode_display_timing() to parse display timing, so that we can support live DT. Signed-off-by: Kever Yang Reviewed-by: Simon Glass --- drivers/video/rockchip/rk_lvds.c | 3 +-- drivers/video/rockchip/rk_mipi.c | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/video/rockchip/rk_lvds.c b/drivers/video/rockchip/rk_lvds.c index 79e24baf53b..404af7eb6e8 100644 --- a/drivers/video/rockchip/rk_lvds.c +++ b/drivers/video/rockchip/rk_lvds.c @@ -161,8 +161,7 @@ int rk_lvds_enable(struct udevice *dev, int panel_bpp, int rk_lvds_read_timing(struct udevice *dev, struct display_timing *timing) { - if (fdtdec_decode_display_timing - (gd->fdt_blob, dev_of_offset(dev), 0, timing)) { + if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) { debug("%s: Failed to decode display timing\n", __func__); return -EINVAL; } diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index f9280e86070..a77bdfd24dd 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -29,8 +29,7 @@ int rk_mipi_read_timing(struct udevice *dev, { int ret; - ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev), - 0, timing); + ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, timing); if (ret) { debug("%s: Failed to decode display timing (ret=%d)\n", __func__, ret); From 653ac184ee8c785564d70ee9ccceffbd9a48b737 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Wed, 19 Feb 2020 09:45:38 +0800 Subject: [PATCH 002/237] rockchip: video: Convert to use APIs which support live DT Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Kever Yang Reviewed-by: Simon Glass --- drivers/video/rockchip/rk3288_mipi.c | 1 - drivers/video/rockchip/rk3399_mipi.c | 1 - drivers/video/rockchip/rk_edp.c | 2 +- drivers/video/rockchip/rk_lvds.c | 10 ++++------ drivers/video/rockchip/rk_mipi.c | 11 +++++------ 5 files changed, 10 insertions(+), 15 deletions(-) diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c index f4444b9c348..71d3faf169d 100644 --- a/drivers/video/rockchip/rk3288_mipi.c +++ b/drivers/video/rockchip/rk3288_mipi.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include "rk_mipi.h" diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c index 74ebe770a95..cfaa37797ed 100644 --- a/drivers/video/rockchip/rk3399_mipi.c +++ b/drivers/video/rockchip/rk3399_mipi.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include "rk_mipi.h" diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c index cf84b886e72..99b16cd95ed 100644 --- a/drivers/video/rockchip/rk_edp.c +++ b/drivers/video/rockchip/rk_edp.c @@ -997,7 +997,7 @@ static int rk_edp_ofdata_to_platdata(struct udevice *dev) { struct rk_edp_priv *priv = dev_get_priv(dev); - priv->regs = (struct rk3288_edp *)devfdt_get_addr(dev); + priv->regs = dev_read_addr_ptr(dev); priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); return 0; diff --git a/drivers/video/rockchip/rk_lvds.c b/drivers/video/rockchip/rk_lvds.c index 404af7eb6e8..c92c2e3c6c0 100644 --- a/drivers/video/rockchip/rk_lvds.c +++ b/drivers/video/rockchip/rk_lvds.c @@ -172,13 +172,11 @@ int rk_lvds_read_timing(struct udevice *dev, struct display_timing *timing) static int rk_lvds_ofdata_to_platdata(struct udevice *dev) { struct rk_lvds_priv *priv = dev_get_priv(dev); - const void *blob = gd->fdt_blob; - int node = dev_of_offset(dev); int ret; - priv->regs = (void *)devfdt_get_addr(dev); + priv->regs = dev_read_addr_ptr(dev); priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - ret = fdtdec_get_int(blob, node, "rockchip,output", -1); + ret = dev_read_s32_default(dev, "rockchip,output", -1); if (ret != -1) { priv->output = ret; debug("LVDS output : %d\n", ret); @@ -187,7 +185,7 @@ static int rk_lvds_ofdata_to_platdata(struct udevice *dev) priv->output = LVDS_OUTPUT_RGB; } - ret = fdtdec_get_int(blob, node, "rockchip,data-mapping", -1); + ret = dev_read_s32_default(dev, "rockchip,data-mapping", -1); if (ret != -1) { priv->format = ret; debug("LVDS data-mapping : %d\n", ret); @@ -196,7 +194,7 @@ static int rk_lvds_ofdata_to_platdata(struct udevice *dev) priv->format = LVDS_FORMAT_JEIDA; } - ret = fdtdec_get_int(blob, node, "rockchip,data-width", -1); + ret = dev_read_s32_default(dev, "rockchip,data-width", -1); if (ret != -1) { debug("LVDS data-width : %d\n", ret); if (ret == 24) { diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index a77bdfd24dd..f1c21bb8d7e 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include "rk_mipi.h" @@ -76,7 +75,7 @@ static void rk_mipi_dsi_write(uintptr_t regs, u32 reg, u32 val) int rk_mipi_dsi_enable(struct udevice *dev, const struct display_timing *timing) { - int node, timing_node; + ofnode node, timing_node; int val; struct rk_mipi_priv *priv = dev_get_priv(dev); uintptr_t regs = priv->regs; @@ -119,10 +118,10 @@ int rk_mipi_dsi_enable(struct udevice *dev, rk_mipi_dsi_write(regs, VID_PKT_SIZE, 0x4b0); /* Set dpi color coding depth 24 bit */ - timing_node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev), - "display-timings"); - node = fdt_first_subnode(gd->fdt_blob, timing_node); - val = fdtdec_get_int(gd->fdt_blob, node, "bits-per-pixel", -1); + timing_node = ofnode_find_subnode(dev->node, "display-timings"); + node = ofnode_first_subnode(timing_node); + + val = ofnode_read_u32_default(node, "bits-per-pixel", -1); switch (val) { case 16: rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_16BIT_CFG_1); From f9e2d9e8899f9edcdf1285073c0e2ca496ae4452 Mon Sep 17 00:00:00 2001 From: Suniel Mahesh Date: Wed, 25 Mar 2020 21:07:36 +0530 Subject: [PATCH 003/237] arm: dts: rockchip: rk3399-roc-pc: Enable FE1.1 USB 2.0 HUB on roc-rk3399-pc roc-rk3399-pc has an FE1.1 USB 2.0 HUB which connects two USB ports (HOST1 and HOST2). For end devices to work we need to enable USB hub so that HOST detects there presence and enumerates them accordingly. This requires explicit pinctrl within gpio enablement. Signed-off-by: Suniel Mahesh Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi index 57464429811..598e0e227cb 100644 --- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi +++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi @@ -14,6 +14,16 @@ chosen { u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; }; + + vcc_hub_en: vcc_hub_en-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_rst>; + regulator-name = "vcc_hub_en"; + regulator-always-on; + }; }; &vdd_log { From 1e1cb9539fc3925796cd2672646a1d1b90186568 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 31 Mar 2020 15:32:46 +0800 Subject: [PATCH 004/237] rockchip: px30: add -u-boot dtsi for soc Add soc level -u-boot.dtst so that boards can share the common nodes. Signed-off-by: Kever Yang --- arch/arm/dts/px30-evb-u-boot.dtsi | 82 +------------------------- arch/arm/dts/px30-firefly-u-boot.dtsi | 82 +------------------------- arch/arm/dts/px30-u-boot.dtsi | 84 +++++++++++++++++++++++++++ 3 files changed, 88 insertions(+), 160 deletions(-) create mode 100644 arch/arm/dts/px30-u-boot.dtsi diff --git a/arch/arm/dts/px30-evb-u-boot.dtsi b/arch/arm/dts/px30-evb-u-boot.dtsi index a2a2c07dcc1..aea9f4d6e51 100644 --- a/arch/arm/dts/px30-evb-u-boot.dtsi +++ b/arch/arm/dts/px30-evb-u-boot.dtsi @@ -1,84 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * (C) Copyright 2020 Rockchip Electronics Co., Ltd */ -/ { - aliases { - mmc0 = &emmc; - mmc1 = &sdmmc; - }; - - chosen { - u-boot,spl-boot-order = &emmc, &sdmmc; - }; -}; - -&dmc { - u-boot,dm-pre-reloc; -}; - -&uart2 { - clock-frequency = <24000000>; - u-boot,dm-pre-reloc; -}; - -&uart5 { - clock-frequency = <24000000>; - u-boot,dm-pre-reloc; -}; - -&sdmmc { - u-boot,dm-pre-reloc; - - /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */ - u-boot,spl-fifo-mode; -}; - -&emmc { - u-boot,dm-pre-reloc; - - /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */ - u-boot,spl-fifo-mode; -}; - -&grf { - u-boot,dm-pre-reloc; -}; - -&pmugrf { - u-boot,dm-pre-reloc; -}; - -&xin24m { - u-boot,dm-pre-reloc; -}; - -&cru { - u-boot,dm-pre-reloc; -}; - -&pmucru { - u-boot,dm-pre-reloc; -}; - -&saradc { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&gpio0 { - u-boot,dm-pre-reloc; -}; - -&gpio1 { - u-boot,dm-pre-reloc; -}; - -&gpio2 { - u-boot,dm-pre-reloc; -}; - -&gpio3 { - u-boot,dm-pre-reloc; -}; +#include "px30-u-boot.dtsi" diff --git a/arch/arm/dts/px30-firefly-u-boot.dtsi b/arch/arm/dts/px30-firefly-u-boot.dtsi index bb782b4e2df..aea9f4d6e51 100644 --- a/arch/arm/dts/px30-firefly-u-boot.dtsi +++ b/arch/arm/dts/px30-firefly-u-boot.dtsi @@ -1,84 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd + * (C) Copyright 2020 Rockchip Electronics Co., Ltd */ -/ { - aliases { - mmc0 = &emmc; - mmc1 = &sdmmc; - }; - - chosen { - u-boot,spl-boot-order = &emmc, &sdmmc; - }; -}; - -&dmc { - u-boot,dm-pre-reloc; -}; - -&uart2 { - clock-frequency = <24000000>; - u-boot,dm-pre-reloc; -}; - -&uart5 { - clock-frequency = <24000000>; - u-boot,dm-pre-reloc; -}; - -&sdmmc { - u-boot,dm-pre-reloc; - - /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ - u-boot,spl-fifo-mode; -}; - -&emmc { - u-boot,dm-pre-reloc; - - /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ - u-boot,spl-fifo-mode; -}; - -&grf { - u-boot,dm-pre-reloc; -}; - -&pmugrf { - u-boot,dm-pre-reloc; -}; - -&xin24m { - u-boot,dm-pre-reloc; -}; - -&cru { - u-boot,dm-pre-reloc; -}; - -&pmucru { - u-boot,dm-pre-reloc; -}; - -&saradc { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&gpio0 { - u-boot,dm-pre-reloc; -}; - -&gpio1 { - u-boot,dm-pre-reloc; -}; - -&gpio2 { - u-boot,dm-pre-reloc; -}; - -&gpio3 { - u-boot,dm-pre-reloc; -}; +#include "px30-u-boot.dtsi" diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi new file mode 100644 index 00000000000..bb782b4e2df --- /dev/null +++ b/arch/arm/dts/px30-u-boot.dtsi @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +/ { + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + chosen { + u-boot,spl-boot-order = &emmc, &sdmmc; + }; +}; + +&dmc { + u-boot,dm-pre-reloc; +}; + +&uart2 { + clock-frequency = <24000000>; + u-boot,dm-pre-reloc; +}; + +&uart5 { + clock-frequency = <24000000>; + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; + + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ + u-boot,spl-fifo-mode; +}; + +&emmc { + u-boot,dm-pre-reloc; + + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ + u-boot,spl-fifo-mode; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&pmugrf { + u-boot,dm-pre-reloc; +}; + +&xin24m { + u-boot,dm-pre-reloc; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&pmucru { + u-boot,dm-pre-reloc; +}; + +&saradc { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&gpio0 { + u-boot,dm-pre-reloc; +}; + +&gpio1 { + u-boot,dm-pre-reloc; +}; + +&gpio2 { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; From 2bffb728834d5293c456fe23ff0248180b96be38 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 31 Mar 2020 15:33:46 +0800 Subject: [PATCH 005/237] rockchip: px30-evb: remove redundant include file The file -u-boot.dtsi inculde automatically by the build system, no need to add this to dts file. Signed-off-by: Kever Yang --- arch/arm/dts/px30-evb.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/px30-evb.dts b/arch/arm/dts/px30-evb.dts index d886f17242f..4134e2ee13d 100644 --- a/arch/arm/dts/px30-evb.dts +++ b/arch/arm/dts/px30-evb.dts @@ -8,7 +8,6 @@ #include #include #include "px30.dtsi" -#include "px30-evb-u-boot.dtsi" / { model = "Rockchip PX30 EVB"; From 91afd36f3802aee001a2f551ea1d77aca428b0a9 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Thu, 20 Feb 2020 22:57:52 +0530 Subject: [PATCH 006/237] spi: Transform the FSL QuadSPI driver to use the SPI MEM API To support the SPI MEM API, instead of modifying the existing U-Boot driver, this patch adds a port of the existing Linux driver. This also has the advantage that porting changes and fixes from Linux will be easier. Porting of driver left most of the functions unchanged while few of the changes are: -Remove lock(mutexes) and irq handler as u-boot is a single core execution. -Remove invalid masterid as it was required specially for multicore execution in LS2088ARDB which is not the case in u-boot. -Remove clock support as changing spi speed is not supported in uboot and nor in linux. Currently tested on LS1088ARDB, LS1012ARDB, LS1046ARDB, LS1046AFRWY, LS1043AQDS, LS1021ATWR, LS2088ARDB, I.MX6ULL EVK. Signed-off-by: Frieder Schrempf Signed-off-by: Ashish Kumar Signed-off-by: Kuldeep Singh Reviewed-by: Stefan Roese Tested-by: Stefan Roese Acked-by: Vignesh Raghavendra Acked-by: Jagan Teki --- drivers/spi/fsl_qspi.c | 1603 ++++++++++++++++------------------------ drivers/spi/fsl_qspi.h | 145 ---- 2 files changed, 621 insertions(+), 1127 deletions(-) delete mode 100644 drivers/spi/fsl_qspi.h diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 8e2a09df366..ee2c8b67dc9 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -1,413 +1,458 @@ // SPDX-License-Identifier: GPL-2.0+ + /* - * Copyright 2013-2015 Freescale Semiconductor, Inc. + * Freescale QuadSPI driver. * - * Freescale Quad Serial Peripheral Interface (QSPI) driver + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * Copyright (C) 2018 Bootlin + * Copyright (C) 2018 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + * Copyright 2019-2020 NXP + * + * This driver is a ported version of Linux Freescale QSPI driver taken from + * v5.5-rc1 tag having following information. + * + * Transition to SPI MEM interface: + * Authors: + * Boris Brezillon + * Frieder Schrempf + * Yogesh Gaur + * Suresh Gupta + * + * Based on the original fsl-quadspi.c spi-nor driver. + * Transition to spi-mem in spi-fsl-qspi.c */ #include -#include -#include #include -#include -#include #include -#include -#include -#include -#include "fsl_qspi.h" +#include +#include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; -#define OFFSET_BITS_MASK GENMASK(23, 0) +/* + * The driver only uses one single LUT entry, that is updated on + * each call of exec_op(). Index 0 is preset at boot with a basic + * read operation, so let's use the last entry (15). + */ +#define SEQID_LUT 15 -#define FLASH_STATUS_WEL 0x02 +/* Registers used by the driver */ +#define QUADSPI_MCR 0x00 +#define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16) +#define QUADSPI_MCR_MDIS_MASK BIT(14) +#define QUADSPI_MCR_CLR_TXF_MASK BIT(11) +#define QUADSPI_MCR_CLR_RXF_MASK BIT(10) +#define QUADSPI_MCR_DDR_EN_MASK BIT(7) +#define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2) +#define QUADSPI_MCR_SWRSTHD_MASK BIT(1) +#define QUADSPI_MCR_SWRSTSD_MASK BIT(0) -/* SEQID */ -#define SEQID_WREN 1 -#define SEQID_FAST_READ 2 -#define SEQID_RDSR 3 -#define SEQID_SE 4 -#define SEQID_CHIP_ERASE 5 -#define SEQID_PP 6 -#define SEQID_RDID 7 -#define SEQID_BE_4K 8 -#ifdef CONFIG_SPI_FLASH_BAR -#define SEQID_BRRD 9 -#define SEQID_BRWR 10 -#define SEQID_RDEAR 11 -#define SEQID_WREAR 12 -#endif -#define SEQID_WRAR 13 -#define SEQID_RDAR 14 +#define QUADSPI_IPCR 0x08 +#define QUADSPI_IPCR_SEQID(x) ((x) << 24) +#define QUADSPI_FLSHCR 0x0c +#define QUADSPI_FLSHCR_TCSS_MASK GENMASK(3, 0) +#define QUADSPI_FLSHCR_TCSH_MASK GENMASK(11, 8) +#define QUADSPI_FLSHCR_TDH_MASK GENMASK(17, 16) -/* QSPI CMD */ -#define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */ -#define QSPI_CMD_RDSR 0x05 /* Read status register */ -#define QSPI_CMD_WREN 0x06 /* Write enable */ -#define QSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */ -#define QSPI_CMD_BE_4K 0x20 /* 4K erase */ -#define QSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */ -#define QSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */ -#define QSPI_CMD_RDID 0x9f /* Read JEDEC ID */ +#define QUADSPI_BUF3CR 0x1c +#define QUADSPI_BUF3CR_ALLMST_MASK BIT(31) +#define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8) +#define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8) -/* Used for Micron, winbond and Macronix flashes */ -#define QSPI_CMD_WREAR 0xc5 /* EAR register write */ -#define QSPI_CMD_RDEAR 0xc8 /* EAR reigster read */ +#define QUADSPI_BFGENCR 0x20 +#define QUADSPI_BFGENCR_SEQID(x) ((x) << 12) -/* Used for Spansion flashes only. */ -#define QSPI_CMD_BRRD 0x16 /* Bank register read */ -#define QSPI_CMD_BRWR 0x17 /* Bank register write */ +#define QUADSPI_BUF0IND 0x30 +#define QUADSPI_BUF1IND 0x34 +#define QUADSPI_BUF2IND 0x38 +#define QUADSPI_SFAR 0x100 -/* Used for Spansion S25FS-S family flash only. */ -#define QSPI_CMD_RDAR 0x65 /* Read any device register */ -#define QSPI_CMD_WRAR 0x71 /* Write any device register */ +#define QUADSPI_SMPR 0x108 +#define QUADSPI_SMPR_DDRSMP_MASK GENMASK(18, 16) +#define QUADSPI_SMPR_FSDLY_MASK BIT(6) +#define QUADSPI_SMPR_FSPHS_MASK BIT(5) +#define QUADSPI_SMPR_HSENA_MASK BIT(0) -/* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */ -#define QSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ -#define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */ -#define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */ +#define QUADSPI_RBCT 0x110 +#define QUADSPI_RBCT_WMRK_MASK GENMASK(4, 0) +#define QUADSPI_RBCT_RXBRD_USEIPS BIT(8) -/* fsl_qspi_platdata flags */ -#define QSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0) +#define QUADSPI_TBDR 0x154 -/* default SCK frequency, unit: HZ */ -#define FSL_QSPI_DEFAULT_SCK_FREQ 50000000 +#define QUADSPI_SR 0x15c +#define QUADSPI_SR_IP_ACC_MASK BIT(1) +#define QUADSPI_SR_AHB_ACC_MASK BIT(2) -/* QSPI max chipselect signals number */ -#define FSL_QSPI_MAX_CHIPSELECT_NUM 4 +#define QUADSPI_FR 0x160 +#define QUADSPI_FR_TFF_MASK BIT(0) -/* Controller needs driver to swap endian */ +#define QUADSPI_RSER 0x164 +#define QUADSPI_RSER_TFIE BIT(0) + +#define QUADSPI_SPTRCLR 0x16c +#define QUADSPI_SPTRCLR_IPPTRC BIT(8) +#define QUADSPI_SPTRCLR_BFPTRC BIT(0) + +#define QUADSPI_SFA1AD 0x180 +#define QUADSPI_SFA2AD 0x184 +#define QUADSPI_SFB1AD 0x188 +#define QUADSPI_SFB2AD 0x18c +#define QUADSPI_RBDR(x) (0x200 + ((x) * 4)) + +#define QUADSPI_LUTKEY 0x300 +#define QUADSPI_LUTKEY_VALUE 0x5AF05AF0 + +#define QUADSPI_LCKCR 0x304 +#define QUADSPI_LCKER_LOCK BIT(0) +#define QUADSPI_LCKER_UNLOCK BIT(1) + +#define QUADSPI_LUT_BASE 0x310 +#define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4) +#define QUADSPI_LUT_REG(idx) \ + (QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4) + +/* Instruction set for the LUT register */ +#define LUT_STOP 0 +#define LUT_CMD 1 +#define LUT_ADDR 2 +#define LUT_DUMMY 3 +#define LUT_MODE 4 +#define LUT_MODE2 5 +#define LUT_MODE4 6 +#define LUT_FSL_READ 7 +#define LUT_FSL_WRITE 8 +#define LUT_JMP_ON_CS 9 +#define LUT_ADDR_DDR 10 +#define LUT_MODE_DDR 11 +#define LUT_MODE2_DDR 12 +#define LUT_MODE4_DDR 13 +#define LUT_FSL_READ_DDR 14 +#define LUT_FSL_WRITE_DDR 15 +#define LUT_DATA_LEARN 16 + +/* + * The PAD definitions for LUT register. + * + * The pad stands for the number of IO lines [0:3]. + * For example, the quad read needs four IO lines, + * so you should use LUT_PAD(4). + */ +#define LUT_PAD(x) (fls(x) - 1) + +/* + * Macro for constructing the LUT entries with the following + * register layout: + * + * --------------------------------------------------- + * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | + * --------------------------------------------------- + */ +#define LUT_DEF(idx, ins, pad, opr) \ + ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16)) + +/* Controller needs driver to swap endianness */ #define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0) -enum fsl_qspi_devtype { - FSL_QUADSPI_VYBRID, - FSL_QUADSPI_IMX6SX, - FSL_QUADSPI_IMX6UL_7D, - FSL_QUADSPI_IMX7ULP, -}; +/* Controller needs 4x internal clock */ +#define QUADSPI_QUIRK_4X_INT_CLK BIT(1) + +/* + * TKT253890, the controller needs the driver to fill the txfifo with + * 16 bytes at least to trigger a data transfer, even though the extra + * data won't be transferred. + */ +#define QUADSPI_QUIRK_TKT253890 BIT(2) + +/* TKT245618, the controller cannot wake up from wait mode */ +#define QUADSPI_QUIRK_TKT245618 BIT(3) + +/* + * Controller adds QSPI_AMBA_BASE (base address of the mapped memory) + * internally. No need to add it when setting SFXXAD and SFAR registers + */ +#define QUADSPI_QUIRK_BASE_INTERNAL BIT(4) + +/* + * Controller uses TDH bits in register QUADSPI_FLSHCR. + * They need to be set in accordance with the DDR/SDR mode. + */ +#define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5) struct fsl_qspi_devtype_data { - enum fsl_qspi_devtype devtype; - u32 rxfifo; - u32 txfifo; - u32 ahb_buf_size; - u32 driver_data; -}; - -/** - * struct fsl_qspi_platdata - platform data for Freescale QSPI - * - * @flags: Flags for QSPI QSPI_FLAG_... - * @speed_hz: Default SCK frequency - * @reg_base: Base address of QSPI registers - * @amba_base: Base address of QSPI memory mapping - * @amba_total_size: size of QSPI memory mapping - * @flash_num: Number of active slave devices - * @num_chipselect: Number of QSPI chipselect signals - */ -struct fsl_qspi_platdata { - u32 flags; - u32 speed_hz; - fdt_addr_t reg_base; - fdt_addr_t amba_base; - fdt_size_t amba_total_size; - u32 flash_num; - u32 num_chipselect; -}; - -/** - * struct fsl_qspi_priv - private data for Freescale QSPI - * - * @flags: Flags for QSPI QSPI_FLAG_... - * @bus_clk: QSPI input clk frequency - * @speed_hz: Default SCK frequency - * @cur_seqid: current LUT table sequence id - * @sf_addr: flash access offset - * @amba_base: Base address of QSPI memory mapping of every CS - * @amba_total_size: size of QSPI memory mapping - * @cur_amba_base: Base address of QSPI memory mapping of current CS - * @flash_num: Number of active slave devices - * @num_chipselect: Number of QSPI chipselect signals - * @regs: Point to QSPI register structure for I/O access - */ -struct fsl_qspi_priv { - u32 flags; - u32 bus_clk; - u32 speed_hz; - u32 cur_seqid; - u32 sf_addr; - u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM]; - u32 amba_total_size; - u32 cur_amba_base; - u32 flash_num; - u32 num_chipselect; - struct fsl_qspi_regs *regs; - struct fsl_qspi_devtype_data *devtype_data; + unsigned int rxfifo; + unsigned int txfifo; + unsigned int ahb_buf_size; + unsigned int quirks; + bool little_endian; }; static const struct fsl_qspi_devtype_data vybrid_data = { - .devtype = FSL_QUADSPI_VYBRID, - .rxfifo = 128, - .txfifo = 64, - .ahb_buf_size = 1024, - .driver_data = QUADSPI_QUIRK_SWAP_ENDIAN, + .rxfifo = SZ_128, + .txfifo = SZ_64, + .ahb_buf_size = SZ_1K, + .quirks = QUADSPI_QUIRK_SWAP_ENDIAN, + .little_endian = true, }; static const struct fsl_qspi_devtype_data imx6sx_data = { - .devtype = FSL_QUADSPI_IMX6SX, - .rxfifo = 128, - .txfifo = 512, - .ahb_buf_size = 1024, - .driver_data = 0, + .rxfifo = SZ_128, + .txfifo = SZ_512, + .ahb_buf_size = SZ_1K, + .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618, + .little_endian = true, }; -static const struct fsl_qspi_devtype_data imx6ul_7d_data = { - .devtype = FSL_QUADSPI_IMX6UL_7D, - .rxfifo = 128, - .txfifo = 512, - .ahb_buf_size = 1024, - .driver_data = 0, +static const struct fsl_qspi_devtype_data imx7d_data = { + .rxfifo = SZ_128, + .txfifo = SZ_512, + .ahb_buf_size = SZ_1K, + .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK | + QUADSPI_QUIRK_USE_TDH_SETTING, + .little_endian = true, }; -static const struct fsl_qspi_devtype_data imx7ulp_data = { - .devtype = FSL_QUADSPI_IMX7ULP, - .rxfifo = 64, - .txfifo = 64, - .ahb_buf_size = 128, - .driver_data = 0, +static const struct fsl_qspi_devtype_data imx6ul_data = { + .rxfifo = SZ_128, + .txfifo = SZ_512, + .ahb_buf_size = SZ_1K, + .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK | + QUADSPI_QUIRK_USE_TDH_SETTING, + .little_endian = true, }; -static u32 qspi_read32(u32 flags, u32 *addr) +static const struct fsl_qspi_devtype_data ls1021a_data = { + .rxfifo = SZ_128, + .txfifo = SZ_64, + .ahb_buf_size = SZ_1K, + .quirks = 0, + .little_endian = false, +}; + +static const struct fsl_qspi_devtype_data ls1088a_data = { + .rxfifo = SZ_128, + .txfifo = SZ_128, + .ahb_buf_size = SZ_1K, + .quirks = QUADSPI_QUIRK_TKT253890, + .little_endian = true, +}; + +static const struct fsl_qspi_devtype_data ls2080a_data = { + .rxfifo = SZ_128, + .txfifo = SZ_64, + .ahb_buf_size = SZ_1K, + .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL, + .little_endian = true, +}; + +struct fsl_qspi { + struct udevice *dev; + void __iomem *iobase; + void __iomem *ahb_addr; + u32 memmap_phy; + const struct fsl_qspi_devtype_data *devtype_data; + int selected; +}; + +static inline int needs_swap_endian(struct fsl_qspi *q) { - return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? - in_be32(addr) : in_le32(addr); + return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN; } -static void qspi_write32(u32 flags, u32 *addr, u32 val) +static inline int needs_4x_clock(struct fsl_qspi *q) { - flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? - out_be32(addr, val) : out_le32(addr, val); + return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK; } -static inline int is_controller_busy(const struct fsl_qspi_priv *priv) +static inline int needs_fill_txfifo(struct fsl_qspi *q) { - u32 val; - u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK | - QSPI_SR_IP_ACC_MASK; - - if (priv->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG) - mask = (u32)cpu_to_be32(mask); - - return readl_poll_timeout(&priv->regs->sr, val, !(val & mask), 1000); + return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890; } -/* QSPI support swapping the flash read/write data - * in hardware for LS102xA, but not for VF610 */ -static inline u32 qspi_endian_xchg(struct fsl_qspi_priv *priv, u32 data) +static inline int needs_wakeup_wait_mode(struct fsl_qspi *q) { - if (priv->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN) - return swab32(data); - else - return data; + return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618; } -static void qspi_set_lut(struct fsl_qspi_priv *priv) +static inline int needs_amba_base_offset(struct fsl_qspi *q) { - struct fsl_qspi_regs *regs = priv->regs; - u32 lut_base; - - /* Unlock the LUT */ - qspi_write32(priv->flags, ®s->lutkey, LUT_KEY_VALUE); - qspi_write32(priv->flags, ®s->lckcr, QSPI_LCKCR_UNLOCK); - - /* Write Enable */ - lut_base = SEQID_WREN * 4; - qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_WREN) | - PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); - qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); - qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); - qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); - - /* Fast Read */ - lut_base = SEQID_FAST_READ * 4; -#ifdef CONFIG_SPI_FLASH_BAR - qspi_write32(priv->flags, ®s->lut[lut_base], - OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) | - INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); -#else - if (FSL_QSPI_FLASH_SIZE <= SZ_16M) - qspi_write32(priv->flags, ®s->lut[lut_base], - OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) | - INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); - else - qspi_write32(priv->flags, ®s->lut[lut_base], - OPRND0(QSPI_CMD_FAST_READ_4B) | - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | - OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) | - INSTR1(LUT_ADDR)); -#endif - qspi_write32(priv->flags, ®s->lut[lut_base + 1], - OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) | - OPRND1(priv->devtype_data->rxfifo) | PAD1(LUT_PAD1) | - INSTR1(LUT_READ)); - qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); - qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); - - /* Read Status */ - lut_base = SEQID_RDSR * 4; - qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_RDSR) | - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | - PAD1(LUT_PAD1) | INSTR1(LUT_READ)); - qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); - qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); - qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); - - /* Erase a sector */ - lut_base = SEQID_SE * 4; -#ifdef CONFIG_SPI_FLASH_BAR - qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_SE) | - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); -#else - if (FSL_QSPI_FLASH_SIZE <= SZ_16M) - qspi_write32(priv->flags, ®s->lut[lut_base], - OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) | - INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); - else - qspi_write32(priv->flags, ®s->lut[lut_base], - OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) | - INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); -#endif - qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); - qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); - qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); - - /* Erase the whole chip */ - lut_base = SEQID_CHIP_ERASE * 4; - qspi_write32(priv->flags, ®s->lut[lut_base], - OPRND0(QSPI_CMD_CHIP_ERASE) | - PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); - qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); - qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); - qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); - - /* Page Program */ - lut_base = SEQID_PP * 4; -#ifdef CONFIG_SPI_FLASH_BAR - qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_PP) | - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); -#else - if (FSL_QSPI_FLASH_SIZE <= SZ_16M) - qspi_write32(priv->flags, ®s->lut[lut_base], - OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) | - INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); - else - qspi_write32(priv->flags, ®s->lut[lut_base], - OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) | - INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); -#endif - /* Use IDATSZ in IPCR to determine the size and here set 0. */ - qspi_write32(priv->flags, ®s->lut[lut_base + 1], OPRND0(0) | - PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); - qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); - qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); - - /* READ ID */ - lut_base = SEQID_RDID * 4; - qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_RDID) | - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) | - PAD1(LUT_PAD1) | INSTR1(LUT_READ)); - qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); - qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); - qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); - - /* SUB SECTOR 4K ERASE */ - lut_base = SEQID_BE_4K * 4; - qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) | - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); - -#ifdef CONFIG_SPI_FLASH_BAR - /* - * BRRD BRWR RDEAR WREAR are all supported, because it is hard to - * dynamically check whether to set BRRD BRWR or RDEAR WREAR during - * initialization. - */ - lut_base = SEQID_BRRD * 4; - qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_BRRD) | - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | - PAD1(LUT_PAD1) | INSTR1(LUT_READ)); - - lut_base = SEQID_BRWR * 4; - qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_BRWR) | - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | - PAD1(LUT_PAD1) | INSTR1(LUT_WRITE)); - - lut_base = SEQID_RDEAR * 4; - qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) | - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | - PAD1(LUT_PAD1) | INSTR1(LUT_READ)); - - lut_base = SEQID_WREAR * 4; - qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_WREAR) | - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | - PAD1(LUT_PAD1) | INSTR1(LUT_WRITE)); -#endif - - /* - * Read any device register. - * Used for Spansion S25FS-S family flash only. - */ - lut_base = SEQID_RDAR * 4; - qspi_write32(priv->flags, ®s->lut[lut_base], - OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) | - INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); - qspi_write32(priv->flags, ®s->lut[lut_base + 1], - OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) | - OPRND1(1) | PAD1(LUT_PAD1) | - INSTR1(LUT_READ)); - - /* - * Write any device register. - * Used for Spansion S25FS-S family flash only. - */ - lut_base = SEQID_WRAR * 4; - qspi_write32(priv->flags, ®s->lut[lut_base], - OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) | - INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); - qspi_write32(priv->flags, ®s->lut[lut_base + 1], - OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); - - /* Lock the LUT */ - qspi_write32(priv->flags, ®s->lutkey, LUT_KEY_VALUE); - qspi_write32(priv->flags, ®s->lckcr, QSPI_LCKCR_LOCK); + return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL); +} + +static inline int needs_tdh_setting(struct fsl_qspi *q) +{ + return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING; } -#if defined(CONFIG_SYS_FSL_QSPI_AHB) /* - * If we have changed the content of the flash by writing or erasing, - * we need to invalidate the AHB buffer. If we do not do so, we may read out - * the wrong data. The spec tells us reset the AHB domain and Serial Flash - * domain at the same time. + * An IC bug makes it necessary to rearrange the 32-bit data. + * Later chips, such as IMX6SLX, have fixed this bug. */ -static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv) +static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a) +{ + return needs_swap_endian(q) ? __swab32(a) : a; +} + +/* + * R/W functions for big- or little-endian registers: + * The QSPI controller's endianness is independent of + * the CPU core's endianness. So far, although the CPU + * core is little-endian the QSPI controller can use + * big-endian or little-endian. + */ +static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr) +{ + if (q->devtype_data->little_endian) + out_le32(addr, val); + else + out_be32(addr, val); +} + +static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr) +{ + if (q->devtype_data->little_endian) + return in_le32(addr); + + return in_be32(addr); +} + +static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width) +{ + switch (width) { + case 1: + case 2: + case 4: + return 0; + } + + return -ENOTSUPP; +} + +static bool fsl_qspi_supports_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + struct fsl_qspi *q = dev_get_priv(slave->dev->parent); + int ret; + + ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth); + + if (op->addr.nbytes) + ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth); + + if (op->dummy.nbytes) + ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth); + + if (op->data.nbytes) + ret |= fsl_qspi_check_buswidth(q, op->data.buswidth); + + if (ret) + return false; + + /* + * The number of instructions needed for the op, needs + * to fit into a single LUT entry. + */ + if (op->addr.nbytes + + (op->dummy.nbytes ? 1 : 0) + + (op->data.nbytes ? 1 : 0) > 6) + return false; + + /* Max 64 dummy clock cycles supported */ + if (op->dummy.nbytes && + (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)) + return false; + + /* Max data length, check controller limits and alignment */ + if (op->data.dir == SPI_MEM_DATA_IN && + (op->data.nbytes > q->devtype_data->ahb_buf_size || + (op->data.nbytes > q->devtype_data->rxfifo - 4 && + !IS_ALIGNED(op->data.nbytes, 8)))) + return false; + + if (op->data.dir == SPI_MEM_DATA_OUT && + op->data.nbytes > q->devtype_data->txfifo) + return false; + + return true; +} + +static void fsl_qspi_prepare_lut(struct fsl_qspi *q, + const struct spi_mem_op *op) +{ + void __iomem *base = q->iobase; + u32 lutval[4] = {}; + int lutidx = 1, i; + + lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), + op->cmd.opcode); + + /* + * For some unknown reason, using LUT_ADDR doesn't work in some + * cases (at least with only one byte long addresses), so + * let's use LUT_MODE to write the address bytes one by one + */ + for (i = 0; i < op->addr.nbytes; i++) { + u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1)); + + lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE, + LUT_PAD(op->addr.buswidth), + addrbyte); + lutidx++; + } + + if (op->dummy.nbytes) { + lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY, + LUT_PAD(op->dummy.buswidth), + op->dummy.nbytes * 8 / + op->dummy.buswidth); + lutidx++; + } + + if (op->data.nbytes) { + lutval[lutidx / 2] |= LUT_DEF(lutidx, + op->data.dir == SPI_MEM_DATA_IN ? + LUT_FSL_READ : LUT_FSL_WRITE, + LUT_PAD(op->data.buswidth), + 0); + lutidx++; + } + + lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0); + + /* unlock LUT */ + qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); + qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR); + + dev_dbg(q->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n", + op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]); + + /* fill LUT */ + for (i = 0; i < ARRAY_SIZE(lutval); i++) + qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i)); + + /* lock LUT */ + qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); + qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); +} + +/* + * If we have changed the content of the flash by writing or erasing, or if we + * read from flash with a different offset into the page buffer, we need to + * invalidate the AHB buffer. If we do not do so, we may read out the wrong + * data. The spec tells us reset the AHB domain and Serial Flash domain at + * the same time. + */ +static void fsl_qspi_invalidate(struct fsl_qspi *q) { - struct fsl_qspi_regs *regs = priv->regs; u32 reg; - reg = qspi_read32(priv->flags, ®s->mcr); - reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK; - qspi_write32(priv->flags, ®s->mcr, reg); + reg = qspi_readl(q, q->iobase + QUADSPI_MCR); + reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK; + qspi_writel(q, reg, q->iobase + QUADSPI_MCR); /* * The minimum delay : 1 AHB + 2 SFCK clocks. @@ -415,728 +460,322 @@ static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv) */ udelay(1); - reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK); - qspi_write32(priv->flags, ®s->mcr, reg); + reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK); + qspi_writel(q, reg, q->iobase + QUADSPI_MCR); } -/* Read out the data from the AHB buffer. */ -static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len) +static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave) { - struct fsl_qspi_regs *regs = priv->regs; - u32 mcr_reg; - void *rx_addr; + struct dm_spi_slave_platdata *plat = + dev_get_parent_platdata(slave->dev); - mcr_reg = qspi_read32(priv->flags, ®s->mcr); + if (q->selected == plat->cs) + return; - qspi_write32(priv->flags, ®s->mcr, - QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - mcr_reg); - - rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr); - /* Read out the data directly from the AHB buffer. */ - memcpy(rxbuf, rx_addr, len); - - qspi_write32(priv->flags, ®s->mcr, mcr_reg); + q->selected = plat->cs; + fsl_qspi_invalidate(q); } -static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv) +static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op) { - u32 reg, reg2; - struct fsl_qspi_regs *regs = priv->regs; - - reg = qspi_read32(priv->flags, ®s->mcr); - /* Disable the module */ - qspi_write32(priv->flags, ®s->mcr, reg | QSPI_MCR_MDIS_MASK); - - /* Set the Sampling Register for DDR */ - reg2 = qspi_read32(priv->flags, ®s->smpr); - reg2 &= ~QSPI_SMPR_DDRSMP_MASK; - reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT); - qspi_write32(priv->flags, ®s->smpr, reg2); - - /* Enable the module again (enable the DDR too) */ - reg |= QSPI_MCR_DDR_EN_MASK; - /* Enable bit 29 for imx6sx */ - reg |= BIT(29); - qspi_write32(priv->flags, ®s->mcr, reg); - - /* Enable the TDH to 1 for some platforms like imx6ul, imx7d, etc - * These two bits are reserved on other platforms - */ - reg = qspi_read32(priv->flags, ®s->flshcr); - reg &= ~(BIT(17)); - reg |= BIT(16); - qspi_write32(priv->flags, ®s->flshcr, reg); + memcpy_fromio(op->data.buf.in, + q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size, + op->data.nbytes); } -/* - * There are two different ways to read out the data from the flash: - * the "IP Command Read" and the "AHB Command Read". - * - * The IC guy suggests we use the "AHB Command Read" which is faster - * then the "IP Command Read". (What's more is that there is a bug in - * the "IP Command Read" in the Vybrid.) - * - * After we set up the registers for the "AHB Command Read", we can use - * the memcpy to read the data directly. A "missed" access to the buffer - * causes the controller to clear the buffer, and use the sequence pointed - * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash. - */ -static void qspi_init_ahb_read(struct fsl_qspi_priv *priv) +static void fsl_qspi_fill_txfifo(struct fsl_qspi *q, + const struct spi_mem_op *op) { - struct fsl_qspi_regs *regs = priv->regs; - - /* AHB configuration for access buffer 0/1/2 .*/ - qspi_write32(priv->flags, ®s->buf0cr, QSPI_BUFXCR_INVALID_MSTRID); - qspi_write32(priv->flags, ®s->buf1cr, QSPI_BUFXCR_INVALID_MSTRID); - qspi_write32(priv->flags, ®s->buf2cr, QSPI_BUFXCR_INVALID_MSTRID); - qspi_write32(priv->flags, ®s->buf3cr, QSPI_BUF3CR_ALLMST_MASK | - ((priv->devtype_data->ahb_buf_size >> 3) << QSPI_BUF3CR_ADATSZ_SHIFT)); - - /* We only use the buffer3 */ - qspi_write32(priv->flags, ®s->buf0ind, 0); - qspi_write32(priv->flags, ®s->buf1ind, 0); - qspi_write32(priv->flags, ®s->buf2ind, 0); - - /* - * Set the default lut sequence for AHB Read. - * Parallel mode is disabled. - */ - qspi_write32(priv->flags, ®s->bfgencr, - SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT); - - /*Enable DDR Mode*/ - qspi_enable_ddr_mode(priv); -} -#endif - -#ifdef CONFIG_SPI_FLASH_BAR -/* Bank register read/write, EAR register read/write */ -static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len) -{ - struct fsl_qspi_regs *regs = priv->regs; - u32 reg, mcr_reg, data, seqid; - - mcr_reg = qspi_read32(priv->flags, ®s->mcr); - qspi_write32(priv->flags, ®s->mcr, - QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - mcr_reg); - qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); - - qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base); - - if (priv->cur_seqid == QSPI_CMD_BRRD) - seqid = SEQID_BRRD; - else - seqid = SEQID_RDEAR; - - qspi_write32(priv->flags, ®s->ipcr, - (seqid << QSPI_IPCR_SEQID_SHIFT) | len); - - /* Wait previous command complete */ - while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) - ; - - while (1) { - WATCHDOG_RESET(); - - reg = qspi_read32(priv->flags, ®s->rbsr); - if (reg & QSPI_RBSR_RDBFL_MASK) { - data = qspi_read32(priv->flags, ®s->rbdr[0]); - data = qspi_endian_xchg(priv, data); - memcpy(rxbuf, &data, len); - qspi_write32(priv->flags, ®s->mcr, - qspi_read32(priv->flags, ®s->mcr) | - QSPI_MCR_CLR_RXF_MASK); - break; - } - } - - qspi_write32(priv->flags, ®s->mcr, mcr_reg); -} -#endif - -static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) -{ - struct fsl_qspi_regs *regs = priv->regs; - u32 mcr_reg, rbsr_reg, data, size; + void __iomem *base = q->iobase; int i; + u32 val; - mcr_reg = qspi_read32(priv->flags, ®s->mcr); - qspi_write32(priv->flags, ®s->mcr, - QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - mcr_reg); - qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); - - qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base); - - qspi_write32(priv->flags, ®s->ipcr, - (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0); - while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) - ; - - i = 0; - while ((priv->devtype_data->rxfifo >= len) && (len > 0)) { - WATCHDOG_RESET(); - - rbsr_reg = qspi_read32(priv->flags, ®s->rbsr); - if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) { - data = qspi_read32(priv->flags, ®s->rbdr[i]); - data = qspi_endian_xchg(priv, data); - size = (len < 4) ? len : 4; - memcpy(rxbuf, &data, size); - len -= size; - rxbuf++; - i++; - } + for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) { + memcpy(&val, op->data.buf.out + i, 4); + val = fsl_qspi_endian_xchg(q, val); + qspi_writel(q, val, base + QUADSPI_TBDR); } - qspi_write32(priv->flags, ®s->mcr, mcr_reg); + if (i < op->data.nbytes) { + memcpy(&val, op->data.buf.out + i, op->data.nbytes - i); + val = fsl_qspi_endian_xchg(q, val); + qspi_writel(q, val, base + QUADSPI_TBDR); + } + + if (needs_fill_txfifo(q)) { + for (i = op->data.nbytes; i < 16; i += 4) + qspi_writel(q, 0, base + QUADSPI_TBDR); + } } -/* If not use AHB read, read data from ip interface */ -static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) +static void fsl_qspi_read_rxfifo(struct fsl_qspi *q, + const struct spi_mem_op *op) { - struct fsl_qspi_regs *regs = priv->regs; - u32 mcr_reg, data; - int i, size; - u32 to_or_from; - u32 seqid; + void __iomem *base = q->iobase; + int i; + u8 *buf = op->data.buf.in; + u32 val; - if (priv->cur_seqid == QSPI_CMD_RDAR) - seqid = SEQID_RDAR; - else - seqid = SEQID_FAST_READ; - - mcr_reg = qspi_read32(priv->flags, ®s->mcr); - qspi_write32(priv->flags, ®s->mcr, - QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - mcr_reg); - qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); - - to_or_from = priv->sf_addr + priv->cur_amba_base; - - while (len > 0) { - WATCHDOG_RESET(); - - qspi_write32(priv->flags, ®s->sfar, to_or_from); - - size = (len > priv->devtype_data->rxfifo) ? - priv->devtype_data->rxfifo : len; - - qspi_write32(priv->flags, ®s->ipcr, - (seqid << QSPI_IPCR_SEQID_SHIFT) | - size); - while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) - ; - - to_or_from += size; - len -= size; - - i = 0; - while ((priv->devtype_data->rxfifo >= size) && (size > 0)) { - data = qspi_read32(priv->flags, ®s->rbdr[i]); - data = qspi_endian_xchg(priv, data); - if (size < 4) - memcpy(rxbuf, &data, size); - else - memcpy(rxbuf, &data, 4); - rxbuf++; - size -= 4; - i++; - } - qspi_write32(priv->flags, ®s->mcr, - qspi_read32(priv->flags, ®s->mcr) | - QSPI_MCR_CLR_RXF_MASK); + for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) { + val = qspi_readl(q, base + QUADSPI_RBDR(i / 4)); + val = fsl_qspi_endian_xchg(q, val); + memcpy(buf + i, &val, 4); } - qspi_write32(priv->flags, ®s->mcr, mcr_reg); + if (i < op->data.nbytes) { + val = qspi_readl(q, base + QUADSPI_RBDR(i / 4)); + val = fsl_qspi_endian_xchg(q, val); + memcpy(buf + i, &val, op->data.nbytes - i); + } } -static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) +static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base, + u32 mask, u32 delay_us, u32 timeout_us) { - struct fsl_qspi_regs *regs = priv->regs; - u32 mcr_reg, data, reg, status_reg, seqid; - int i, size, tx_size; - u32 to_or_from = 0; + u32 reg; - mcr_reg = qspi_read32(priv->flags, ®s->mcr); - qspi_write32(priv->flags, ®s->mcr, - QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - mcr_reg); - qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); + if (!q->devtype_data->little_endian) + mask = (u32)cpu_to_be32(mask); - status_reg = 0; - while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) { - WATCHDOG_RESET(); + return readl_poll_timeout(base, reg, !(reg & mask), timeout_us); +} - qspi_write32(priv->flags, ®s->ipcr, - (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); - while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) - ; +static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op) +{ + void __iomem *base = q->iobase; + int err = 0; - qspi_write32(priv->flags, ®s->ipcr, - (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1); - while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) - ; - - reg = qspi_read32(priv->flags, ®s->rbsr); - if (reg & QSPI_RBSR_RDBFL_MASK) { - status_reg = qspi_read32(priv->flags, ®s->rbdr[0]); - status_reg = qspi_endian_xchg(priv, status_reg); - } - qspi_write32(priv->flags, ®s->mcr, - qspi_read32(priv->flags, ®s->mcr) | - QSPI_MCR_CLR_RXF_MASK); - } - - /* Default is page programming */ - seqid = SEQID_PP; - if (priv->cur_seqid == QSPI_CMD_WRAR) - seqid = SEQID_WRAR; -#ifdef CONFIG_SPI_FLASH_BAR - if (priv->cur_seqid == QSPI_CMD_BRWR) - seqid = SEQID_BRWR; - else if (priv->cur_seqid == QSPI_CMD_WREAR) - seqid = SEQID_WREAR; -#endif - - to_or_from = priv->sf_addr + priv->cur_amba_base; - - qspi_write32(priv->flags, ®s->sfar, to_or_from); - - tx_size = (len > priv->devtype_data->txfifo) ? - priv->devtype_data->txfifo : len; - - size = tx_size / 16; /* - * There must be atleast 128bit data - * available in TX FIFO for any pop operation + * Always start the sequence at the same index since we update + * the LUT at each exec_op() call. And also specify the DATA + * length, since it's has not been specified in the LUT. */ - if (tx_size % 16) - size++; - for (i = 0; i < size * 4; i++) { - memcpy(&data, txbuf, 4); - data = qspi_endian_xchg(priv, data); - qspi_write32(priv->flags, ®s->tbdr, data); - txbuf += 4; - } + qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT), + base + QUADSPI_IPCR); - qspi_write32(priv->flags, ®s->ipcr, - (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size); - while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) - ; + /* wait for the controller being ready */ + err = fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, + (QUADSPI_SR_IP_ACC_MASK | + QUADSPI_SR_AHB_ACC_MASK), + 10, 1000); - qspi_write32(priv->flags, ®s->mcr, mcr_reg); + if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN) + fsl_qspi_read_rxfifo(q, op); + + return err; } -static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len) +static int fsl_qspi_exec_op(struct spi_slave *slave, + const struct spi_mem_op *op) { - struct fsl_qspi_regs *regs = priv->regs; - u32 mcr_reg, reg, data; + struct fsl_qspi *q = dev_get_priv(slave->dev->parent); + void __iomem *base = q->iobase; + u32 addr_offset = 0; + int err = 0; - mcr_reg = qspi_read32(priv->flags, ®s->mcr); - qspi_write32(priv->flags, ®s->mcr, - QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - mcr_reg); - qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); + /* wait for the controller being ready */ + fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK | + QUADSPI_SR_AHB_ACC_MASK), 10, 1000); - qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base); + fsl_qspi_select_mem(q, slave); - qspi_write32(priv->flags, ®s->ipcr, - (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0); - while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) - ; + if (needs_amba_base_offset(q)) + addr_offset = q->memmap_phy; - while (1) { - WATCHDOG_RESET(); + qspi_writel(q, + q->selected * q->devtype_data->ahb_buf_size + addr_offset, + base + QUADSPI_SFAR); - reg = qspi_read32(priv->flags, ®s->rbsr); - if (reg & QSPI_RBSR_RDBFL_MASK) { - data = qspi_read32(priv->flags, ®s->rbdr[0]); - data = qspi_endian_xchg(priv, data); - memcpy(rxbuf, &data, len); - qspi_write32(priv->flags, ®s->mcr, - qspi_read32(priv->flags, ®s->mcr) | - QSPI_MCR_CLR_RXF_MASK); - break; - } + qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) | + QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK, + base + QUADSPI_MCR); + + qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC, + base + QUADSPI_SPTRCLR); + + fsl_qspi_prepare_lut(q, op); + + /* + * If we have large chunks of data, we read them through the AHB bus + * by accessing the mapped memory. In all other cases we use + * IP commands to access the flash. + */ + if (op->data.nbytes > (q->devtype_data->rxfifo - 4) && + op->data.dir == SPI_MEM_DATA_IN) { + fsl_qspi_read_ahb(q, op); + } else { + qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | + QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT); + + if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) + fsl_qspi_fill_txfifo(q, op); + + err = fsl_qspi_do_op(q, op); } - qspi_write32(priv->flags, ®s->mcr, mcr_reg); + /* Invalidate the data in the AHB buffer. */ + fsl_qspi_invalidate(q); + + return err; } -static void qspi_op_erase(struct fsl_qspi_priv *priv) +static int fsl_qspi_adjust_op_size(struct spi_slave *slave, + struct spi_mem_op *op) { - struct fsl_qspi_regs *regs = priv->regs; - u32 mcr_reg; - u32 to_or_from = 0; + struct fsl_qspi *q = dev_get_priv(slave->dev->parent); - mcr_reg = qspi_read32(priv->flags, ®s->mcr); - qspi_write32(priv->flags, ®s->mcr, - QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - mcr_reg); - qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); - - to_or_from = priv->sf_addr + priv->cur_amba_base; - qspi_write32(priv->flags, ®s->sfar, to_or_from); - - qspi_write32(priv->flags, ®s->ipcr, - (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); - while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) - ; - - if (priv->cur_seqid == QSPI_CMD_SE) { - qspi_write32(priv->flags, ®s->ipcr, - (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0); - } else if (priv->cur_seqid == QSPI_CMD_BE_4K) { - qspi_write32(priv->flags, ®s->ipcr, - (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0); + if (op->data.dir == SPI_MEM_DATA_OUT) { + if (op->data.nbytes > q->devtype_data->txfifo) + op->data.nbytes = q->devtype_data->txfifo; + } else { + if (op->data.nbytes > q->devtype_data->ahb_buf_size) + op->data.nbytes = q->devtype_data->ahb_buf_size; + else if (op->data.nbytes > (q->devtype_data->rxfifo - 4)) + op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); } - while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) - ; - - qspi_write32(priv->flags, ®s->mcr, mcr_reg); -} - -int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - u32 bytes = DIV_ROUND_UP(bitlen, 8); - static u32 wr_sfaddr; - u32 txbuf; - - WATCHDOG_RESET(); - - if (dout) { - if (flags & SPI_XFER_BEGIN) { - priv->cur_seqid = *(u8 *)dout; - memcpy(&txbuf, dout, 4); - } - - if (flags == SPI_XFER_END) { - priv->sf_addr = wr_sfaddr; - qspi_op_write(priv, (u8 *)dout, bytes); - return 0; - } - - if (priv->cur_seqid == QSPI_CMD_FAST_READ || - priv->cur_seqid == QSPI_CMD_RDAR) { - priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; - } else if ((priv->cur_seqid == QSPI_CMD_SE) || - (priv->cur_seqid == QSPI_CMD_BE_4K)) { - priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; - qspi_op_erase(priv); - } else if (priv->cur_seqid == QSPI_CMD_PP || - priv->cur_seqid == QSPI_CMD_WRAR) { - wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK; - } else if ((priv->cur_seqid == QSPI_CMD_BRWR) || - (priv->cur_seqid == QSPI_CMD_WREAR)) { -#ifdef CONFIG_SPI_FLASH_BAR - wr_sfaddr = 0; -#endif - } - } - - if (din) { - if (priv->cur_seqid == QSPI_CMD_FAST_READ) { -#ifdef CONFIG_SYS_FSL_QSPI_AHB - qspi_ahb_read(priv, din, bytes); -#else - qspi_op_read(priv, din, bytes); -#endif - } else if (priv->cur_seqid == QSPI_CMD_RDAR) { - qspi_op_read(priv, din, bytes); - } else if (priv->cur_seqid == QSPI_CMD_RDID) - qspi_op_rdid(priv, din, bytes); - else if (priv->cur_seqid == QSPI_CMD_RDSR) - qspi_op_rdsr(priv, din, bytes); -#ifdef CONFIG_SPI_FLASH_BAR - else if ((priv->cur_seqid == QSPI_CMD_BRRD) || - (priv->cur_seqid == QSPI_CMD_RDEAR)) { - priv->sf_addr = 0; - qspi_op_rdbank(priv, din, bytes); - } -#endif - } - -#ifdef CONFIG_SYS_FSL_QSPI_AHB - if ((priv->cur_seqid == QSPI_CMD_SE) || - (priv->cur_seqid == QSPI_CMD_PP) || - (priv->cur_seqid == QSPI_CMD_BE_4K) || - (priv->cur_seqid == QSPI_CMD_WREAR) || - (priv->cur_seqid == QSPI_CMD_BRWR)) - qspi_ahb_invalid(priv); -#endif return 0; } -void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable) +static int fsl_qspi_default_setup(struct fsl_qspi *q) { - u32 mcr_val; + void __iomem *base = q->iobase; + u32 reg, addr_offset = 0; - mcr_val = qspi_read32(priv->flags, &priv->regs->mcr); - if (disable) - mcr_val |= QSPI_MCR_MDIS_MASK; - else - mcr_val &= ~QSPI_MCR_MDIS_MASK; - qspi_write32(priv->flags, &priv->regs->mcr, mcr_val); -} + /* Reset the module */ + qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK, + base + QUADSPI_MCR); + udelay(1); -void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits) -{ - u32 smpr_val; + /* Disable the module */ + qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK, + base + QUADSPI_MCR); - smpr_val = qspi_read32(priv->flags, &priv->regs->smpr); - smpr_val &= ~clear_bits; - smpr_val |= set_bits; - qspi_write32(priv->flags, &priv->regs->smpr, smpr_val); -} + /* + * Previous boot stages (BootROM, bootloader) might have used DDR + * mode and did not clear the TDH bits. As we currently use SDR mode + * only, clear the TDH bits if necessary. + */ + if (needs_tdh_setting(q)) + qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) & + ~QUADSPI_FLSHCR_TDH_MASK, + base + QUADSPI_FLSHCR); -static int fsl_qspi_child_pre_probe(struct udevice *dev) -{ - struct spi_slave *slave = dev_get_parent_priv(dev); - struct fsl_qspi_priv *priv = dev_get_priv(dev_get_parent(dev)); + reg = qspi_readl(q, base + QUADSPI_SMPR); + qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK + | QUADSPI_SMPR_FSPHS_MASK + | QUADSPI_SMPR_HSENA_MASK + | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR); - slave->max_write_size = priv->devtype_data->txfifo; + /* We only use the buffer3 for AHB read */ + qspi_writel(q, 0, base + QUADSPI_BUF0IND); + qspi_writel(q, 0, base + QUADSPI_BUF1IND); + qspi_writel(q, 0, base + QUADSPI_BUF2IND); + qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT), + q->iobase + QUADSPI_BFGENCR); + qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT); + qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | + QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8), + base + QUADSPI_BUF3CR); + + if (needs_amba_base_offset(q)) + addr_offset = q->memmap_phy; + + /* + * In HW there can be a maximum of four chips on two buses with + * two chip selects on each bus. We use four chip selects in SW + * to differentiate between the four chips. + * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD, + * SFB2AD accordingly. + */ + qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset, + base + QUADSPI_SFA1AD); + qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset, + base + QUADSPI_SFA2AD); + qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset, + base + QUADSPI_SFB1AD); + qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset, + base + QUADSPI_SFB2AD); + + q->selected = -1; + + /* Enable the module */ + qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK, + base + QUADSPI_MCR); return 0; } +static const struct spi_controller_mem_ops fsl_qspi_mem_ops = { + .adjust_op_size = fsl_qspi_adjust_op_size, + .supports_op = fsl_qspi_supports_op, + .exec_op = fsl_qspi_exec_op, +}; + static int fsl_qspi_probe(struct udevice *bus) { - u32 amba_size_per_chip; - struct fsl_qspi_platdata *plat = dev_get_platdata(bus); - struct fsl_qspi_priv *priv = dev_get_priv(bus); - struct dm_spi_bus *dm_spi_bus; - int i, ret; - - dm_spi_bus = bus->uclass_priv; - - dm_spi_bus->max_hz = plat->speed_hz; - - priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base; - priv->flags = plat->flags; - - priv->speed_hz = plat->speed_hz; - /* - * QSPI SFADR width is 32bits, the max dest addr is 4GB-1. - * AMBA memory zone should be located on the 0~4GB space - * even on a 64bits cpu. - */ - priv->amba_base[0] = (u32)plat->amba_base; - priv->amba_total_size = (u32)plat->amba_total_size; - priv->flash_num = plat->flash_num; - priv->num_chipselect = plat->num_chipselect; - - priv->devtype_data = (struct fsl_qspi_devtype_data *)dev_get_driver_data(bus); - if (!priv->devtype_data) { - printf("ERROR : No devtype_data found\n"); - return -ENODEV; - } - - debug("devtype=%d, txfifo=%d, rxfifo=%d, ahb=%d, data=0x%x\n", - priv->devtype_data->devtype, - priv->devtype_data->txfifo, - priv->devtype_data->rxfifo, - priv->devtype_data->ahb_buf_size, - priv->devtype_data->driver_data); - - /* make sure controller is not busy anywhere */ - ret = is_controller_busy(priv); - - if (ret) { - debug("ERROR : The controller is busy\n"); - return ret; - } - - qspi_write32(priv->flags, &priv->regs->mcr, - QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK | - QSPI_MCR_END_CFD_LE); - - qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK | - QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0); - - /* - * Assign AMBA memory zone for every chipselect - * QuadSPI has two channels, every channel has two chipselects. - * If the property 'num-cs' in dts is 2, the AMBA memory will be divided - * into two parts and assign to every channel. This indicate that every - * channel only has one valid chipselect. - * If the property 'num-cs' in dts is 4, the AMBA memory will be divided - * into four parts and assign to every chipselect. - * Every channel will has two valid chipselects. - */ - amba_size_per_chip = priv->amba_total_size >> - (priv->num_chipselect >> 1); - for (i = 1 ; i < priv->num_chipselect ; i++) - priv->amba_base[i] = - amba_size_per_chip + priv->amba_base[i - 1]; - - /* - * Any read access to non-implemented addresses will provide - * undefined results. - * - * In case single die flash devices, TOP_ADDR_MEMA2 and - * TOP_ADDR_MEMB2 should be initialized/programmed to - * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect, - * setting the size of these devices to 0. This would ensure - * that the complete memory map is assigned to only one flash device. - */ - qspi_write32(priv->flags, &priv->regs->sfa1ad, - priv->amba_base[0] + amba_size_per_chip); - switch (priv->num_chipselect) { - case 1: - break; - case 2: - qspi_write32(priv->flags, &priv->regs->sfa2ad, - priv->amba_base[1]); - qspi_write32(priv->flags, &priv->regs->sfb1ad, - priv->amba_base[1] + amba_size_per_chip); - qspi_write32(priv->flags, &priv->regs->sfb2ad, - priv->amba_base[1] + amba_size_per_chip); - break; - case 4: - qspi_write32(priv->flags, &priv->regs->sfa2ad, - priv->amba_base[2]); - qspi_write32(priv->flags, &priv->regs->sfb1ad, - priv->amba_base[3]); - qspi_write32(priv->flags, &priv->regs->sfb2ad, - priv->amba_base[3] + amba_size_per_chip); - break; - default: - debug("Error: Unsupported chipselect number %u!\n", - priv->num_chipselect); - qspi_module_disable(priv, 1); - return -EINVAL; - } - - qspi_set_lut(priv); - -#ifdef CONFIG_SYS_FSL_QSPI_AHB - qspi_init_ahb_read(priv); -#endif - - qspi_module_disable(priv, 0); - - return 0; -} - -static int fsl_qspi_ofdata_to_platdata(struct udevice *bus) -{ - struct fdt_resource res_regs, res_mem; - struct fsl_qspi_platdata *plat = bus->platdata; + struct dm_spi_bus *dm_bus = bus->uclass_priv; + struct fsl_qspi *q = dev_get_priv(bus); const void *blob = gd->fdt_blob; int node = dev_of_offset(bus); - int ret, flash_num = 0, subnode; + struct fdt_resource res; + int ret; - if (fdtdec_get_bool(blob, node, "big-endian")) - plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG; + q->dev = bus; + q->devtype_data = (struct fsl_qspi_devtype_data *) + dev_get_driver_data(bus); - ret = fdt_get_named_resource(blob, node, "reg", "reg-names", - "QuadSPI", &res_regs); + /* find the resources */ + ret = fdt_get_named_resource(blob, node, "reg", "reg-names", "QuadSPI", + &res); if (ret) { - debug("Error: can't get regs base addresses(ret = %d)!\n", ret); - return -ENOMEM; - } - ret = fdt_get_named_resource(blob, node, "reg", "reg-names", - "QuadSPI-memory", &res_mem); - if (ret) { - debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret); + dev_err(bus, "Can't get regs base addresses(ret = %d)!\n", ret); return -ENOMEM; } - /* Count flash numbers */ - fdt_for_each_subnode(subnode, blob, node) - ++flash_num; + q->iobase = map_physmem(res.start, res.end - res.start, MAP_NOCACHE); - if (flash_num == 0) { - debug("Error: Missing flashes!\n"); - return -ENODEV; + ret = fdt_get_named_resource(blob, node, "reg", "reg-names", + "QuadSPI-memory", &res); + if (ret) { + dev_err(bus, "Can't get AMBA base addresses(ret = %d)!\n", ret); + return -ENOMEM; } - plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency", - FSL_QSPI_DEFAULT_SCK_FREQ); - plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs", - FSL_QSPI_MAX_CHIPSELECT_NUM); + q->ahb_addr = map_physmem(res.start, res.end - res.start, MAP_NOCACHE); + q->memmap_phy = res.start; - plat->reg_base = res_regs.start; - plat->amba_base = res_mem.start; - plat->amba_total_size = res_mem.end - res_mem.start + 1; - plat->flash_num = flash_num; + dm_bus->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", + 66000000); - debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n", - __func__, - (u64)plat->reg_base, - (u64)plat->amba_base, - (u64)plat->amba_total_size, - plat->speed_hz, - plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le" - ); + fsl_qspi_default_setup(q); return 0; } static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) + const void *dout, void *din, unsigned long flags) { - struct fsl_qspi_priv *priv; - struct udevice *bus; - - bus = dev->parent; - priv = dev_get_priv(bus); - - return qspi_xfer(priv, bitlen, dout, din, flags); + return 0; } static int fsl_qspi_claim_bus(struct udevice *dev) { - struct fsl_qspi_priv *priv; - struct udevice *bus; - struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); - int ret; - - bus = dev->parent; - priv = dev_get_priv(bus); - - /* make sure controller is not busy anywhere */ - ret = is_controller_busy(priv); - - if (ret) { - debug("ERROR : The controller is busy\n"); - return ret; - } - - priv->cur_amba_base = priv->amba_base[slave_plat->cs]; - - qspi_module_disable(priv, 0); - return 0; } static int fsl_qspi_release_bus(struct udevice *dev) { - struct fsl_qspi_priv *priv; - struct udevice *bus; - - bus = dev->parent; - priv = dev_get_priv(bus); - - qspi_module_disable(priv, 1); - return 0; } static int fsl_qspi_set_speed(struct udevice *bus, uint speed) { - /* Nothing to do */ return 0; } static int fsl_qspi_set_mode(struct udevice *bus, uint mode) { - /* Nothing to do */ return 0; } @@ -1146,14 +785,17 @@ static const struct dm_spi_ops fsl_qspi_ops = { .xfer = fsl_qspi_xfer, .set_speed = fsl_qspi_set_speed, .set_mode = fsl_qspi_set_mode, + .mem_ops = &fsl_qspi_mem_ops, }; static const struct udevice_id fsl_qspi_ids[] = { - { .compatible = "fsl,vf610-qspi", .data = (ulong)&vybrid_data }, - { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data }, - { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_7d_data }, - { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx6ul_7d_data }, - { .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data }, + { .compatible = "fsl,vf610-qspi", .data = (ulong)&vybrid_data, }, + { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data, }, + { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_data, }, + { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, }, + { .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, }, + { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls1088a_data, }, + { .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, }, { } }; @@ -1162,9 +804,6 @@ U_BOOT_DRIVER(fsl_qspi) = { .id = UCLASS_SPI, .of_match = fsl_qspi_ids, .ops = &fsl_qspi_ops, - .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata), - .priv_auto_alloc_size = sizeof(struct fsl_qspi_priv), + .priv_auto_alloc_size = sizeof(struct fsl_qspi), .probe = fsl_qspi_probe, - .child_pre_probe = fsl_qspi_child_pre_probe, }; diff --git a/drivers/spi/fsl_qspi.h b/drivers/spi/fsl_qspi.h deleted file mode 100644 index 9e61a852b5a..00000000000 --- a/drivers/spi/fsl_qspi.h +++ /dev/null @@ -1,145 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - * - * Register definitions for Freescale QSPI - */ - -#ifndef _FSL_QSPI_H_ -#define _FSL_QSPI_H_ - -struct fsl_qspi_regs { - u32 mcr; - u32 rsvd0[1]; - u32 ipcr; - u32 flshcr; - u32 buf0cr; - u32 buf1cr; - u32 buf2cr; - u32 buf3cr; - u32 bfgencr; - u32 soccr; - u32 rsvd1[2]; - u32 buf0ind; - u32 buf1ind; - u32 buf2ind; - u32 rsvd2[49]; - u32 sfar; - u32 rsvd3[1]; - u32 smpr; - u32 rbsr; - u32 rbct; - u32 rsvd4[15]; - u32 tbsr; - u32 tbdr; - u32 rsvd5[1]; - u32 sr; - u32 fr; - u32 rser; - u32 spndst; - u32 sptrclr; - u32 rsvd6[4]; - u32 sfa1ad; - u32 sfa2ad; - u32 sfb1ad; - u32 sfb2ad; - u32 rsvd7[28]; - u32 rbdr[32]; - u32 rsvd8[32]; - u32 lutkey; - u32 lckcr; - u32 rsvd9[2]; - u32 lut[64]; -}; - -#define QSPI_IPCR_SEQID_SHIFT 24 -#define QSPI_IPCR_SEQID_MASK (0xf << QSPI_IPCR_SEQID_SHIFT) - -#define QSPI_MCR_END_CFD_SHIFT 2 -#define QSPI_MCR_END_CFD_MASK (3 << QSPI_MCR_END_CFD_SHIFT) -#ifdef CONFIG_SYS_FSL_QSPI_AHB -/* AHB needs 64bit operation */ -#define QSPI_MCR_END_CFD_LE (3 << QSPI_MCR_END_CFD_SHIFT) -#else -#define QSPI_MCR_END_CFD_LE (1 << QSPI_MCR_END_CFD_SHIFT) -#endif -#define QSPI_MCR_DDR_EN_SHIFT 7 -#define QSPI_MCR_DDR_EN_MASK (1 << QSPI_MCR_DDR_EN_SHIFT) -#define QSPI_MCR_CLR_RXF_SHIFT 10 -#define QSPI_MCR_CLR_RXF_MASK (1 << QSPI_MCR_CLR_RXF_SHIFT) -#define QSPI_MCR_CLR_TXF_SHIFT 11 -#define QSPI_MCR_CLR_TXF_MASK (1 << QSPI_MCR_CLR_TXF_SHIFT) -#define QSPI_MCR_MDIS_SHIFT 14 -#define QSPI_MCR_MDIS_MASK (1 << QSPI_MCR_MDIS_SHIFT) -#define QSPI_MCR_RESERVED_SHIFT 16 -#define QSPI_MCR_RESERVED_MASK (0xf << QSPI_MCR_RESERVED_SHIFT) -#define QSPI_MCR_SWRSTHD_SHIFT 1 -#define QSPI_MCR_SWRSTHD_MASK (1 << QSPI_MCR_SWRSTHD_SHIFT) -#define QSPI_MCR_SWRSTSD_SHIFT 0 -#define QSPI_MCR_SWRSTSD_MASK (1 << QSPI_MCR_SWRSTSD_SHIFT) - -#define QSPI_SMPR_HSENA_SHIFT 0 -#define QSPI_SMPR_HSENA_MASK (1 << QSPI_SMPR_HSENA_SHIFT) -#define QSPI_SMPR_FSPHS_SHIFT 5 -#define QSPI_SMPR_FSPHS_MASK (1 << QSPI_SMPR_FSPHS_SHIFT) -#define QSPI_SMPR_FSDLY_SHIFT 6 -#define QSPI_SMPR_FSDLY_MASK (1 << QSPI_SMPR_FSDLY_SHIFT) -#define QSPI_SMPR_DDRSMP_SHIFT 16 -#define QSPI_SMPR_DDRSMP_MASK (7 << QSPI_SMPR_DDRSMP_SHIFT) - -#define QSPI_BUFXCR_INVALID_MSTRID 0xe -#define QSPI_BUF3CR_ALLMST_SHIFT 31 -#define QSPI_BUF3CR_ALLMST_MASK (1 << QSPI_BUF3CR_ALLMST_SHIFT) -#define QSPI_BUF3CR_ADATSZ_SHIFT 8 -#define QSPI_BUF3CR_ADATSZ_MASK (0xFF << QSPI_BUF3CR_ADATSZ_SHIFT) - -#define QSPI_BFGENCR_SEQID_SHIFT 12 -#define QSPI_BFGENCR_SEQID_MASK (0xf << QSPI_BFGENCR_SEQID_SHIFT) -#define QSPI_BFGENCR_PAR_EN_SHIFT 16 -#define QSPI_BFGENCR_PAR_EN_MASK (1 << QSPI_BFGENCR_PAR_EN_SHIFT) - -#define QSPI_RBSR_RDBFL_SHIFT 8 -#define QSPI_RBSR_RDBFL_MASK (0x3f << QSPI_RBSR_RDBFL_SHIFT) - -#define QSPI_RBCT_RXBRD_SHIFT 8 -#define QSPI_RBCT_RXBRD_USEIPS (1 << QSPI_RBCT_RXBRD_SHIFT) - -#define QSPI_SR_AHB_ACC_SHIFT 2 -#define QSPI_SR_AHB_ACC_MASK (1 << QSPI_SR_AHB_ACC_SHIFT) -#define QSPI_SR_IP_ACC_SHIFT 1 -#define QSPI_SR_IP_ACC_MASK (1 << QSPI_SR_IP_ACC_SHIFT) -#define QSPI_SR_BUSY_SHIFT 0 -#define QSPI_SR_BUSY_MASK (1 << QSPI_SR_BUSY_SHIFT) - -#define QSPI_LCKCR_LOCK 0x1 -#define QSPI_LCKCR_UNLOCK 0x2 - -#define LUT_KEY_VALUE 0x5af05af0 - -#define OPRND0_SHIFT 0 -#define OPRND0(x) ((x) << OPRND0_SHIFT) -#define PAD0_SHIFT 8 -#define PAD0(x) ((x) << PAD0_SHIFT) -#define INSTR0_SHIFT 10 -#define INSTR0(x) ((x) << INSTR0_SHIFT) -#define OPRND1_SHIFT 16 -#define OPRND1(x) ((x) << OPRND1_SHIFT) -#define PAD1_SHIFT 24 -#define PAD1(x) ((x) << PAD1_SHIFT) -#define INSTR1_SHIFT 26 -#define INSTR1(x) ((x) << INSTR1_SHIFT) - -#define LUT_CMD 1 -#define LUT_ADDR 2 -#define LUT_DUMMY 3 -#define LUT_READ 7 -#define LUT_WRITE 8 - -#define LUT_PAD1 0 -#define LUT_PAD2 1 -#define LUT_PAD4 2 - -#define ADDR24BIT 0x18 -#define ADDR32BIT 0x20 - -#endif /* _FSL_QSPI_H_ */ From 7ddea756540b5adddfde3b890fa46a40c649e68f Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Fri, 13 Mar 2020 01:06:38 +0100 Subject: [PATCH 007/237] spi: use is_power_of_2 instead of hweight32 in spi_nor_write() hweight32 is a somewhat expensive way to check for power-of-2. Use the is_power_of_2 helper, which does the standard and cheap idiom foo&(foo-1)==0. add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-96 (-96) Function old new delta spi_nor_write 388 292 -96 Signed-off-by: Rasmus Villemoes Acked-by: Vignesh Raghavendra Acked-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 7b6ad495ace..3bf8ddfb9df 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1246,11 +1246,8 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, * If page_size is a power of two, the offset can be quickly * calculated with an AND operation. On the other cases we * need to do a modulus operation (more expensive). - * Power of two numbers have only one bit set and we can use - * the instruction hweight32 to detect if we need to do a - * modulus (do_div()) or not. */ - if (hweight32(nor->page_size) == 1) { + if (is_power_of_2(nor->page_size)) { page_offset = addr & (nor->page_size - 1); } else { u64 aux = addr; From 0a9c2874978a8468c92ed0dafe7a0cf239dc6a35 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Mon, 24 Feb 2020 12:40:51 +0530 Subject: [PATCH 008/237] spi: cadence-qspi: Move ref clock calculation to probe "assigned-clock-parents" and "assigned-clock-rates" DT properties take effect only after ofdata_to_platdata() when clk_set_defaults() is called in device_probe(). Therefore clk get rate() would return a wrong value in ofdata_to_platdata() when compared with probe. Hence it needs to be moved to probe. Tested on u-boot-ti/next. Signed-off-by: Pratyush Yadav Acked-by: Vignesh Raghavendra Acked-by: Simon Goldschmidt Reviewed-by: Jagan Teki --- drivers/spi/cadence_qspi.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 83b114ffe74..994a5948f1e 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -166,11 +166,28 @@ static int cadence_spi_probe(struct udevice *bus) { struct cadence_spi_platdata *plat = bus->platdata; struct cadence_spi_priv *priv = dev_get_priv(bus); + struct clk clk; int ret; priv->regbase = plat->regbase; priv->ahbbase = plat->ahbbase; + if (plat->ref_clk_hz == 0) { + ret = clk_get_by_index(bus, 0, &clk); + if (ret) { +#ifdef CONFIG_CQSPI_REF_CLK + plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK; +#else + return ret; +#endif + } else { + plat->ref_clk_hz = clk_get_rate(&clk); + clk_free(&clk); + if (IS_ERR_VALUE(plat->ref_clk_hz)) + return plat->ref_clk_hz; + } + } + ret = reset_get_bulk(bus, &priv->resets); if (ret) dev_warn(bus, "Can't get reset: %d\n", ret); @@ -268,8 +285,6 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) { struct cadence_spi_platdata *plat = bus->platdata; ofnode subnode; - struct clk clk; - int ret; plat->regbase = (void *)devfdt_get_addr_index(bus, 0); plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1, @@ -305,20 +320,6 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20); plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20); - ret = clk_get_by_index(bus, 0, &clk); - if (ret) { -#ifdef CONFIG_CQSPI_REF_CLK - plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK; -#else - return ret; -#endif - } else { - plat->ref_clk_hz = clk_get_rate(&clk); - clk_free(&clk); - if (IS_ERR_VALUE(plat->ref_clk_hz)) - return plat->ref_clk_hz; - } - debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", __func__, plat->regbase, plat->ahbbase, plat->max_hz, plat->page_size); From cae3c7cc581c441d822e18c0d14dd3c230beef80 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Sat, 14 Mar 2020 18:23:54 +0530 Subject: [PATCH 009/237] mtd: spi-nor-ids: Enable SPI_NOR_OCTAL_READ flag for mt35xu* Commit 658df8bd9464 ("mtd: spi-nor-core: Add octal mode support") enables octal mode(1-1-8) support in spi-nor framework. mt35xu512aba and mt35xu02g supports SINGLE and OCTAL I/O. Hence, enable SPI_NOR_OCTAL_READ flag for these flashes. Signed-off-by: Kuldeep Singh Reviewed-by: Vignesh Raghavendra Reviewed-by: Priyanka Jain Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-ids.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index abdf560e020..30b9fa8110e 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -183,8 +183,8 @@ const struct flash_info spi_nor_ids[] = { { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, - { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_4B_OPCODES) }, - { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_4B_OPCODES) }, + { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ /* Spansion/Cypress -- single (large) sector size only, at least From 6f3b1f4a1dea5b733b03445c2a3eff2e4a47eafb Mon Sep 17 00:00:00 2001 From: Bacem Daassi Date: Fri, 27 Mar 2020 19:58:14 +0100 Subject: [PATCH 010/237] mtd: spi-nor: Enable dual and quad read for s25fl256s0 The s25fl256s0 supports dual and quad read like s25fl256s1. Enable it by adding SPI_NOR_DUAL_READ and SPI_NOR_QUAD_READ flags to the flash_info entry. Tested on real silicon and confirmed to be working. Signed-off-by: Bacem Daassi Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-ids.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 30b9fa8110e..218385f50a1 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -192,7 +192,7 @@ const struct flash_info spi_nor_ids[] = { */ { INFO("s25sl032p", 0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) }, + { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO6("s25fl512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, From 89127104848cea38bac5d40e3d6973fc203e2df6 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 3 Mar 2020 20:25:40 +0100 Subject: [PATCH 011/237] mtd: spi-nand: Import Toshiba SPI-NAND support Linux has good support for Toshiba SPI-NAND, so lets import it. Signed-off-by: Robert Marko Tested-by: Luka Kovacic Cc: Luka Perkov Reviewed-by: Jagan Teki --- drivers/mtd/nand/spi/Makefile | 2 +- drivers/mtd/nand/spi/core.c | 1 + drivers/mtd/nand/spi/toshiba.c | 191 +++++++++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 1 + 4 files changed, 194 insertions(+), 1 deletion(-) create mode 100644 drivers/mtd/nand/spi/toshiba.c diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile index dd6bacae34d..6c65b187e86 100644 --- a/drivers/mtd/nand/spi/Makefile +++ b/drivers/mtd/nand/spi/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 -spinand-objs := core.o gigadevice.o macronix.o micron.o winbond.o +spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o obj-$(CONFIG_MTD_SPI_NAND) += spinand.o diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index cd624ec6ae6..397dfa41789 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -835,6 +835,7 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = { &gigadevice_spinand_manufacturer, ¯onix_spinand_manufacturer, µn_spinand_manufacturer, + &toshiba_spinand_manufacturer, &winbond_spinand_manufacturer, }; diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c new file mode 100644 index 00000000000..571104a5d94 --- /dev/null +++ b/drivers/mtd/nand/spi/toshiba.c @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 exceet electronics GmbH + * Copyright (c) 2018 Kontron Electronics GmbH + * + * Author: Frieder Schrempf + */ + +#ifndef __UBOOT__ +#include +#include +#include +#endif +#include + +#define SPINAND_MFR_TOSHIBA 0x98 +#define TOSH_STATUS_ECC_HAS_BITFLIPS_T (3 << 4) + +static SPINAND_OP_VARIANTS(read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); + +static SPINAND_OP_VARIANTS(write_cache_variants, + SPINAND_PROG_LOAD(true, 0, NULL, 0)); + +static SPINAND_OP_VARIANTS(update_cache_variants, + SPINAND_PROG_LOAD(false, 0, NULL, 0)); + +static int tc58cxgxsx_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section > 0) + return -ERANGE; + + region->offset = mtd->oobsize / 2; + region->length = mtd->oobsize / 2; + + return 0; +} + +static int tc58cxgxsx_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section > 0) + return -ERANGE; + + /* 2 bytes reserved for BBM */ + region->offset = 2; + region->length = (mtd->oobsize / 2) - 2; + + return 0; +} + +static const struct mtd_ooblayout_ops tc58cxgxsx_ooblayout = { + .ecc = tc58cxgxsx_ooblayout_ecc, + .rfree = tc58cxgxsx_ooblayout_free, +}; + +static int tc58cxgxsx_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ + struct nand_device *nand = spinand_to_nand(spinand); + u8 mbf = 0; + struct spi_mem_op op = SPINAND_GET_FEATURE_OP(0x30, &mbf); + + switch (status & STATUS_ECC_MASK) { + case STATUS_ECC_NO_BITFLIPS: + return 0; + + case STATUS_ECC_UNCOR_ERROR: + return -EBADMSG; + + case STATUS_ECC_HAS_BITFLIPS: + case TOSH_STATUS_ECC_HAS_BITFLIPS_T: + /* + * Let's try to retrieve the real maximum number of bitflips + * in order to avoid forcing the wear-leveling layer to move + * data around if it's not necessary. + */ + if (spi_mem_exec_op(spinand->slave, &op)) + return nand->eccreq.strength; + + mbf >>= 4; + + if (WARN_ON(mbf > nand->eccreq.strength || !mbf)) + return nand->eccreq.strength; + + return mbf; + + default: + break; + } + + return -EINVAL; +} + +static const struct spinand_info toshiba_spinand_table[] = { + /* 3.3V 1Gb */ + SPINAND_INFO("TC58CVG0S3", 0xC2, + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, + tc58cxgxsx_ecc_get_status)), + /* 3.3V 2Gb */ + SPINAND_INFO("TC58CVG1S3", 0xCB, + NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, + tc58cxgxsx_ecc_get_status)), + /* 3.3V 4Gb */ + SPINAND_INFO("TC58CVG2S0", 0xCD, + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, + tc58cxgxsx_ecc_get_status)), + /* 1.8V 1Gb */ + SPINAND_INFO("TC58CYG0S3", 0xB2, + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, + tc58cxgxsx_ecc_get_status)), + /* 1.8V 2Gb */ + SPINAND_INFO("TC58CYG1S3", 0xBB, + NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, + tc58cxgxsx_ecc_get_status)), + /* 1.8V 4Gb */ + SPINAND_INFO("TC58CYG2S0", 0xBD, + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, + tc58cxgxsx_ecc_get_status)), +}; + +static int toshiba_spinand_detect(struct spinand_device *spinand) +{ + u8 *id = spinand->id.data; + int ret; + + /* + * Toshiba SPI NAND read ID needs a dummy byte, + * so the first byte in id is garbage. + */ + if (id[1] != SPINAND_MFR_TOSHIBA) + return 0; + + ret = spinand_match_and_init(spinand, toshiba_spinand_table, + ARRAY_SIZE(toshiba_spinand_table), + id[2]); + if (ret) + return ret; + + return 1; +} + +static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = { + .detect = toshiba_spinand_detect, +}; + +const struct spinand_manufacturer toshiba_spinand_manufacturer = { + .id = SPINAND_MFR_TOSHIBA, + .name = "Toshiba", + .ops = &toshiba_spinand_manuf_ops, +}; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index be01e1e82e5..83eafb184e6 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -204,6 +204,7 @@ struct spinand_manufacturer { extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; extern const struct spinand_manufacturer macronix_spinand_manufacturer; extern const struct spinand_manufacturer micron_spinand_manufacturer; +extern const struct spinand_manufacturer toshiba_spinand_manufacturer; extern const struct spinand_manufacturer winbond_spinand_manufacturer; /** From f5fba6e85bf15ae43d73f66730ebf32918445be4 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 3 Mar 2020 20:25:42 +0100 Subject: [PATCH 012/237] mtd: nand: spi: add support for Toshiba TC58CVG2S0HRAIJ Toshiba recently launched new revisions of their serial SLC NAND series. TC58CVG2S0HRAIJ is a refresh of previous series with minor improvements. Basic parameters are same so lets add support for this new revision. Datasheet: https://business.kioxia.com/info/docget.jsp?did=58601&prodName=TC58CVG2S0HRAIJ Signed-off-by: Robert Marko Tested-by: Luka Kovacic Cc: Luka Perkov Reviewed-by: Jagan Teki --- drivers/mtd/nand/spi/toshiba.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c index 571104a5d94..77c25398fcc 100644 --- a/drivers/mtd/nand/spi/toshiba.c +++ b/drivers/mtd/nand/spi/toshiba.c @@ -127,6 +127,16 @@ static const struct spinand_info toshiba_spinand_table[] = { 0, SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, tc58cxgxsx_ecc_get_status)), + /* 3.3V 4Gb */ + SPINAND_INFO("TC58CVG2S0", 0xED, + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, + tc58cxgxsx_ecc_get_status)), /* 1.8V 1Gb */ SPINAND_INFO("TC58CYG0S3", 0xB2, NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), From 790c1699b2c0ca40809c43b3ddb9fc4a46939d18 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 20 Mar 2020 09:35:31 +0000 Subject: [PATCH 013/237] spi: spi-mem: Add SPI_MEM_NO_DATA to the spi_mem_data_dir enum Commit: 0ebb261a0b2d ("spi: spi-mem: Add SPI_MEM_NO_DATA to the spi_mem_data_dir enum") in linux. When defining spi_mem_op templates we don't necessarily know the size that will be passed when the template is actually used, and basing the supports_op() check on op->data.nbytes to know whether there will be data transferred for a specific operation is not possible. Add SPI_MEM_NO_DATA to the spi_mem_data_dir enum so that we can base our checks on op->data.dir instead of op->data.nbytes. This also fixes a bug identified with the atmel-quaspi driver. The spi-nor core, when erasing sectors, fills the spi_mem_op template using SPI_MEM_OP_NO_DATA, which initializes all the data members with value zero. This is wrong because data.dir is treated as SPI_MEM_DATA_IN, which translates in our driver to read accesses for erases (RICR), while the controller expects write accesses (WICR). Signed-off-by: Tudor Ambarus Reviewed-by: Jagan Teki --- drivers/spi/spi-mem.c | 2 +- include/spi-mem.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index e900c997bd7..ffbe20c5b1e 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -153,7 +153,7 @@ bool spi_mem_default_supports_op(struct spi_slave *slave, spi_check_buswidth_req(slave, op->dummy.buswidth, true)) return false; - if (op->data.nbytes && + if (op->data.dir != SPI_MEM_NO_DATA && spi_check_buswidth_req(slave, op->data.buswidth, op->data.dir == SPI_MEM_DATA_OUT)) return false; diff --git a/include/spi-mem.h b/include/spi-mem.h index 36814efa861..893f7bd7337 100644 --- a/include/spi-mem.h +++ b/include/spi-mem.h @@ -60,10 +60,12 @@ /** * enum spi_mem_data_dir - describes the direction of a SPI memory data * transfer from the controller perspective + * @SPI_MEM_NO_DATA: no data transferred * @SPI_MEM_DATA_IN: data coming from the SPI memory * @SPI_MEM_DATA_OUT: data sent the SPI memory */ enum spi_mem_data_dir { + SPI_MEM_NO_DATA, SPI_MEM_DATA_IN, SPI_MEM_DATA_OUT, }; From f76b9388c6067b4a1705e7f8524423dd20622762 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 10 Apr 2020 23:56:29 +0530 Subject: [PATCH 014/237] environment: distro: Add SF distro command Add distro boot command support for SPI flash (SF). This distro boot will read the boot script at specific location at the flash and start sourcing the same. This file need to include on required include/config file. Cc: Tom Rini Signed-off-by: Jagan Teki Reviewed-by: Tom Rini --- include/environment/distro/sf.h | 41 +++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 include/environment/distro/sf.h diff --git a/include/environment/distro/sf.h b/include/environment/distro/sf.h new file mode 100644 index 00000000000..e793be06c6f --- /dev/null +++ b/include/environment/distro/sf.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Amarula Solutions(India) + * + * SF distro configurations. + */ + +#ifndef __DISTRO_SF_CONFIG_H +#define __DISTRO_SF_CONFIG_H + +#if CONFIG_IS_ENABLED(CMD_SF) +#define BOOTENV_SHARED_SF(devtypel) \ + #devtypel "_boot=" \ + "if " #devtypel " probe ${busnum}; then " \ + "devtype=" #devtypel "; " \ + "run scan_sf_for_scripts; " \ + "fi\0" +#define BOOTENV_DEV_SF(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "busnum=" #instance "; " \ + "run " #devtypel "_boot\0" +#define BOOTENV_DEV_NAME_SF(devtypeu, devtypel, instance) \ + #devtypel #instance " " +#else +#define BOOTENV_SHARED_SF(devtypel) +#define BOOTENV_DEV_SF \ + BOOT_TARGET_DEVICES_references_SF_without_CONFIG_CMD_SF +#define BOOTENV_DEV_NAME_SF \ + BOOT_TARGET_DEVICES_references_SF_without_CONFIG_CMD_SF + +#endif /* CONFIG_CMD_SF */ + +#define BOOTENV_SF \ + BOOTENV_SHARED_SF(sf) \ + "scan_sf_for_scripts=" \ + "${devtype} read ${scriptaddr} " \ + "${script_offset_f} ${script_size_f}; " \ + "source ${scriptaddr}; " \ + "echo SCRIPT FAILED: continuing...\0" + +#endif /* __DISTRO_SF_CONFIG_H */ From d2c19b740c48c662fe23d02ac8d6514895d8c205 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 10 Apr 2020 23:56:30 +0530 Subject: [PATCH 015/237] rk3399: Add boot flash script offset, size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Most of the SPI flash devices in rockchip (rk3399) are 16MiB size. So, let's use the script offset at the end of 8K.  This way it cannot overlap any offsets being used by software components in flash layout. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- include/configs/rk3399_common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 89a8a44bbe2..01a9174bd2c 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -48,6 +48,8 @@ #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ + "script_offset_f=0xffe000\0" \ + "script_size_f=0x2000\0" \ "pxefile_addr_r=0x00600000\0" \ "fdt_addr_r=0x01f00000\0" \ "kernel_addr_r=0x02080000\0" \ From 91e858dcf667e58f1c814cfcd32d6d8d811b03a7 Mon Sep 17 00:00:00 2001 From: Lin Jinhan Date: Tue, 31 Mar 2020 17:39:57 +0800 Subject: [PATCH 016/237] arm: dts: rockchip: rk3399: add and enable rng node Add rng node in rk3399-u-boot.dtsi and enable it in rk3399-evb-u-boot.dtsi. Signed-off-by: Lin Jinhan Tested-by: Peter Robinson Reviewed-by: Sughosh Ganu Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-evb-u-boot.dtsi | 4 ++++ arch/arm/dts/rk3399-u-boot.dtsi | 6 ++++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi index ccb33d34d12..f68a56fdd0b 100644 --- a/arch/arm/dts/rk3399-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi @@ -11,3 +11,7 @@ u-boot,spl-boot-order = &sdhci, &sdmmc; }; }; + +&rng { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 8b857ccfc79..757b8c10a24 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -25,6 +25,12 @@ clock-names = "pclk_ddr_mon"; }; + rng: rng@ff8b8000 { + compatible = "rockchip,cryptov1-rng"; + reg = <0x0 0xff8b8000 0x0 0x1000>; + status = "disabled"; + }; + dmc: dmc { u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-dmc"; From fb9230c53b01666503010f1d59effc64b0e7842e Mon Sep 17 00:00:00 2001 From: Lin Jinhan Date: Tue, 31 Mar 2020 17:39:58 +0800 Subject: [PATCH 017/237] arm: dts: rockchip: px30: add and enable rng node Add enable rng node in px30-evb-u-boot.dtsi. Signed-off-by: Lin Jinhan Reviewed-by: Kever Yang --- arch/arm/dts/px30-evb-u-boot.dtsi | 4 ++++ arch/arm/dts/px30-u-boot.dtsi | 6 ++++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm/dts/px30-evb-u-boot.dtsi b/arch/arm/dts/px30-evb-u-boot.dtsi index aea9f4d6e51..61b1433af91 100644 --- a/arch/arm/dts/px30-evb-u-boot.dtsi +++ b/arch/arm/dts/px30-evb-u-boot.dtsi @@ -4,3 +4,7 @@ */ #include "px30-u-boot.dtsi" + +&rng { + status = "okay"; +}; diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi index bb782b4e2df..029c8fbd8d9 100644 --- a/arch/arm/dts/px30-u-boot.dtsi +++ b/arch/arm/dts/px30-u-boot.dtsi @@ -12,6 +12,12 @@ chosen { u-boot,spl-boot-order = &emmc, &sdmmc; }; + + rng: rng@ff0b0000 { + compatible = "rockchip,cryptov2-rng"; + reg = <0x0 0xff0b0000 0x0 0x4000>; + status = "disabled"; + }; }; &dmc { From 6e7353e3d9929d34c3fc1422503923aedbf6f972 Mon Sep 17 00:00:00 2001 From: Lin Jinhan Date: Tue, 31 Mar 2020 17:39:59 +0800 Subject: [PATCH 018/237] rockchip: rng: Add a driver for random number generator(rng) device Add a driver for the rng device found on rockchip platforms. Support rng module of crypto v1 and crypto v2. Signed-off-by: Lin Jinhan Tested-by: Peter Robinson Reviewed-by: Kever Yang --- drivers/rng/Kconfig | 8 ++ drivers/rng/Makefile | 1 + drivers/rng/rockchip_rng.c | 224 +++++++++++++++++++++++++++++++++++++ 3 files changed, 233 insertions(+) create mode 100644 drivers/rng/rockchip_rng.c diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig index edb6152bb9d..e4b22d79ebc 100644 --- a/drivers/rng/Kconfig +++ b/drivers/rng/Kconfig @@ -31,4 +31,12 @@ config RNG_STM32MP1 help Enable STM32MP1 rng driver. +config RNG_ROCKCHIP + bool "Enable random number generator for rockchip crypto rng" + depends on ARCH_ROCKCHIP && DM_RNG + default n + help + Enable random number generator for rockchip.This driver is + support rng module of crypto v1 and crypto v2. + endif diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile index 6a8a66779b5..44a00039173 100644 --- a/drivers/rng/Makefile +++ b/drivers/rng/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_DM_RNG) += rng-uclass.o obj-$(CONFIG_RNG_MESON) += meson-rng.o obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o +obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o diff --git a/drivers/rng/rockchip_rng.c b/drivers/rng/rockchip_rng.c new file mode 100644 index 00000000000..47fb140077d --- /dev/null +++ b/drivers/rng/rockchip_rng.c @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + */ +#include +#include +#include +#include +#include +#include +#include + +#define RK_HW_RNG_MAX 32 + +#define _SBF(s, v) ((v) << (s)) + +/* start of CRYPTO V1 register define */ +#define CRYPTO_V1_CTRL 0x0008 +#define CRYPTO_V1_RNG_START BIT(8) +#define CRYPTO_V1_RNG_FLUSH BIT(9) + +#define CRYPTO_V1_TRNG_CTRL 0x0200 +#define CRYPTO_V1_OSC_ENABLE BIT(16) +#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x) + +#define CRYPTO_V1_TRNG_DOUT_0 0x0204 +/* end of CRYPTO V1 register define */ + +/* start of CRYPTO V2 register define */ +#define CRYPTO_V2_RNG_CTL 0x0400 +#define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00) +#define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01) +#define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02) +#define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03) +#define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00) +#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01) +#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02) +#define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03) +#define CRYPTO_V2_RNG_ENABLE BIT(1) +#define CRYPTO_V2_RNG_START BIT(0) +#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0404 +#define CRYPTO_V2_RNG_DOUT_0 0x0410 +/* end of CRYPTO V2 register define */ + +#define RK_RNG_TIME_OUT 50000 /* max 50ms */ + +struct rk_rng_soc_data { + int (*rk_rng_read)(struct udevice *dev, void *data, size_t len); +}; + +struct rk_rng_platdata { + fdt_addr_t base; + struct rk_rng_soc_data *soc_data; +}; + +static int rk_rng_read_regs(fdt_addr_t addr, void *buf, size_t size) +{ + u32 count = RK_HW_RNG_MAX / sizeof(u32); + u32 reg, tmp_len; + + if (size > RK_HW_RNG_MAX) + return -EINVAL; + + while (size && count) { + reg = readl(addr); + tmp_len = min(size, sizeof(u32)); + memcpy(buf, ®, tmp_len); + addr += sizeof(u32); + buf += tmp_len; + size -= tmp_len; + count--; + } + + return 0; +} + +static int rk_v1_rng_read(struct udevice *dev, void *data, size_t len) +{ + struct rk_rng_platdata *pdata = dev_get_priv(dev); + u32 reg = 0; + int retval; + + if (len > RK_HW_RNG_MAX) + return -EINVAL; + + /* enable osc_ring to get entropy, sample period is set as 100 */ + writel(CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100), + pdata->base + CRYPTO_V1_TRNG_CTRL); + + rk_clrsetreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START, + CRYPTO_V1_RNG_START); + + retval = readl_poll_timeout(pdata->base + CRYPTO_V1_CTRL, reg, + !(reg & CRYPTO_V1_RNG_START), + RK_RNG_TIME_OUT); + if (retval) + goto exit; + + rk_rng_read_regs(pdata->base + CRYPTO_V1_TRNG_DOUT_0, data, len); + +exit: + /* close TRNG */ + rk_clrreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START); + + return 0; +} + +static int rk_v2_rng_read(struct udevice *dev, void *data, size_t len) +{ + struct rk_rng_platdata *pdata = dev_get_priv(dev); + u32 reg = 0; + int retval; + + if (len > RK_HW_RNG_MAX) + return -EINVAL; + + /* enable osc_ring to get entropy, sample period is set as 100 */ + writel(100, pdata->base + CRYPTO_V2_RNG_SAMPLE_CNT); + + reg |= CRYPTO_V2_RNG_256_BIT_LEN; + reg |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0; + reg |= CRYPTO_V2_RNG_ENABLE; + reg |= CRYPTO_V2_RNG_START; + + rk_clrsetreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff, reg); + + retval = readl_poll_timeout(pdata->base + CRYPTO_V2_RNG_CTL, reg, + !(reg & CRYPTO_V2_RNG_START), + RK_RNG_TIME_OUT); + if (retval) + goto exit; + + rk_rng_read_regs(pdata->base + CRYPTO_V2_RNG_DOUT_0, data, len); + +exit: + /* close TRNG */ + rk_clrreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff); + + return retval; +} + +static int rockchip_rng_read(struct udevice *dev, void *data, size_t len) +{ + unsigned char *buf = data; + unsigned int i; + int ret = -EIO; + + struct rk_rng_platdata *pdata = dev_get_priv(dev); + + if (!len) + return 0; + + if (!pdata->soc_data || !pdata->soc_data->rk_rng_read) + return -EINVAL; + + for (i = 0; i < len / RK_HW_RNG_MAX; i++, buf += RK_HW_RNG_MAX) { + ret = pdata->soc_data->rk_rng_read(dev, buf, RK_HW_RNG_MAX); + if (ret) + goto exit; + } + + if (len % RK_HW_RNG_MAX) + ret = pdata->soc_data->rk_rng_read(dev, buf, + len % RK_HW_RNG_MAX); + +exit: + return ret; +} + +static int rockchip_rng_ofdata_to_platdata(struct udevice *dev) +{ + struct rk_rng_platdata *pdata = dev_get_priv(dev); + + memset(pdata, 0x00, sizeof(*pdata)); + + pdata->base = (fdt_addr_t)dev_read_addr_ptr(dev); + if (!pdata->base) + return -ENOMEM; + + return 0; +} + +static int rockchip_rng_probe(struct udevice *dev) +{ + struct rk_rng_platdata *pdata = dev_get_priv(dev); + + pdata->soc_data = (struct rk_rng_soc_data *)dev_get_driver_data(dev); + + return 0; +} + +static const struct rk_rng_soc_data rk_rng_v1_soc_data = { + .rk_rng_read = rk_v1_rng_read, +}; + +static const struct rk_rng_soc_data rk_rng_v2_soc_data = { + .rk_rng_read = rk_v2_rng_read, +}; + +static const struct dm_rng_ops rockchip_rng_ops = { + .read = rockchip_rng_read, +}; + +static const struct udevice_id rockchip_rng_match[] = { + { + .compatible = "rockchip,cryptov1-rng", + .data = (ulong)&rk_rng_v1_soc_data, + }, + { + .compatible = "rockchip,cryptov2-rng", + .data = (ulong)&rk_rng_v2_soc_data, + }, + {}, +}; + +U_BOOT_DRIVER(rockchip_rng) = { + .name = "rockchip-rng", + .id = UCLASS_RNG, + .of_match = rockchip_rng_match, + .ops = &rockchip_rng_ops, + .probe = rockchip_rng_probe, + .ofdata_to_platdata = rockchip_rng_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct rk_rng_platdata), +}; From df35df3e8d6ccb1e4179fcab440f52204218524e Mon Sep 17 00:00:00 2001 From: Lin Jinhan Date: Tue, 31 Mar 2020 17:40:00 +0800 Subject: [PATCH 019/237] rockchip: rk3399: Enable CONFIG_RNG_ROCKCHIP CONFIG_RNG_ROCKCHIP/CONFIG_DM_RNG is enabled. Signed-off-by: Lin Jinhan Reviewed-by: Kever Yang --- configs/evb-rk3399_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 3f74be3b3c4..7f14e18b1b3 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -39,6 +39,8 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y From d768a064a4368a458fe8320e0a45d198acd4475e Mon Sep 17 00:00:00 2001 From: Lin Jinhan Date: Tue, 31 Mar 2020 17:40:01 +0800 Subject: [PATCH 020/237] rockchip: px30: Enable CONFIG_RNG_ROCKCHIP CONFIG_RNG_ROCKCHIP/CONFIG_DM_RNG is enabled. Signed-off-by: Lin Jinhan Reviewed-by: Kever Yang --- configs/evb-px30_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index b5ba75cc6ef..d2cf13e54a5 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -85,6 +85,8 @@ CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y CONFIG_ROCKCHIP_SDRAM_COMMON=y CONFIG_DM_RESET=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y From 79011f358f6aab88cc8334d26d11b0ceddc176e9 Mon Sep 17 00:00:00 2001 From: Suniel Mahesh Date: Thu, 2 Apr 2020 18:22:30 +0530 Subject: [PATCH 021/237] rockchip: board: roc-pc-rk3399: Remove support for push button In case of a power interruption, human intervention is required which is not desirable if the device is installed at a remote location. Drop yellow LED as it is not much of use. Keep red LED(diy-led) as it is, to indicate board in full power mode. Signed-off-by: Suniel Mahesh Reviewed-by: Kever Yang --- board/firefly/roc-pc-rk3399/roc-pc-rk3399.c | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c index de9185a7cee..0fe1914c0fc 100644 --- a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c +++ b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c @@ -10,7 +10,6 @@ #include #include #include -#include #ifndef CONFIG_SPL_BUILD int board_early_init_f(void) @@ -34,26 +33,13 @@ out: #if defined(CONFIG_TPL_BUILD) -#define PMUGRF_BASE 0xff320000 #define GPIO0_BASE 0xff720000 int board_early_init_f(void) { struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE; - struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; - /** - * 1. Glow yellow LED, termed as low power - * 2. Poll for on board power key press - * 3. Once 2 done, off yellow and glow red LED, termed as full power - * 4. Continue booting... - */ - spl_gpio_output(gpio0, GPIO(BANK_A, 2), 1); - - spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_A, 5), GPIO_PULL_NORMAL); - while (readl(&gpio0->ext_port) & 0x20); - - spl_gpio_output(gpio0, GPIO(BANK_A, 2), 0); + /* Turn on red LED, indicating full power mode */ spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1); return 0; From f263b860acf82de85e4d61ac67b1e4f62efcf1cc Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 10 Apr 2020 23:56:31 +0530 Subject: [PATCH 022/237] rk3399: Enable SF distro bootcmd Enable SPI flash(SF) distro boot command in rk3399. This distro boot will read the boot script at specific location at the flash and start sourcing the same. Included the SF device at the last of the target devices list since all the rest of the devices on the list have more possibility to boot the distribution due to the size of the SPI flash is concern. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- include/configs/rk3399_common.h | 1 + include/configs/rockchip-common.h | 15 +++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 01a9174bd2c..f0ae6e67a71 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -60,6 +60,7 @@ #endif #include +#include #define CONFIG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index b55e09a9ca1..bf8c60d6ddd 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -41,11 +41,26 @@ #define BOOT_TARGET_DHCP(func) #endif +#if CONFIG_IS_ENABLED(CMD_SF) + #define BOOT_TARGET_SF(func) func(SF, sf, 0) +#else + #define BOOT_TARGET_SF(func) +#endif + +#ifdef CONFIG_ROCKCHIP_RK3399 +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_MMC(func) \ + BOOT_TARGET_USB(func) \ + BOOT_TARGET_PXE(func) \ + BOOT_TARGET_DHCP(func) \ + BOOT_TARGET_SF(func) +#else #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_MMC(func) \ BOOT_TARGET_USB(func) \ BOOT_TARGET_PXE(func) \ BOOT_TARGET_DHCP(func) +#endif #ifdef CONFIG_ARM64 #define ROOT_UUID "B921B045-1DF0-41C3-AF44-4C6F280D3FAE;\0" From e67cd814ee2d00e1b8651bc1cd889ac6f45ed26b Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 20 Apr 2020 16:03:46 +0530 Subject: [PATCH 023/237] spi: sifive: Tidy up dm_spi_slave_platdata variable Usually variable name slave is used for spi_slave structure and slave_plat for the dm_spi_slave_platdata. Let's follow this meaningful notation by replacing slave with slave_plat for dm_spi_slave_platdata structure. Signed-off-by: Jagan Teki Reviewed-by: Bin Meng --- drivers/spi/spi-sifive.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c index 969bd4b75cb..8f5efb51a37 100644 --- a/drivers/spi/spi-sifive.c +++ b/drivers/spi/spi-sifive.c @@ -95,25 +95,25 @@ struct sifive_spi { }; static void sifive_spi_prep_device(struct sifive_spi *spi, - struct dm_spi_slave_platdata *slave) + struct dm_spi_slave_platdata *slave_plat) { /* Update the chip select polarity */ - if (slave->mode & SPI_CS_HIGH) - spi->cs_inactive &= ~BIT(slave->cs); + if (slave_plat->mode & SPI_CS_HIGH) + spi->cs_inactive &= ~BIT(slave_plat->cs); else - spi->cs_inactive |= BIT(slave->cs); + spi->cs_inactive |= BIT(slave_plat->cs); writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF); /* Select the correct device */ - writel(slave->cs, spi->regs + SIFIVE_SPI_REG_CSID); + writel(slave_plat->cs, spi->regs + SIFIVE_SPI_REG_CSID); } static int sifive_spi_set_cs(struct sifive_spi *spi, - struct dm_spi_slave_platdata *slave) + struct dm_spi_slave_platdata *slave_plat) { u32 cs_mode = SIFIVE_SPI_CSMODE_MODE_HOLD; - if (slave->mode & SPI_CS_HIGH) + if (slave_plat->mode & SPI_CS_HIGH) cs_mode = SIFIVE_SPI_CSMODE_MODE_AUTO; writel(cs_mode, spi->regs + SIFIVE_SPI_REG_CSMODE); @@ -128,7 +128,7 @@ static void sifive_spi_clear_cs(struct sifive_spi *spi) static void sifive_spi_prep_transfer(struct sifive_spi *spi, bool is_rx_xfer, - struct dm_spi_slave_platdata *slave) + struct dm_spi_slave_platdata *slave_plat) { u32 cr; @@ -141,14 +141,14 @@ static void sifive_spi_prep_transfer(struct sifive_spi *spi, /* LSB first? */ cr &= ~SIFIVE_SPI_FMT_ENDIAN; - if (slave->mode & SPI_LSB_FIRST) + if (slave_plat->mode & SPI_LSB_FIRST) cr |= SIFIVE_SPI_FMT_ENDIAN; /* Number of wires ? */ cr &= ~SIFIVE_SPI_FMT_PROTO_MASK; - if ((slave->mode & SPI_TX_QUAD) || (slave->mode & SPI_RX_QUAD)) + if ((slave_plat->mode & SPI_TX_QUAD) || (slave_plat->mode & SPI_RX_QUAD)) cr |= SIFIVE_SPI_FMT_PROTO_QUAD; - else if ((slave->mode & SPI_TX_DUAL) || (slave->mode & SPI_RX_DUAL)) + else if ((slave_plat->mode & SPI_TX_DUAL) || (slave_plat->mode & SPI_RX_DUAL)) cr |= SIFIVE_SPI_FMT_PROTO_DUAL; else cr |= SIFIVE_SPI_FMT_PROTO_SINGLE; @@ -191,21 +191,21 @@ static int sifive_spi_xfer(struct udevice *dev, unsigned int bitlen, { struct udevice *bus = dev->parent; struct sifive_spi *spi = dev_get_priv(bus); - struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev); + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); const unsigned char *tx_ptr = dout; u8 *rx_ptr = din; u32 remaining_len; int ret; if (flags & SPI_XFER_BEGIN) { - sifive_spi_prep_device(spi, slave); + sifive_spi_prep_device(spi, slave_plat); - ret = sifive_spi_set_cs(spi, slave); + ret = sifive_spi_set_cs(spi, slave_plat); if (ret) return ret; } - sifive_spi_prep_transfer(spi, true, slave); + sifive_spi_prep_transfer(spi, true, slave_plat); remaining_len = bitlen / 8; From 5bf3f3dd11db4048d7ad60f2ee210dc50da26051 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 20 Apr 2020 15:36:06 +0530 Subject: [PATCH 024/237] mtd: spi-nor: Enable QE bit for ISSI flash Enable QE bit for ISSI flash chips. QE enablement logic is similar to what Macronix has, so reuse the existing code itself. Cc: Sagar Shrikant Kadam Signed-off-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 1 + include/linux/mtd/spi-nor.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 3bf8ddfb9df..e840c60f275 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -325,6 +325,7 @@ static int set_4byte(struct spi_nor *nor, const struct flash_info *info, case SNOR_MFR_MICRON: /* Some Micron need WREN command; all will accept it */ need_wren = true; + case SNOR_MFR_ISSI: case SNOR_MFR_MACRONIX: case SNOR_MFR_WINBOND: if (need_wren) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index ec144a08d8f..233fdc341a7 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -22,6 +22,7 @@ #define SNOR_MFR_INTEL CFI_MFR_INTEL #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */ #define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */ +#define SNOR_MFR_ISSI CFI_MFR_PMC #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX #define SNOR_MFR_SPANSION CFI_MFR_AMD #define SNOR_MFR_SST CFI_MFR_SST From a976238de39c6adc34b2505a147c93acc6e27124 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 20 Apr 2020 15:36:07 +0530 Subject: [PATCH 025/237] mtd: spi-nor-ids: Enable 4B_OPCODES for is25wp256 IS25WP256 flash chips do support 4byte address opcodes, so enable support for it. Signed-off-by: Jagan Teki Reviewed-by: Sagar Kadam --- drivers/mtd/spi/spi-nor-ids.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 218385f50a1..804ec6307a7 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -135,7 +135,8 @@ const struct flash_info spi_nor_ids[] = { { INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ /* Macronix */ From 0a08a614b05e8dd199ba15179e2cb8b55a3f8e32 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 20 Apr 2020 23:34:13 +0530 Subject: [PATCH 026/237] watchdog: kconfig: Enable designware for rk3399 Enable designware watchdog driver for rk3399 if WDT defined. Cc: Marek Vasut Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/watchdog/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 6cafd243e04..bf06180cddf 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -49,6 +49,7 @@ config ULP_WATCHDOG config DESIGNWARE_WATCHDOG bool "Designware watchdog timer support" select HW_WATCHDOG if !WDT + default y if WDT && ROCKCHIP_RK3399 help Enable this to support Designware Watchdog Timer IP, present e.g. on Altera SoCFPGA SoCs. From 685465fbba4f502190f9d1ccd28443f5e0e4ec20 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Fri, 3 Apr 2020 12:27:42 +0530 Subject: [PATCH 027/237] mtd: spi-nor-ids: Add Spansion s25fs512s flash entry Spansion "s25fs512s" flash is incorrectly decoded as "s25fl512s" on various platforms as former is not present. Add the entry. Linux already has both the flashes present. A snippet below: { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256...}, { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256...}, Signed-off-by: Kuldeep Singh Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-ids.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 804ec6307a7..e5e71029231 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -195,7 +195,8 @@ const struct flash_info spi_nor_ids[] = { { INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, - { INFO6("s25fl512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, From b7d6e104fbfd54b7ffe9e0a00200e98dd2904a65 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 23 Apr 2020 22:30:53 +0530 Subject: [PATCH 028/237] spi: sifive: Add spi-mem exec op SiFive SPI controller is responsible to handle the slave devices like mmc spi and spi nor flash. The controller is designed such a way that it would handle the slave transactions based on the I/O protocol numbers, example if spi nor slave send quad write opcode it has to send alone with I/O protocol number of 4 and if it try to send data it has to send I/O protocol number along with 4 line data. But the current spi-xfer code from spi-mem is combining the opcode and address in a single transaction, so the SPI controller will be unable to identify the I/O protocol number of opcode vs address. So, add the spi-mem exec_op with spi-xfer of opcode, address and data as a separate transaction. This doesn't remove the .xfer of dm_spi_ops since mmc spi will make use of it. Note: This code might have moved to the spi-mem core area once we have done the dedicated tests on other controllers and have real reason to move. Cc: Vignesh R Signed-off-by: Jagan Teki Tested-by: Sagar Kadam --- drivers/spi/spi-sifive.c | 75 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 74 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c index 8f5efb51a37..5e612edcff7 100644 --- a/drivers/spi/spi-sifive.c +++ b/drivers/spi/spi-sifive.c @@ -8,8 +8,9 @@ #include #include +#include #include -#include +#include #include #include #include @@ -241,6 +242,73 @@ static int sifive_spi_xfer(struct udevice *dev, unsigned int bitlen, return 0; } +static int sifive_spi_exec_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + struct udevice *dev = slave->dev; + unsigned long flags = SPI_XFER_BEGIN; + u8 opcode = op->cmd.opcode; + unsigned int pos = 0; + const void *tx_buf = NULL; + void *rx_buf = NULL; + int op_len, i; + int ret; + + if (!op->addr.nbytes && !op->dummy.nbytes && !op->data.nbytes) + flags |= SPI_XFER_END; + + /* send the opcode */ + ret = sifive_spi_xfer(dev, 8, (void *)&opcode, NULL, flags); + if (ret < 0) { + dev_err(dev, "failed to xfer opcode\n"); + return ret; + } + + op_len = op->addr.nbytes + op->dummy.nbytes; + u8 op_buf[op_len]; + + /* send the addr + dummy */ + if (op->addr.nbytes) { + /* fill address */ + for (i = 0; i < op->addr.nbytes; i++) + op_buf[pos + i] = op->addr.val >> + (8 * (op->addr.nbytes - i - 1)); + + pos += op->addr.nbytes; + + /* fill dummy */ + if (op->dummy.nbytes) + memset(op_buf + pos, 0xff, op->dummy.nbytes); + + /* make sure to set end flag, if no data bytes */ + if (!op->data.nbytes) + flags |= SPI_XFER_END; + + ret = sifive_spi_xfer(dev, op_len * 8, op_buf, NULL, flags); + if (ret < 0) { + dev_err(dev, "failed to xfer addr + dummy\n"); + return ret; + } + } + + /* send/received the data */ + if (op->data.nbytes) { + if (op->data.dir == SPI_MEM_DATA_IN) + rx_buf = op->data.buf.in; + else + tx_buf = op->data.buf.out; + + ret = sifive_spi_xfer(dev, op->data.nbytes * 8, + tx_buf, rx_buf, SPI_XFER_END); + if (ret) { + dev_err(dev, "failed to xfer data\n"); + return ret; + } + } + + return 0; +} + static int sifive_spi_set_speed(struct udevice *bus, uint speed) { struct sifive_spi *spi = dev_get_priv(bus); @@ -348,11 +416,16 @@ static int sifive_spi_probe(struct udevice *bus) return 0; } +static const struct spi_controller_mem_ops sifive_spi_mem_ops = { + .exec_op = sifive_spi_exec_op, +}; + static const struct dm_spi_ops sifive_spi_ops = { .xfer = sifive_spi_xfer, .set_speed = sifive_spi_set_speed, .set_mode = sifive_spi_set_mode, .cs_info = sifive_spi_cs_info, + .mem_ops = &sifive_spi_mem_ops, }; static const struct udevice_id sifive_spi_ids[] = { From 622b913ea179645a37dc4fcb75cea6f54d3b505f Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 23 Apr 2020 22:30:54 +0530 Subject: [PATCH 029/237] spi: sifive: Fix format register proto field MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SiFive SPI controller has a proto bit field in frame format register which would be used to configure the SPI I/O protocol lines used on specific transfer.  Right now the driver is configuring this proto using slave->mode, for all types of transctions. This makes the driver unable to function since the proto needs to configure dynamically for each and every transaction separately at runtime. Now, the controller driver supports per transfer via spi-mem exec_opo, so add the fmt_proto flag and fill the per transfer buswidth so that the controller configures the proto bit at runtime. This patch fixes the SPI controller works with SPI NOR flash on quad read with page program. Cc: Vignesh R Signed-off-by: Jagan Teki Tested-by: Sagar Kadam --- drivers/spi/spi-sifive.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c index 5e612edcff7..0ea4930a0a3 100644 --- a/drivers/spi/spi-sifive.c +++ b/drivers/spi/spi-sifive.c @@ -86,6 +86,11 @@ #define SIFIVE_SPI_IP_TXWM BIT(0) #define SIFIVE_SPI_IP_RXWM BIT(1) +/* format protocol */ +#define SIFIVE_SPI_PROTO_QUAD 4 /* 4 lines I/O protocol transfer */ +#define SIFIVE_SPI_PROTO_DUAL 2 /* 2 lines I/O protocol transfer */ +#define SIFIVE_SPI_PROTO_SINGLE 1 /* 1 line I/O protocol transfer */ + struct sifive_spi { void *regs; /* base address of the registers */ u32 fifo_depth; @@ -93,6 +98,7 @@ struct sifive_spi { u32 cs_inactive; /* Level of the CS pins when inactive*/ u32 freq; u32 num_cs; + u8 fmt_proto; }; static void sifive_spi_prep_device(struct sifive_spi *spi, @@ -147,12 +153,17 @@ static void sifive_spi_prep_transfer(struct sifive_spi *spi, /* Number of wires ? */ cr &= ~SIFIVE_SPI_FMT_PROTO_MASK; - if ((slave_plat->mode & SPI_TX_QUAD) || (slave_plat->mode & SPI_RX_QUAD)) + switch (spi->fmt_proto) { + case SIFIVE_SPI_PROTO_QUAD: cr |= SIFIVE_SPI_FMT_PROTO_QUAD; - else if ((slave_plat->mode & SPI_TX_DUAL) || (slave_plat->mode & SPI_RX_DUAL)) + break; + case SIFIVE_SPI_PROTO_DUAL: cr |= SIFIVE_SPI_FMT_PROTO_DUAL; - else + break; + default: cr |= SIFIVE_SPI_FMT_PROTO_SINGLE; + break; + } /* SPI direction in/out ? */ cr &= ~SIFIVE_SPI_FMT_DIR; @@ -246,6 +257,7 @@ static int sifive_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) { struct udevice *dev = slave->dev; + struct sifive_spi *spi = dev_get_priv(dev->parent); unsigned long flags = SPI_XFER_BEGIN; u8 opcode = op->cmd.opcode; unsigned int pos = 0; @@ -257,6 +269,8 @@ static int sifive_spi_exec_op(struct spi_slave *slave, if (!op->addr.nbytes && !op->dummy.nbytes && !op->data.nbytes) flags |= SPI_XFER_END; + spi->fmt_proto = op->cmd.buswidth; + /* send the opcode */ ret = sifive_spi_xfer(dev, 8, (void *)&opcode, NULL, flags); if (ret < 0) { @@ -284,6 +298,8 @@ static int sifive_spi_exec_op(struct spi_slave *slave, if (!op->data.nbytes) flags |= SPI_XFER_END; + spi->fmt_proto = op->addr.buswidth; + ret = sifive_spi_xfer(dev, op_len * 8, op_buf, NULL, flags); if (ret < 0) { dev_err(dev, "failed to xfer addr + dummy\n"); @@ -298,6 +314,8 @@ static int sifive_spi_exec_op(struct spi_slave *slave, else tx_buf = op->data.buf.out; + spi->fmt_proto = op->data.buswidth; + ret = sifive_spi_xfer(dev, op->data.nbytes * 8, tx_buf, rx_buf, SPI_XFER_END); if (ret) { From 25e4d94f45611bfc5f1ff71cf29a8d41bb6e9e9f Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 23 Apr 2020 22:30:55 +0530 Subject: [PATCH 030/237] spi: sifive: Fix QPP transfer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The guessed reason is that the existing logic of filling tx fifo with data, rx fifo with NULL for tx transfer and filling rx fifo with data, tx fifo with NULL for rx transfer is not clear enough to support the Quad Page Program.     SiFive SPI controllers have specific sets of watermark registers and SPI I/O directions bits in order to program SPI controllers clear enough to support all sets of operating modes.     Here is the exact programing sequence that would follow on this patch and tested via SPI-NOR and MMC_SPI.     - set the frame format proto, endian - set the frame format dir, set it for tx and clear it for rx - TX transfer:   fill tx fifo with data.   wait for TX watermark bit to clear. - RX transfer:   fill tx fifo with 0xff.   write nbytes to rx watermark register   wait for rx watermark bit to clear.   read the rx fifo data. So, this patch adopts this program sequence and fixes the existing I/O direction bit. Cc: Vignesh R Signed-off-by: Jagan Teki Tested-by: Sagar Kadam --- drivers/spi/spi-sifive.c | 57 ++++++++++++++++++++++++++-------------- 1 file changed, 37 insertions(+), 20 deletions(-) diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c index 0ea4930a0a3..4cab0391f7d 100644 --- a/drivers/spi/spi-sifive.c +++ b/drivers/spi/spi-sifive.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -134,8 +135,8 @@ static void sifive_spi_clear_cs(struct sifive_spi *spi) } static void sifive_spi_prep_transfer(struct sifive_spi *spi, - bool is_rx_xfer, - struct dm_spi_slave_platdata *slave_plat) + struct dm_spi_slave_platdata *slave_plat, + u8 *rx_ptr) { u32 cr; @@ -167,7 +168,7 @@ static void sifive_spi_prep_transfer(struct sifive_spi *spi, /* SPI direction in/out ? */ cr &= ~SIFIVE_SPI_FMT_DIR; - if (!is_rx_xfer) + if (!rx_ptr) cr |= SIFIVE_SPI_FMT_DIR; writel(cr, spi->regs + SIFIVE_SPI_REG_FMT); @@ -198,13 +199,19 @@ static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr) writel(tx_data, spi->regs + SIFIVE_SPI_REG_TXDATA); } +static int sifive_spi_wait(struct sifive_spi *spi, u32 bit) +{ + return wait_for_bit_le32(spi->regs + SIFIVE_SPI_REG_IP, + bit, true, 100, false); +} + static int sifive_spi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { struct udevice *bus = dev->parent; struct sifive_spi *spi = dev_get_priv(bus); struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); - const unsigned char *tx_ptr = dout; + const u8 *tx_ptr = dout; u8 *rx_ptr = din; u32 remaining_len; int ret; @@ -217,31 +224,37 @@ static int sifive_spi_xfer(struct udevice *dev, unsigned int bitlen, return ret; } - sifive_spi_prep_transfer(spi, true, slave_plat); + sifive_spi_prep_transfer(spi, slave_plat, rx_ptr); remaining_len = bitlen / 8; while (remaining_len) { - int n_words, tx_words, rx_words; - - n_words = min(remaining_len, spi->fifo_depth); + unsigned int n_words = min(remaining_len, spi->fifo_depth); + unsigned int tx_words, rx_words; /* Enqueue n_words for transmission */ - if (tx_ptr) { - for (tx_words = 0; tx_words < n_words; ++tx_words) { - sifive_spi_tx(spi, tx_ptr); - sifive_spi_rx(spi, NULL); - tx_ptr++; - } + for (tx_words = 0; tx_words < n_words; tx_words++) { + if (!tx_ptr) + sifive_spi_tx(spi, NULL); + else + sifive_spi_tx(spi, tx_ptr++); } - /* Read out all the data from the RX FIFO */ if (rx_ptr) { - for (rx_words = 0; rx_words < n_words; ++rx_words) { - sifive_spi_tx(spi, NULL); - sifive_spi_rx(spi, rx_ptr); - rx_ptr++; - } + /* Wait for transmission + reception to complete */ + writel(n_words - 1, spi->regs + SIFIVE_SPI_REG_RXMARK); + ret = sifive_spi_wait(spi, SIFIVE_SPI_IP_RXWM); + if (ret) + return ret; + + /* Read out all the data from the RX FIFO */ + for (rx_words = 0; rx_words < n_words; rx_words++) + sifive_spi_rx(spi, rx_ptr++); + } else { + /* Wait for transmission to complete */ + ret = sifive_spi_wait(spi, SIFIVE_SPI_IP_TXWM); + if (ret) + return ret; } remaining_len -= n_words; @@ -395,6 +408,10 @@ static void sifive_spi_init_hw(struct sifive_spi *spi) /* Watermark interrupts are disabled by default */ writel(0, spi->regs + SIFIVE_SPI_REG_IE); + /* Default watermark FIFO threshold values */ + writel(1, spi->regs + SIFIVE_SPI_REG_TXMARK); + writel(0, spi->regs + SIFIVE_SPI_REG_RXMARK); + /* Set CS/SCK Delays and Inactive Time to defaults */ writel(SIFIVE_SPI_DELAY0_CSSCK(1) | SIFIVE_SPI_DELAY0_SCKCS(1), spi->regs + SIFIVE_SPI_REG_DELAY0); From 0edb066ce56504f84b8d8ff0e6f542fc36d0f3b7 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 23 Apr 2020 22:30:56 +0530 Subject: [PATCH 031/237] riscv: dts: hifive-unleashed-a00: Add -u-boot.dtsi Add U-Boot specific dts file for hifive-unleashed-a00, this would help to add u-boot specific properties and other node changes without touching the base dts(i) files which are easy to sync from Linux. Added spi2 alias for qspi2 as an initial u-boot specific property change. spi probing in current dm model is very much rely on aliases numbering. Even though the qspi2 can't come under any associated spi nor flash it would require to specify the same to make proper binding happen for other spi slaves. Signed-off-by: Jagan Teki Reviewed-by: Bin Meng Tested-by: Sagar Kadam --- arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi new file mode 100644 index 00000000000..8a784b56619 --- /dev/null +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2019 Jagan Teki + */ + +/ { + aliases { + spi2 = &qspi2; + }; +}; From 286bcdb40f11def282117e16401bb85502e426a8 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 29 Apr 2020 21:03:53 +0530 Subject: [PATCH 032/237] sifive: fu540: Enable spi-nor flash support HiFive Unleashed A00 support is25wp256 spi-nor flash, So enable the same and add test result log for future reference. Tested on SiFive FU540 board. Thanks to Sagar for various use cases and tests. [QUAD mode in dt with spi-tx-bus-width: <4>] pp opcode = 0x34 [QUAD MODE] read opcode = 0x6c [QUAD MODE] erase opcode = 0x21 SPI-NOR: 1. erase entire flash: Pass 2. write entire flash: Pass 3. read entire flash: Pass 4. cmp 32MiB read back data: Pass 5. MMC: Booted Linux and dtb from mmc [SPI MODE in dt with spi-tx-bus-width: <1>] pp opcode = 0x12 [SPI MODE] read opcode = 0xc [SPI MODE] erase opcode = 0x21 SPI-NOR: 1. erase entire flash: Pass 2. write entire flash: Pass 3. read entire flash: Pass 4. cmp 32MiB read back data: Pass 5. MMC: Booted Linux and dtb from mmc Signed-off-by: Jagan Teki Reviewed-by: Bin Meng Tested-by: Sagar Kadam --- arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 1 + board/sifive/fu540/Kconfig | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi index 8a784b56619..2aebfab6466 100644 --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi @@ -5,6 +5,7 @@ / { aliases { + spi0 = &qspi0; spi2 = &qspi2; }; }; diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index 5ca21474dee..75661f35f8a 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply CMD_FS_GENERIC imply CMD_NET imply CMD_PING + imply CMD_SF imply CLK_SIFIVE imply CLK_SIFIVE_FU540_PRCI imply DOS_PARTITION @@ -40,6 +41,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply SIFIVE_SERIAL imply SPI imply SPI_SIFIVE + imply SPI_FLASH + imply SPI_FLASH_ISSI imply MMC imply MMC_SPI imply MMC_BROKEN_CD From 9a031773788bdd242f7b6616da9f41335dec821a Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 27 Apr 2020 14:52:46 +0800 Subject: [PATCH 033/237] rockchip: dts: rk3328-evb: Move vcc5v0-host-xhci-drv to -u-boot.dtsi USB 3.0 is only supported in U-boot, not in the Linux kernel where the device tree files are ultimately synced from. While the xhci node was moved, the external vbus regulator was not. Move it as well. Fixes: 2e91e2025c1b ("rockchip: rk3328: migrate u-boot node to -u-boot.dtsi") Reviewed-by: Kever Yang Tested-by: Loic Devulder Tested-by: Peter Geis Signed-off-by: Chen-Yu Tsai --- arch/arm/dts/rk3328-evb-u-boot.dtsi | 11 +++++++++++ arch/arm/dts/rk3328-evb.dts | 9 --------- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi b/arch/arm/dts/rk3328-evb-u-boot.dtsi index 4a827063c55..5679897279a 100644 --- a/arch/arm/dts/rk3328-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi @@ -6,6 +6,17 @@ #include "rk3328-u-boot.dtsi" #include "rk3328-sdram-ddr3-666.dtsi" +/{ + vcc5v0_host_xhci: vcc5v0-host-xhci-drv { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc5v0_host_xhci"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + &usb_host0_xhci { vbus-supply = <&vcc5v0_host_xhci>; status = "okay"; diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index a2ee838fcd6..e9bc849f8c2 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -38,15 +38,6 @@ regulator-max-microvolt = <5000000>; }; - vcc5v0_host_xhci: vcc5v0-host-xhci-drv { - compatible = "regulator-fixed"; - enable-active-high; - regulator-name = "vcc5v0_host_xhci"; - gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - vcc_phy: vcc-phy-regulator { compatible = "regulator-fixed"; regulator-name = "vcc_phy"; From 032ca153e292c0ab9138c2bbd3106bf473b2527f Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 27 Apr 2020 14:52:47 +0800 Subject: [PATCH 034/237] rockchip: dts: rk3328-evb: Move gmac2io related nodes to -u-boot.dtsi The device tree file for rk3328-evb in the Linux kernel does not have gmac2io enabled. Instead, gmac2phy is enabled, but that is not supported in U-boot. Move the gmac2io related nodes to rk3328-evb-u-boot.dtsi to preserve the current functionality. When the device tree files are synced, gmac2phy should be marked as "broken" in -u-boot.dtsi files. Reviewed-by: Kever Yang Tested-by: Loic Devulder Tested-by: Peter Geis Signed-off-by: Chen-Yu Tsai --- arch/arm/dts/rk3328-evb-u-boot.dtsi | 23 +++++++++++++++++++++++ arch/arm/dts/rk3328-evb.dts | 23 ----------------------- 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi b/arch/arm/dts/rk3328-evb-u-boot.dtsi index 5679897279a..8ba53cf8f44 100644 --- a/arch/arm/dts/rk3328-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi @@ -7,6 +7,13 @@ #include "rk3328-sdram-ddr3-666.dtsi" /{ + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + vcc5v0_host_xhci: vcc5v0-host-xhci-drv { compatible = "regulator-fixed"; enable-active-high; @@ -17,6 +24,22 @@ }; }; +&gmac2io { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + tx_delay = <0x26>; + rx_delay = <0x11>; + status = "okay"; +}; + &usb_host0_xhci { vbus-supply = <&vcc5v0_host_xhci>; status = "okay"; diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index e9bc849f8c2..97bef37cf61 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -14,13 +14,6 @@ stdout-path = &uart2; }; - gmac_clkin: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - vcc3v3_sdmmc: sdmmc-pwren { compatible = "regulator-fixed"; regulator-name = "vcc3v3"; @@ -78,22 +71,6 @@ status = "okay"; }; -&gmac2io { - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmiim1_pins>; - tx_delay = <0x26>; - rx_delay = <0x11>; - status = "okay"; -}; - &usb_host0_ehci { status = "okay"; }; From 32fd6169a199506b2d2ee08bde3b027fa227cbb0 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 27 Apr 2020 14:52:48 +0800 Subject: [PATCH 035/237] rockchip: dts: rk3328: Move OTG node's hnp-srp-disable to rk3328-u-boot.dtsi The "hnp-srp-disable" property for dwc2 is specific to U-boot, not part of upstream Linux's device tree bindings. Move it to rk3328-u-boot.dtsi to avoid losing it when syncing device tree files. Signed-off-by: Chen-Yu Tsai Reviewed-by: Kever Yang --- arch/arm/dts/rk3328-u-boot.dtsi | 4 ++++ arch/arm/dts/rk3328.dtsi | 1 - 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index 6d5b3ec06e0..c69e13e11ef 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -62,3 +62,7 @@ /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */ u-boot,spl-fifo-mode; }; + +&usb20_otg { + hnp-srp-disable; +}; diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index 060c84e6c0c..57719b82d13 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -483,7 +483,6 @@ "snps,dwc2"; reg = <0x0 0xff580000 0x0 0x40000>; interrupts = ; - hnp-srp-disable; dr_mode = "otg"; status = "disabled"; }; From d751b0c00091670c335335a77d6fe192609db493 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 27 Apr 2020 14:52:49 +0800 Subject: [PATCH 036/237] dt-bindings: clock: rk3328: sync from upstream Linux kernel This syncs the rk3328 clock header file from Linux kernel next-20200324, to support newer hardware blocks when syncing the device tree files. The last non-merge commit to touch it was 0dc14b013f79 ("clk: rockchip: add clock id for watchdog pclk on rk3328") Reviewed-by: Kever Yang Tested-by: Loic Devulder Tested-by: Peter Geis Signed-off-by: Chen-Yu Tsai --- include/dt-bindings/clock/rk3328-cru.h | 212 ++++++++++++------------- 1 file changed, 106 insertions(+), 106 deletions(-) diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h index cde61ed8830..555b4ff660a 100644 --- a/include/dt-bindings/clock/rk3328-cru.h +++ b/include/dt-bindings/clock/rk3328-cru.h @@ -1,6 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * Copyright (c) 2016 Rockchip Electronics Co. Ltd. + * Author: Elaine */ #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H @@ -90,119 +91,118 @@ #define SCLK_MAC2IO_EXT 102 /* dclk gates */ -#define DCLK_LCDC 180 -#define DCLK_HDMIPHY 181 -#define HDMIPHY 182 -#define USB480M 183 -#define DCLK_LCDC_SRC 184 +#define DCLK_LCDC 120 +#define DCLK_HDMIPHY 121 +#define HDMIPHY 122 +#define USB480M 123 +#define DCLK_LCDC_SRC 124 /* aclk gates */ -#define ACLK_AXISRAM 190 -#define ACLK_VOP_PRE 191 -#define ACLK_USB3OTG 192 -#define ACLK_RGA_PRE 193 -#define ACLK_DMAC 194 -#define ACLK_GPU 195 -#define ACLK_BUS_PRE 196 -#define ACLK_PERI_PRE 197 -#define ACLK_RKVDEC_PRE 198 -#define ACLK_RKVDEC 199 -#define ACLK_RKVENC 200 -#define ACLK_VPU_PRE 201 -#define ACLK_VIO_PRE 202 -#define ACLK_VPU 203 -#define ACLK_VIO 204 -#define ACLK_VOP 205 -#define ACLK_GMAC 206 -#define ACLK_H265 207 -#define ACLK_H264 208 -#define ACLK_MAC2PHY 209 -#define ACLK_MAC2IO 210 -#define ACLK_DCF 211 -#define ACLK_TSP 212 -#define ACLK_PERI 213 -#define ACLK_RGA 214 -#define ACLK_IEP 215 -#define ACLK_CIF 216 -#define ACLK_HDCP 217 +#define ACLK_AXISRAM 130 +#define ACLK_VOP_PRE 131 +#define ACLK_USB3OTG 132 +#define ACLK_RGA_PRE 133 +#define ACLK_DMAC 134 +#define ACLK_GPU 135 +#define ACLK_BUS_PRE 136 +#define ACLK_PERI_PRE 137 +#define ACLK_RKVDEC_PRE 138 +#define ACLK_RKVDEC 139 +#define ACLK_RKVENC 140 +#define ACLK_VPU_PRE 141 +#define ACLK_VIO_PRE 142 +#define ACLK_VPU 143 +#define ACLK_VIO 144 +#define ACLK_VOP 145 +#define ACLK_GMAC 146 +#define ACLK_H265 147 +#define ACLK_H264 148 +#define ACLK_MAC2PHY 149 +#define ACLK_MAC2IO 150 +#define ACLK_DCF 151 +#define ACLK_TSP 152 +#define ACLK_PERI 153 +#define ACLK_RGA 154 +#define ACLK_IEP 155 +#define ACLK_CIF 156 +#define ACLK_HDCP 157 /* pclk gates */ -#define PCLK_GPIO0 300 -#define PCLK_GPIO1 301 -#define PCLK_GPIO2 302 -#define PCLK_GPIO3 303 -#define PCLK_GRF 304 -#define PCLK_I2C0 305 -#define PCLK_I2C1 306 -#define PCLK_I2C2 307 -#define PCLK_I2C3 308 -#define PCLK_SPI 309 -#define PCLK_UART0 310 -#define PCLK_UART1 311 -#define PCLK_UART2 312 -#define PCLK_TSADC 313 -#define PCLK_PWM 314 -#define PCLK_TIMER 315 -#define PCLK_BUS_PRE 316 -#define PCLK_PERI_PRE 317 -#define PCLK_HDMI_CTRL 318 -#define PCLK_HDMI_PHY 319 -#define PCLK_GMAC 320 -#define PCLK_H265 321 -#define PCLK_MAC2PHY 322 -#define PCLK_MAC2IO 323 -#define PCLK_USB3PHY_OTG 324 -#define PCLK_USB3PHY_PIPE 325 -#define PCLK_USB3_GRF 326 -#define PCLK_USB2_GRF 327 -#define PCLK_HDMIPHY 328 -#define PCLK_DDR 329 -#define PCLK_PERI 330 -#define PCLK_HDMI 331 -#define PCLK_HDCP 332 -#define PCLK_DCF 333 -#define PCLK_SARADC 334 +#define PCLK_GPIO0 200 +#define PCLK_GPIO1 201 +#define PCLK_GPIO2 202 +#define PCLK_GPIO3 203 +#define PCLK_GRF 204 +#define PCLK_I2C0 205 +#define PCLK_I2C1 206 +#define PCLK_I2C2 207 +#define PCLK_I2C3 208 +#define PCLK_SPI 209 +#define PCLK_UART0 210 +#define PCLK_UART1 211 +#define PCLK_UART2 212 +#define PCLK_TSADC 213 +#define PCLK_PWM 214 +#define PCLK_TIMER 215 +#define PCLK_BUS_PRE 216 +#define PCLK_PERI_PRE 217 +#define PCLK_HDMI_CTRL 218 +#define PCLK_HDMI_PHY 219 +#define PCLK_GMAC 220 +#define PCLK_H265 221 +#define PCLK_MAC2PHY 222 +#define PCLK_MAC2IO 223 +#define PCLK_USB3PHY_OTG 224 +#define PCLK_USB3PHY_PIPE 225 +#define PCLK_USB3_GRF 226 +#define PCLK_USB2_GRF 227 +#define PCLK_HDMIPHY 228 +#define PCLK_DDR 229 +#define PCLK_PERI 230 +#define PCLK_HDMI 231 +#define PCLK_HDCP 232 +#define PCLK_DCF 233 +#define PCLK_SARADC 234 +#define PCLK_ACODECPHY 235 +#define PCLK_WDT 236 /* hclk gates */ -#define HCLK_PERI 408 -#define HCLK_TSP 409 -#define HCLK_GMAC 410 -#define HCLK_I2S0_8CH 411 -#define HCLK_I2S1_8CH 413 -#define HCLK_I2S2_2CH 413 -#define HCLK_SPDIF_8CH 414 -#define HCLK_VOP 415 -#define HCLK_NANDC 416 -#define HCLK_SDMMC 417 -#define HCLK_SDIO 418 -#define HCLK_EMMC 419 -#define HCLK_SDMMC_EXT 420 -#define HCLK_RKVDEC_PRE 421 -#define HCLK_RKVDEC 422 -#define HCLK_RKVENC 423 -#define HCLK_VPU_PRE 424 -#define HCLK_VIO_PRE 425 -#define HCLK_VPU 426 -#define HCLK_VIO 427 -#define HCLK_BUS_PRE 428 -#define HCLK_PERI_PRE 429 -#define HCLK_H264 430 -#define HCLK_CIF 431 -#define HCLK_OTG_PMU 432 -#define HCLK_OTG 433 -#define HCLK_HOST0 434 -#define HCLK_HOST0_ARB 435 -#define HCLK_CRYPTO_MST 436 -#define HCLK_CRYPTO_SLV 437 -#define HCLK_PDM 438 -#define HCLK_IEP 439 -#define HCLK_RGA 440 -#define HCLK_HDCP 441 +#define HCLK_PERI 308 +#define HCLK_TSP 309 +#define HCLK_GMAC 310 +#define HCLK_I2S0_8CH 311 +#define HCLK_I2S1_8CH 312 +#define HCLK_I2S2_2CH 313 +#define HCLK_SPDIF_8CH 314 +#define HCLK_VOP 315 +#define HCLK_NANDC 316 +#define HCLK_SDMMC 317 +#define HCLK_SDIO 318 +#define HCLK_EMMC 319 +#define HCLK_SDMMC_EXT 320 +#define HCLK_RKVDEC_PRE 321 +#define HCLK_RKVDEC 322 +#define HCLK_RKVENC 323 +#define HCLK_VPU_PRE 324 +#define HCLK_VIO_PRE 325 +#define HCLK_VPU 326 +#define HCLK_BUS_PRE 328 +#define HCLK_PERI_PRE 329 +#define HCLK_H264 330 +#define HCLK_CIF 331 +#define HCLK_OTG_PMU 332 +#define HCLK_OTG 333 +#define HCLK_HOST0 334 +#define HCLK_HOST0_ARB 335 +#define HCLK_CRYPTO_MST 336 +#define HCLK_CRYPTO_SLV 337 +#define HCLK_PDM 338 +#define HCLK_IEP 339 +#define HCLK_RGA 340 +#define HCLK_HDCP 341 #define CLK_NR_CLKS (HCLK_HDCP + 1) -#define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1) - /* soft-reset indices */ #define SRST_CORE0_PO 0 #define SRST_CORE1_PO 1 From 2e15f86b54c00f63027be0dd19c5c561a8aa0e05 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 27 Apr 2020 14:52:50 +0800 Subject: [PATCH 037/237] dt-bindings: power: rk3328-power: sync from upstream Linux kernel This syncs the rk3328 power domain header file from Linux kernel next-20200324, to support newer hardware blocks when syncing the device tree files. The last non-merge commit to touch it was b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") Reviewed-by: Kever Yang Tested-by: Loic Devulder Tested-by: Peter Geis Signed-off-by: Chen-Yu Tsai --- include/dt-bindings/power/rk3328-power.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 include/dt-bindings/power/rk3328-power.h diff --git a/include/dt-bindings/power/rk3328-power.h b/include/dt-bindings/power/rk3328-power.h new file mode 100644 index 00000000000..02e3d7fc1cc --- /dev/null +++ b/include/dt-bindings/power/rk3328-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3328_POWER_H__ +#define __DT_BINDINGS_POWER_RK3328_POWER_H__ + +/** + * RK3328 idle id Summary. + */ +#define RK3328_PD_CORE 0 +#define RK3328_PD_GPU 1 +#define RK3328_PD_BUS 2 +#define RK3328_PD_MSCH 3 +#define RK3328_PD_PERI 4 +#define RK3328_PD_VIDEO 5 +#define RK3328_PD_HEVC 6 +#define RK3328_PD_SYS 7 +#define RK3328_PD_VPU 8 +#define RK3328_PD_VIO 9 + +#endif From 5d0ec90ac8d5d11fe490506d9b1bb55956996ac5 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 27 Apr 2020 14:52:51 +0800 Subject: [PATCH 038/237] rockchip: rk3328: Disable generic PHY support The USB PHYs on the RK3328 aren't supported, nor are any other generic PHYs. Because upstream Linux device trees already include the USB PHYs and references in the USB hosts, this would result in various calls to the generic PHY API to fail. Instead, just disable generic PHY support for now. Signed-off-by: Chen-Yu Tsai Reviewed-by: Kever Yang --- configs/evb-rk3328_defconfig | 1 - configs/rock64-rk3328_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 5bbdc002148..7667bb037b3 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -61,7 +61,6 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 826c7a69174..7d096d38c6d 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -60,7 +60,6 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y From 50cbff7cf36371728024e95ed46e3b9793b2bd8a Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 27 Apr 2020 14:52:52 +0800 Subject: [PATCH 039/237] rockchip: dts: rk3328: Sync device tree files from Linux This syncs rk3328 device tree files from the Linux kernel next-20200324. The last commit to touch these files is: b2411befed60 ("arm64: dts: add bus to rockchip amba nodenames") Additional changes not yet in the Linux kernel include: arm64: dts: rockchip: rk3328: drop #address-cells, #size-cells from grf node arm64: dts: rockchip: rk3328: drop non-existent gmac2phy pinmux options arm64: dts: rockchip: rk3328: Replace RK805 PMIC node name with "pmic" Changes include: - conversion of raw pin numbers to macros - removal of deprecated RK_FUNC_* macros - update of device tree binding headers - new devices - device tree cleanups - gmac2phy disabled in -u-boot.dtsi as it is not supported in U-boot This includes a re-ordering of the USB device nodes compared to upstream Linux, moving the dwc2 OTG controller after the EHCI/OHCI nodes. This is currently required as otherwise the dwc2 controller would not be able to detect devices in some cases. This may be due to lack of USB PHY support in U-boot. Signed-off-by: Chen-Yu Tsai --- arch/arm/dts/rk3328-evb-u-boot.dtsi | 5 + arch/arm/dts/rk3328-evb.dts | 196 ++-- arch/arm/dts/rk3328-rock64.dts | 132 ++- arch/arm/dts/rk3328.dtsi | 1414 +++++++++++++++++---------- 4 files changed, 1166 insertions(+), 581 deletions(-) diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi b/arch/arm/dts/rk3328-evb-u-boot.dtsi index 8ba53cf8f44..4bfa0c2330b 100644 --- a/arch/arm/dts/rk3328-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi @@ -40,6 +40,11 @@ status = "okay"; }; +&gmac2phy { + /* Integrated PHY unsupported by U-boot */ + status = "broken"; +}; + &usb_host0_xhci { vbus-supply = <&vcc5v0_host_xhci>; status = "okay"; diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index 97bef37cf61..6abc6f4a86c 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd */ /dts-v1/; @@ -11,24 +11,51 @@ compatible = "rockchip,rk3328-evb", "rockchip,rk3328"; chosen { - stdout-path = &uart2; + stdout-path = "serial2:1500000n8"; }; - vcc3v3_sdmmc: sdmmc-pwren { + dc_12v: dc-12v { compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; + regulator-name = "dc_12v"; regulator-always-on; regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; }; - vcc5v0_otg: vcc5v0-otg-drv { + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + }; + + vcc_sd: sdmmc-regulator { compatible = "regulator-fixed"; - enable-active-high; - regulator-name = "vcc5v0_otg"; - gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>; + gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_gpio>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; }; vcc_phy: vcc-phy-regulator { @@ -39,80 +66,60 @@ }; }; -&saradc { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; - status = "okay"; +&cpu0 { + cpu-supply = <&vdd_arm>; }; &emmc { bus-width = <8>; cap-mmc-highspeed; - supports-emmc; - disable-wp; non-removable; - num-slots = <1>; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; status = "okay"; }; -&usb_host0_ehci { - status = "okay"; -}; +&gmac2phy { + phy-supply = <&vcc_phy>; + clock_in_out = "output"; + assigned-clocks = <&cru SCLK_MAC2PHY_SRC>; + assigned-clock-rate = <50000000>; + assigned-clocks = <&cru SCLK_MAC2PHY>; + assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; -&usb_host0_ohci { - status = "okay"; -}; - -&usb20_otg { - vbus-supply = <&vcc5v0_otg>; - status = "okay"; }; &i2c1 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; status = "okay"; rk805: pmic@18 { compatible = "rockchip,rk805"; - status = "okay"; reg = <0x18>; interrupt-parent = <&gpio2>; interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pmic_int_l>; rockchip,system-power-controller; wakeup-source; - gpio-controller; - #gpio-cells = <2>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_io>; regulators { vdd_logic: DCDC_REG1 { regulator-name = "vdd_logic"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <6001>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1000000>; @@ -123,19 +130,18 @@ regulator-name = "vdd_arm"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <6001>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; + regulator-suspend-microvolt = <950000>; }; }; vcc_ddr: DCDC_REG3 { regulator-name = "vcc_ddr"; - regulator-boot-on; regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; }; @@ -145,32 +151,32 @@ regulator-name = "vcc_io"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <3300000>; }; }; - vdd_18: LDO_REG1 { - regulator-name = "vdd_18"; + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1800000>; }; }; - vcc_18emmc: LDO_REG2 { - regulator-name = "vcc_18emmc"; + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1800000>; @@ -181,8 +187,8 @@ regulator-name = "vdd_10"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1000000>; @@ -195,9 +201,71 @@ &pinctrl { pmic { pmic_int_l: pmic-int-l { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { rockchip,pins = - <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; /* gpio2_a6 */ + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <150000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts index a78eb4ac6ff..ebf3eb222e1 100644 --- a/arch/arm/dts/rk3328-rock64.dts +++ b/arch/arm/dts/rk3328-rock64.dts @@ -43,6 +43,17 @@ vin-supply = <&vcc_sys>; }; + vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host_drv>; + regulator-name = "vcc_host1_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + vcc_sys: vcc-sys { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; @@ -51,6 +62,56 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&ir_int>; + pinctrl-names = "default"; + }; + + leds { + compatible = "gpio-leds"; + + power { + gpios = <&rk805 1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc0"; + }; + + standby { + gpios = <&rk805 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + sound { + compatible = "audio-graph-card"; + label = "rockchip,rk3328"; + dais = <&i2s1_p0 + &spdif_p0>; + }; + + spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + + port { + dit_p0_0: endpoint { + remote-endpoint = <&spdif_p0_0>; + }; + }; + }; +}; + +&codec { + mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; + status = "okay"; + + port@0 { + codec_p0_0: endpoint { + remote-endpoint = <&i2s1_p0_0>; + }; + }; }; &cpu0 { @@ -98,16 +159,26 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + &i2c1 { status = "okay"; - rk805: rk805@18 { + rk805: pmic@18 { compatible = "rockchip,rk805"; reg = <0x18>; interrupt-parent = <&gpio2>; interrupts = <6 IRQ_TYPE_LEVEL_LOW>; #clock-cells = <1>; clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pmic_int_l>; rockchip,system-power-controller; @@ -169,7 +240,7 @@ }; vcc_18: LDO_REG1 { - regulator-name = "vdd_18"; + regulator-name = "vcc_18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; @@ -181,7 +252,7 @@ }; vcc18_emmc: LDO_REG2 { - regulator-name = "vcc_18emmc"; + regulator-name = "vcc18_emmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; @@ -207,6 +278,18 @@ }; }; +&i2s1 { + status = "okay"; + + i2s1_p0: port { + i2s1_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&codec_p0_0>; + }; + }; +}; + &io_domains { status = "okay"; @@ -220,6 +303,12 @@ }; &pinctrl { + ir { + ir_int: ir-int { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; @@ -245,6 +334,17 @@ status = "okay"; }; +&spdif { + pinctrl-0 = <&spdifm0_tx>; + status = "okay"; + + spdif_p0: port { + spdif_p0_0: endpoint { + remote-endpoint = <&dit_p0_0>; + }; + }; +}; + &spi0 { status = "okay"; @@ -257,10 +357,28 @@ }; }; +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + &uart2 { status = "okay"; }; +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + &usb20_otg { dr_mode = "host"; status = "okay"; @@ -273,3 +391,11 @@ &usb_host0_ohci { status = "okay"; }; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index 57719b82d13..945387e579f 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd */ #include @@ -8,6 +8,9 @@ #include #include #include +#include +#include +#include / { compatible = "rockchip,rk3328"; @@ -24,9 +27,8 @@ i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; - mmc0 = &emmc; - mmc1 = &sdmmc; - mmc2 = &sdmmc_ext; + ethernet0 = &gmac2io; + ethernet1 = &gmac2phy; }; cpus { @@ -35,29 +37,71 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; + dynamic-power-coefficient = <120>; enable-method = "psci"; -// clocks = <&cru ARMCLK>; + next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; }; + cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x1>; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; + dynamic-power-coefficient = <120>; enable-method = "psci"; + next-level-cache = <&l2>; + operating-points-v2 = <&cpu0_opp_table>; }; + cpu2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x2>; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; + dynamic-power-coefficient = <120>; enable-method = "psci"; + next-level-cache = <&l2>; + operating-points-v2 = <&cpu0_opp_table>; }; + cpu3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x3>; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; + dynamic-power-coefficient = <120>; enable-method = "psci"; + next-level-cache = <&l2>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <120>; + exit-latency-us = <250>; + min-residency-us = <900>; + }; + }; + + l2: l2-cache0 { + compatible = "cache"; }; }; @@ -65,39 +109,72 @@ compatible = "operating-points-v2"; opp-shared; - opp@408000000 { + opp-408000000 { opp-hz = /bits/ 64 <408000000>; opp-microvolt = <950000>; clock-latency-ns = <40000>; opp-suspend; }; - opp@600000000 { + opp-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <950000>; clock-latency-ns = <40000>; }; - opp@816000000 { + opp-816000000 { opp-hz = /bits/ 64 <816000000>; opp-microvolt = <1000000>; clock-latency-ns = <40000>; }; - opp@1008000000 { + opp-1008000000 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <1100000>; clock-latency-ns = <40000>; }; - opp@1200000000 { + opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1225000>; clock-latency-ns = <40000>; }; - opp@1296000000 { + opp-1296000000 { opp-hz = /bits/ 64 <1296000000>; opp-microvolt = <1300000>; clock-latency-ns = <40000>; }; }; + amba: bus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dmac: dmac@ff1f0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff1f0000 0x0 0x4000>; + interrupts = , + ; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + }; + + analog_sound: analog-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "Analog"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + + simple-audio-card,codec { + sound-dai = <&codec>; + }; + }; + arm-pmu { compatible = "arm,cortex-a53-pmu"; interrupts = , @@ -107,8 +184,29 @@ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "HDMI"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + psci { - compatible = "arm,psci-1.0"; + compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; }; @@ -134,8 +232,8 @@ clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; clock-names = "i2s_clk", "i2s_hclk"; dmas = <&dmac 11>, <&dmac 12>; - #dma-cells = <2>; dma-names = "tx", "rx"; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -146,8 +244,8 @@ clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; clock-names = "i2s_clk", "i2s_hclk"; dmas = <&dmac 14>, <&dmac 15>; - #dma-cells = <2>; dma-names = "tx", "rx"; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -158,16 +256,8 @@ clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; clock-names = "i2s_clk", "i2s_hclk"; dmas = <&dmac 0>, <&dmac 1>; - #dma-cells = <2>; dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2s2m0_mclk - &i2s2m0_sclk - &i2s2m0_lrcktx - &i2s2m0_lrckrx - &i2s2m0_sdo - &i2s2m0_sdi>; - pinctrl-1 = <&i2s2m0_sleep>; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -178,10 +268,31 @@ clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; clock-names = "mclk", "hclk"; dmas = <&dmac 10>; - #dma-cells = <1>; dma-names = "tx"; pinctrl-names = "default"; pinctrl-0 = <&spdifm2_tx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pdm: pdm@ff040000 { + compatible = "rockchip,pdm"; + reg = <0x0 0xff040000 0x0 0x1000>; + clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; + clock-names = "pdm_clk", "pdm_hclk"; + dmas = <&dmac 16>; + dma-names = "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pdmm0_clk + &pdmm0_sdi0 + &pdmm0_sdi1 + &pdmm0_sdi2 + &pdmm0_sdi3>; + pinctrl-1 = <&pdmm0_clk_sleep + &pdmm0_sdi0_sleep + &pdmm0_sdi1_sleep + &pdmm0_sdi2_sleep + &pdmm0_sdi3_sleep>; status = "disabled"; }; @@ -193,6 +304,39 @@ compatible = "rockchip,rk3328-io-voltage-domain"; status = "disabled"; }; + + grf_gpio: grf-gpio { + compatible = "rockchip,rk3328-grf-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + power: power-controller { + compatible = "rockchip,rk3328-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hevc@RK3328_PD_HEVC { + reg = ; + }; + pd_video@RK3328_PD_VIDEO { + reg = ; + }; + pd_vpu@RK3328_PD_VPU { + reg = ; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + }; + }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x5c8>; + mode-normal = ; + mode-recovery = ; + mode-bootloader = ; + mode-loader = ; + }; }; uart0: serial@ff110000 { @@ -201,12 +345,12 @@ interrupts = ; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; dmas = <&dmac 2>, <&dmac 3>; - #dma-cells = <2>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + reg-io-width = <4>; + reg-shift = <2>; status = "disabled"; }; @@ -215,13 +359,13 @@ reg = <0x0 0xff120000 0x0 0x100>; interrupts = ; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "sclk_uart", "pclk_uart"; - reg-shift = <2>; - reg-io-width = <4>; + clock-names = "baudclk", "apb_pclk"; dmas = <&dmac 4>, <&dmac 5>; - #dma-cells = <2>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; + reg-io-width = <4>; + reg-shift = <2>; status = "disabled"; }; @@ -231,22 +375,17 @@ interrupts = ; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; dmas = <&dmac 6>, <&dmac 7>; - #dma-cells = <2>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart2m1_xfer>; + reg-io-width = <4>; + reg-shift = <2>; status = "disabled"; }; - pmu: power-management@ff140000 { - compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd"; - reg = <0x0 0xff140000 0x0 0x1000>; - }; - i2c0: i2c@ff150000 { - compatible = "rockchip,rk3328-i2c"; + compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xff150000 0x0 0x1000>; interrupts = ; #address-cells = <1>; @@ -259,7 +398,7 @@ }; i2c1: i2c@ff160000 { - compatible = "rockchip,rk3328-i2c"; + compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xff160000 0x0 0x1000>; interrupts = ; #address-cells = <1>; @@ -272,7 +411,7 @@ }; i2c2: i2c@ff170000 { - compatible = "rockchip,rk3328-i2c"; + compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xff170000 0x0 0x1000>; interrupts = ; #address-cells = <1>; @@ -285,7 +424,7 @@ }; i2c3: i2c@ff180000 { - compatible = "rockchip,rk3328-i2c"; + compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xff180000 0x0 0x1000>; interrupts = ; #address-cells = <1>; @@ -306,7 +445,6 @@ clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; clock-names = "spiclk", "apb_pclk"; dmas = <&dmac 8>, <&dmac 9>; - #dma-cells = <2>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; @@ -317,28 +455,141 @@ compatible = "snps,dw-wdt"; reg = <0x0 0xff1a0000 0x0 0x100>; interrupts = ; + clocks = <&cru PCLK_WDT>; + }; + + pwm0: pwm@ff1b0000 { + compatible = "rockchip,rk3328-pwm"; + reg = <0x0 0xff1b0000 0x0 0x10>; + clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + #pwm-cells = <3>; status = "disabled"; }; - amba { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + pwm1: pwm@ff1b0010 { + compatible = "rockchip,rk3328-pwm"; + reg = <0x0 0xff1b0010 0x0 0x10>; + clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; - dmac: dmac@ff1f0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff1f0000 0x0 0x4000>; - interrupts = , - ; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - #dma-cells = <1>; + pwm2: pwm@ff1b0020 { + compatible = "rockchip,rk3328-pwm"; + reg = <0x0 0xff1b0020 0x0 0x10>; + clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@ff1b0030 { + compatible = "rockchip,rk3328-pwm"; + reg = <0x0 0xff1b0030 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwmir_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <20>; + polling-delay = <1000>; + sustainable-power = <1000>; + + thermal-sensors = <&tsadc 0>; + + trips { + threshold: trip-point0 { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + target: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + soc_crit: soc-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; + }; + }; + + }; + + tsadc: tsadc@ff250000 { + compatible = "rockchip,rk3328-tsadc"; + reg = <0x0 0xff250000 0x0 0x100>; + interrupts = ; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <50000>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&otp_gpio>; + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_gpio>; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + rockchip,grf = <&grf>; + rockchip,hw-tshut-temp = <100000>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + efuse: efuse@ff260000 { + compatible = "rockchip,rk3328-efuse"; + reg = <0x0 0xff260000 0x0 0x50>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru SCLK_EFUSE>; + clock-names = "pclk_efuse"; + rockchip,efuse-size = <0x20>; + + /* Data cells */ + efuse_id: id@7 { + reg = <0x07 0x10>; + }; + cpu_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + logic_leakage: logic-leakage@19 { + reg = <0x19 0x1>; + }; + efuse_cpu_version: cpu-version@1a { + reg = <0x1a 0x1>; + bits = <3 3>; }; }; - saradc: saradc@ff280000 { - compatible = "rockchip,rk3328-saradc", "rockchip,saradc"; + saradc: adc@ff280000 { + compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; reg = <0x0 0xff280000 0x0 0x100>; interrupts = ; #io-channel-cells = <1>; @@ -349,6 +600,169 @@ status = "disabled"; }; + gpu: gpu@ff300000 { + compatible = "rockchip,rk3328-mali", "arm,mali-450"; + reg = <0x0 0xff300000 0x0 0x40000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1"; + clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; + clock-names = "bus", "core"; + resets = <&cru SRST_GPU_A>; + }; + + h265e_mmu: iommu@ff330200 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff330200 0 0x100>; + interrupts = ; + interrupt-names = "h265e_mmu"; + clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + vepu_mmu: iommu@ff340800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff340800 0x0 0x40>; + interrupts = ; + interrupt-names = "vepu_mmu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + vpu: video-codec@ff350000 { + compatible = "rockchip,rk3328-vpu"; + reg = <0x0 0xff350000 0x0 0x800>; + interrupts = ; + interrupt-names = "vdpu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; + power-domains = <&power RK3328_PD_VPU>; + }; + + vpu_mmu: iommu@ff350800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff350800 0x0 0x40>; + interrupts = ; + interrupt-names = "vpu_mmu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3328_PD_VPU>; + }; + + rkvdec_mmu: iommu@ff360480 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; + interrupts = ; + interrupt-names = "rkvdec_mmu"; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + vop: vop@ff370000 { + compatible = "rockchip,rk3328-vop"; + reg = <0x0 0xff370000 0x0 0x3efc>; + interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vop_mmu>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop>; + }; + }; + }; + + vop_mmu: iommu@ff373f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff373f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + hdmi: hdmi@ff3c0000 { + compatible = "rockchip,rk3328-dw-hdmi"; + reg = <0x0 0xff3c0000 0x0 0x20000>; + reg-io-width = <4>; + interrupts = , + ; + clocks = <&cru PCLK_HDMI>, + <&cru SCLK_HDMI_SFC>, + <&cru SCLK_RTC32K>; + clock-names = "iahb", + "isfr", + "cec"; + phys = <&hdmiphy>; + phy-names = "hdmi"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + hdmi_in: port { + hdmi_in_vop: endpoint { + remote-endpoint = <&vop_out_hdmi>; + }; + }; + }; + }; + + codec: codec@ff410000 { + compatible = "rockchip,rk3328-codec"; + reg = <0x0 0xff410000 0x0 0x1000>; + clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; + clock-names = "pclk", "mclk"; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + hdmiphy: phy@ff430000 { + compatible = "rockchip,rk3328-hdmi-phy"; + reg = <0x0 0xff430000 0x0 0x10000>; + interrupts = ; + clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; + clock-names = "sysclk", "refoclk", "refpclk"; + clock-output-names = "hdmi_phy"; + #clock-cells = <0>; + nvmem-cells = <&efuse_cpu_version>; + nvmem-cell-names = "cpu-version"; + #phy-cells = <0>; + status = "disabled"; + }; + cru: clock-controller@ff440000 { compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; reg = <0x0 0xff440000 0x0 0x1000>; @@ -356,6 +770,12 @@ #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = + /* + * CPLL should run at 1200, but that is to high for + * the initial dividers of most of its children. + * We need set cpll child clk div first, + * and then set the cpll frequency. + */ <&cru DCLK_LCDC>, <&cru SCLK_PDM>, <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, <&cru SCLK_UART1>, <&cru SCLK_UART2>, @@ -371,15 +791,7 @@ <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, <&cru HCLK_PERI>, <&cru PCLK_PERI>, - <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>, - <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>, - <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, - <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, - <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, - <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, - <&cru SCLK_EFUSE>, <&cru PCLK_DDR>, - <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, - <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>; + <&cru SCLK_RTC32K>; assigned-clock-parents = <&cru HDMIPHY>, <&cru PLL_APLL>, <&cru PLL_GPLL>, <&xin24m>, @@ -400,55 +812,85 @@ <150000000>, <75000000>, <75000000>, <150000000>, <75000000>, <75000000>, - <300000000>, <100000000>, - <300000000>, <200000000>, - <400000000>, <500000000>, - <200000000>, <300000000>, - <300000000>, <250000000>, - <200000000>, <100000000>, - <24000000>, <100000000>, - <150000000>, <50000000>, - <32768>, <32768>; + <32768>; }; - sdmmc: rksdmmc@ff500000 { + usb2phy_grf: syscon@ff450000 { + compatible = "rockchip,rk3328-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xff450000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy: usb2-phy@100 { + compatible = "rockchip,rk3328-usb2phy"; + reg = <0x100 0x10>; + clocks = <&xin24m>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy"; + #clock-cells = <0>; + assigned-clocks = <&cru USB480M>; + assigned-clock-parents = <&u2phy>; + status = "disabled"; + + u2phy_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + + u2phy_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "disabled"; + }; + }; + }; + + sdmmc: mmc@ff500000 { compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff500000 0x0 0x4000>; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; - fifo-depth = <0x100>; interrupts = ; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; status = "disabled"; }; - sdio: dwmmc@ff510000 { + sdio: mmc@ff510000 { compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff510000 0x0 0x4000>; - max-frequency = <150000000>; + interrupts = ; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; - interrupts = ; + max-frequency = <150000000>; status = "disabled"; }; - emmc: rksdmmc@ff520000 { + emmc: mmc@ff520000 { compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff520000 0x0 0x4000>; - max-frequency = <150000000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; - clock-names = "biu", "ciu"; - fifo-depth = <0x100>; interrupts = ; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; status = "disabled"; }; gmac2io: ethernet@ff540000 { compatible = "rockchip,rk3328-gmac"; reg = <0x0 0xff540000 0x0 0x10000>; - rockchip,grf = <&grf>; interrupts = ; interrupt-names = "macirq"; clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, @@ -461,13 +903,56 @@ "pclk_mac"; resets = <&cru SRST_GMAC2IO_A>; reset-names = "stmmaceth"; + rockchip,grf = <&grf>; + snps,txpbl = <0x4>; status = "disabled"; }; + gmac2phy: ethernet@ff550000 { + compatible = "rockchip,rk3328-gmac"; + reg = <0x0 0xff550000 0x0 0x10000>; + rockchip,grf = <&grf>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, + <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, + <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, + <&cru SCLK_MAC2PHY_OUT>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "aclk_mac", "pclk_mac", + "clk_macphy"; + resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>; + reset-names = "stmmaceth", "mac-phy"; + phy-mode = "rmii"; + phy-handle = <&phy>; + snps,txpbl = <0x4>; + status = "disabled"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy: phy@0 { + compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + clocks = <&cru SCLK_MAC2PHY_OUT>; + resets = <&cru SRST_MACPHY>; + pinctrl-names = "default"; + pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; + phy-is-integrated; + }; + }; + }; + usb_host0_ehci: usb@ff5c0000 { compatible = "generic-ehci"; reg = <0x0 0xff5c0000 0x0 0x10000>; interrupts = ; + clocks = <&cru HCLK_HOST0>, <&u2phy>; + phys = <&u2phy_host>; + phy-names = "usb"; status = "disabled"; }; @@ -475,30 +960,38 @@ compatible = "generic-ohci"; reg = <0x0 0xff5d0000 0x0 0x10000>; interrupts = ; + clocks = <&cru HCLK_HOST0>, <&u2phy>; + phys = <&u2phy_host>; + phy-names = "usb"; status = "disabled"; }; + /* + * U-boot Specific Change + * + * The OTG controller must come after the USB host pair for it + * to work. This is likely due to lack of support for the USB + * PHYs. This must be manually changed after each device tree + * sync. There is no clean way to handle this in -u-boot.dtsi + * files. + */ usb20_otg: usb@ff580000 { compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", "snps,dwc2"; reg = <0x0 0xff580000 0x0 0x40000>; interrupts = ; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; status = "disabled"; }; - sdmmc_ext: rksdmmc@ff5f0000 { - compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff5f0000 0x0 0x4000>; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; - fifo-depth = <0x100>; - interrupts = ; - status = "disabled"; - }; - - gic: interrupt-controller@ffb70000 { + gic: interrupt-controller@ff811000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; #address-cells = <0>; @@ -646,654 +1139,576 @@ i2c0 { i2c0_xfer: i2c0-xfer { - rockchip,pins = - <2 24 RK_FUNC_1 &pcfg_pull_none>, - <2 25 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, + <2 RK_PD1 1 &pcfg_pull_none>; }; }; i2c1 { i2c1_xfer: i2c1-xfer { - rockchip,pins = - <2 4 RK_FUNC_2 &pcfg_pull_none>, - <2 5 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, + <2 RK_PA5 2 &pcfg_pull_none>; }; }; i2c2 { i2c2_xfer: i2c2-xfer { - rockchip,pins = - <2 13 RK_FUNC_1 &pcfg_pull_none>, - <2 14 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, + <2 RK_PB6 1 &pcfg_pull_none>; }; }; i2c3 { i2c3_xfer: i2c3-xfer { - rockchip,pins = - <0 5 RK_FUNC_2 &pcfg_pull_none>, - <0 6 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, + <0 RK_PA6 2 &pcfg_pull_none>; }; i2c3_gpio: i2c3-gpio { rockchip,pins = - <0 5 RK_FUNC_GPIO &pcfg_pull_none>, - <0 6 RK_FUNC_GPIO &pcfg_pull_none>; + <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; hdmi_i2c { hdmii2c_xfer: hdmii2c-xfer { + rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, + <0 RK_PA6 1 &pcfg_pull_none>; + }; + }; + + pdm-0 { + pdmm0_clk: pdmm0-clk { + rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; + }; + + pdmm0_fsync: pdmm0-fsync { + rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; + }; + + pdmm0_sdi0: pdmm0-sdi0 { + rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; + }; + + pdmm0_sdi1: pdmm0-sdi1 { + rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; + }; + + pdmm0_sdi2: pdmm0-sdi2 { + rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; + }; + + pdmm0_sdi3: pdmm0-sdi3 { + rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; + }; + + pdmm0_clk_sleep: pdmm0-clk-sleep { rockchip,pins = - <0 5 RK_FUNC_1 &pcfg_pull_none>, - <0 6 RK_FUNC_1 &pcfg_pull_none>; + <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { + rockchip,pins = + <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { + rockchip,pins = + <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { + rockchip,pins = + <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { + rockchip,pins = + <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdmm0_fsync_sleep: pdmm0-fsync-sleep { + rockchip,pins = + <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; + }; + }; + + tsadc { + otp_gpio: otp-gpio { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otp_out: otp-out { + rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; }; }; uart0 { uart0_xfer: uart0-xfer { - rockchip,pins = - <1 9 RK_FUNC_1 &pcfg_pull_up>, - <1 8 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>, + <1 RK_PB0 1 &pcfg_pull_none>; }; uart0_cts: uart0-cts { - rockchip,pins = - <1 11 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; }; uart0_rts: uart0-rts { - rockchip,pins = - <1 10 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; }; uart0_rts_gpio: uart0-rts-gpio { - rockchip,pins = - <1 10 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; uart1 { uart1_xfer: uart1-xfer { - rockchip,pins = - <3 4 RK_FUNC_4 &pcfg_pull_up>, - <3 6 RK_FUNC_4 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>, + <3 RK_PA6 4 &pcfg_pull_none>; }; uart1_cts: uart1-cts { - rockchip,pins = - <3 7 RK_FUNC_4 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; }; uart1_rts: uart1-rts { - rockchip,pins = - <3 5 RK_FUNC_4 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; }; uart1_rts_gpio: uart1-rts-gpio { - rockchip,pins = - <3 5 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; uart2-0 { uart2m0_xfer: uart2m0-xfer { - rockchip,pins = - <1 0 RK_FUNC_2 &pcfg_pull_up>, - <1 1 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>, + <1 RK_PA1 2 &pcfg_pull_none>; }; }; uart2-1 { uart2m1_xfer: uart2m1-xfer { - rockchip,pins = - <2 0 RK_FUNC_1 &pcfg_pull_up>, - <2 1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>, + <2 RK_PA1 1 &pcfg_pull_none>; }; }; spi0-0 { spi0m0_clk: spi0m0-clk { - rockchip,pins = - <2 8 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; }; spi0m0_cs0: spi0m0-cs0 { - rockchip,pins = - <2 11 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; }; spi0m0_tx: spi0m0-tx { - rockchip,pins = - <2 9 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; }; spi0m0_rx: spi0m0-rx { - rockchip,pins = - <2 10 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; }; spi0m0_cs1: spi0m0-cs1 { - rockchip,pins = - <2 12 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; }; }; spi0-1 { spi0m1_clk: spi0m1-clk { - rockchip,pins = - <3 23 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; }; spi0m1_cs0: spi0m1-cs0 { - rockchip,pins = - <3 26 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; }; spi0m1_tx: spi0m1-tx { - rockchip,pins = - <3 25 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; }; spi0m1_rx: spi0m1-rx { - rockchip,pins = - <3 24 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; }; spi0m1_cs1: spi0m1-cs1 { - rockchip,pins = - <3 27 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; }; }; spi0-2 { spi0m2_clk: spi0m2-clk { - rockchip,pins = - <3 0 RK_FUNC_4 &pcfg_pull_up>; + rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; }; spi0m2_cs0: spi0m2-cs0 { - rockchip,pins = - <3 8 RK_FUNC_3 &pcfg_pull_up>; + rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; }; spi0m2_tx: spi0m2-tx { - rockchip,pins = - <3 1 RK_FUNC_4 &pcfg_pull_up>; + rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; }; spi0m2_rx: spi0m2-rx { - rockchip,pins = - <3 2 RK_FUNC_4 &pcfg_pull_up>; + rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; }; }; i2s1 { i2s1_mclk: i2s1-mclk { - rockchip,pins = - <2 15 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; }; i2s1_sclk: i2s1-sclk { - rockchip,pins = - <2 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; }; i2s1_lrckrx: i2s1-lrckrx { - rockchip,pins = - <2 16 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; }; i2s1_lrcktx: i2s1-lrcktx { - rockchip,pins = - <2 17 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; }; i2s1_sdi: i2s1-sdi { - rockchip,pins = - <2 19 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; }; i2s1_sdo: i2s1-sdo { - rockchip,pins = - <2 23 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; }; i2s1_sdio1: i2s1-sdio1 { - rockchip,pins = - <2 20 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; }; i2s1_sdio2: i2s1-sdio2 { - rockchip,pins = - <2 21 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; }; i2s1_sdio3: i2s1-sdio3 { - rockchip,pins = - <2 22 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; }; i2s1_sleep: i2s1-sleep { rockchip,pins = - <2 15 RK_FUNC_GPIO &pcfg_input_high>, - <2 16 RK_FUNC_GPIO &pcfg_input_high>, - <2 17 RK_FUNC_GPIO &pcfg_input_high>, - <2 18 RK_FUNC_GPIO &pcfg_input_high>, - <2 19 RK_FUNC_GPIO &pcfg_input_high>, - <2 20 RK_FUNC_GPIO &pcfg_input_high>, - <2 21 RK_FUNC_GPIO &pcfg_input_high>, - <2 22 RK_FUNC_GPIO &pcfg_input_high>, - <2 23 RK_FUNC_GPIO &pcfg_input_high>; + <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; }; }; i2s2-0 { i2s2m0_mclk: i2s2m0-mclk { - rockchip,pins = - <1 21 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; }; i2s2m0_sclk: i2s2m0-sclk { - rockchip,pins = - <1 22 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; }; i2s2m0_lrckrx: i2s2m0-lrckrx { - rockchip,pins = - <1 26 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; }; i2s2m0_lrcktx: i2s2m0-lrcktx { - rockchip,pins = - <1 23 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; }; i2s2m0_sdi: i2s2m0-sdi { - rockchip,pins = - <1 24 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; }; i2s2m0_sdo: i2s2m0-sdo { - rockchip,pins = - <1 25 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; }; i2s2m0_sleep: i2s2m0-sleep { rockchip,pins = - <1 21 RK_FUNC_GPIO &pcfg_input_high>, - <1 22 RK_FUNC_GPIO &pcfg_input_high>, - <1 26 RK_FUNC_GPIO &pcfg_input_high>, - <1 23 RK_FUNC_GPIO &pcfg_input_high>, - <1 24 RK_FUNC_GPIO &pcfg_input_high>, - <1 25 RK_FUNC_GPIO &pcfg_input_high>; + <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, + <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, + <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, + <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, + <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, + <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; }; }; i2s2-1 { i2s2m1_mclk: i2s2m1-mclk { - rockchip,pins = - <1 21 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; }; i2s2m1_sclk: i2s2m1-sclk { - rockchip,pins = - <3 0 RK_FUNC_6 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; }; i2s2m1_lrckrx: i2sm1-lrckrx { - rockchip,pins = - <3 8 RK_FUNC_6 &pcfg_pull_none>; + rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; }; i2s2m1_lrcktx: i2s2m1-lrcktx { - rockchip,pins = - <3 8 RK_FUNC_4 &pcfg_pull_none>; + rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; }; i2s2m1_sdi: i2s2m1-sdi { - rockchip,pins = - <3 2 RK_FUNC_6 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; }; i2s2m1_sdo: i2s2m1-sdo { - rockchip,pins = - <3 1 RK_FUNC_6 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; }; i2s2m1_sleep: i2s2m1-sleep { rockchip,pins = - <1 21 RK_FUNC_GPIO &pcfg_input_high>, - <3 0 RK_FUNC_GPIO &pcfg_input_high>, - <3 8 RK_FUNC_GPIO &pcfg_input_high>, - <3 2 RK_FUNC_GPIO &pcfg_input_high>, - <3 1 RK_FUNC_GPIO &pcfg_input_high>; + <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, + <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, + <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, + <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, + <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; }; }; spdif-0 { spdifm0_tx: spdifm0-tx { - rockchip,pins = - <0 27 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; }; }; spdif-1 { spdifm1_tx: spdifm1-tx { - rockchip,pins = - <2 17 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; }; }; spdif-2 { spdifm2_tx: spdifm2-tx { - rockchip,pins = - <0 2 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; }; }; sdmmc0-0 { sdmmc0m0_pwren: sdmmc0m0-pwren { - rockchip,pins = - <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>; + rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; }; sdmmc0m0_gpio: sdmmc0m0-gpio { - rockchip,pins = - <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; }; }; sdmmc0-1 { sdmmc0m1_pwren: sdmmc0m1-pwren { - rockchip,pins = - <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>; + rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; }; sdmmc0m1_gpio: sdmmc0m1-gpio { - rockchip,pins = - <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; }; }; sdmmc0 { sdmmc0_clk: sdmmc0-clk { - rockchip,pins = - <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>; + rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; }; sdmmc0_cmd: sdmmc0-cmd { - rockchip,pins = - <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>; + rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; }; sdmmc0_dectn: sdmmc0-dectn { - rockchip,pins = - <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>; + rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; }; sdmmc0_wrprt: sdmmc0-wrprt { - rockchip,pins = - <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>; + rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; }; sdmmc0_bus1: sdmmc0-bus1 { - rockchip,pins = - <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>; + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; }; sdmmc0_bus4: sdmmc0-bus4 { - rockchip,pins = - <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>, - <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>, - <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>, - <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>; + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, + <1 RK_PA1 1 &pcfg_pull_up_8ma>, + <1 RK_PA2 1 &pcfg_pull_up_8ma>, + <1 RK_PA3 1 &pcfg_pull_up_8ma>; }; sdmmc0_gpio: sdmmc0-gpio { rockchip,pins = - <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; }; }; sdmmc0ext { sdmmc0ext_clk: sdmmc0ext-clk { - rockchip,pins = - <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>; + rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; }; sdmmc0ext_cmd: sdmmc0ext-cmd { - rockchip,pins = - <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>; + rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; }; sdmmc0ext_wrprt: sdmmc0ext-wrprt { - rockchip,pins = - <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>; + rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; }; sdmmc0ext_dectn: sdmmc0ext-dectn { - rockchip,pins = - <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>; + rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; }; sdmmc0ext_bus1: sdmmc0ext-bus1 { - rockchip,pins = - <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>; + rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; }; sdmmc0ext_bus4: sdmmc0ext-bus4 { rockchip,pins = - <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>, - <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>, - <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>, - <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>; + <3 RK_PA4 3 &pcfg_pull_up_4ma>, + <3 RK_PA5 3 &pcfg_pull_up_4ma>, + <3 RK_PA6 3 &pcfg_pull_up_4ma>, + <3 RK_PA7 3 &pcfg_pull_up_4ma>; }; sdmmc0ext_gpio: sdmmc0ext-gpio { rockchip,pins = - <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; }; }; sdmmc1 { sdmmc1_clk: sdmmc1-clk { - rockchip,pins = - <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>; + rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; }; sdmmc1_cmd: sdmmc1-cmd { - rockchip,pins = - <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>; + rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; }; sdmmc1_pwren: sdmmc1-pwren { - rockchip,pins = - <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>; + rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; }; sdmmc1_wrprt: sdmmc1-wrprt { - rockchip,pins = - <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>; + rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; }; sdmmc1_dectn: sdmmc1-dectn { - rockchip,pins = - <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>; + rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; }; sdmmc1_bus1: sdmmc1-bus1 { - rockchip,pins = - <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>; + rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; }; sdmmc1_bus4: sdmmc1-bus4 { - rockchip,pins = - <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>, - <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>, - <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>, - <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>; + rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, + <1 RK_PB7 1 &pcfg_pull_up_8ma>, + <1 RK_PC0 1 &pcfg_pull_up_8ma>, + <1 RK_PC1 1 &pcfg_pull_up_8ma>; }; sdmmc1_gpio: sdmmc1-gpio { rockchip,pins = - <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; }; }; emmc { emmc_clk: emmc-clk { - rockchip,pins = - <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>; + rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; }; emmc_cmd: emmc-cmd { - rockchip,pins = - <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>; + rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; }; emmc_pwren: emmc-pwren { - rockchip,pins = - <3 22 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; }; emmc_rstnout: emmc-rstnout { - rockchip,pins = - <3 20 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; }; emmc_bus1: emmc-bus1 { - rockchip,pins = - <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>; + rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; }; emmc_bus4: emmc-bus4 { rockchip,pins = - <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, - <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, - <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, - <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>; + <0 RK_PA7 2 &pcfg_pull_up_12ma>, + <2 RK_PD4 2 &pcfg_pull_up_12ma>, + <2 RK_PD5 2 &pcfg_pull_up_12ma>, + <2 RK_PD6 2 &pcfg_pull_up_12ma>; }; emmc_bus8: emmc-bus8 { rockchip,pins = - <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, - <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, - <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, - <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>, - <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>, - <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>, - <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>, - <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>; + <0 RK_PA7 2 &pcfg_pull_up_12ma>, + <2 RK_PD4 2 &pcfg_pull_up_12ma>, + <2 RK_PD5 2 &pcfg_pull_up_12ma>, + <2 RK_PD6 2 &pcfg_pull_up_12ma>, + <2 RK_PD7 2 &pcfg_pull_up_12ma>, + <3 RK_PC0 2 &pcfg_pull_up_12ma>, + <3 RK_PC1 2 &pcfg_pull_up_12ma>, + <3 RK_PC2 2 &pcfg_pull_up_12ma>; }; }; pwm0 { pwm0_pin: pwm0-pin { - rockchip,pins = - <2 4 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; }; }; pwm1 { pwm1_pin: pwm1-pin { - rockchip,pins = - <2 5 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; }; }; pwm2 { pwm2_pin: pwm2-pin { - rockchip,pins = - <2 6 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; }; }; pwmir { pwmir_pin: pwmir-pin { - rockchip,pins = - <2 2 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - gmac-0 { - rgmiim0_pins: rgmiim0-pins { - rockchip,pins = - /* mac_txclk */ - <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>, - /* mac_rxclk */ - <0 10 RK_FUNC_1 &pcfg_pull_none>, - /* mac_mdio */ - <0 11 RK_FUNC_1 &pcfg_pull_none>, - /* mac_txen */ - <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, - /* mac_clk */ - <0 24 RK_FUNC_1 &pcfg_pull_none>, - /* mac_rxdv */ - <0 25 RK_FUNC_1 &pcfg_pull_none>, - /* mac_mdc */ - <0 19 RK_FUNC_1 &pcfg_pull_none>, - /* mac_rxd1 */ - <0 14 RK_FUNC_1 &pcfg_pull_none>, - /* mac_rxd0 */ - <0 15 RK_FUNC_1 &pcfg_pull_none>, - /* mac_txd1 */ - <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, - /* mac_txd0 */ - <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>, - /* mac_rxd3 */ - <0 20 RK_FUNC_1 &pcfg_pull_none>, - /* mac_rxd2 */ - <0 21 RK_FUNC_1 &pcfg_pull_none>, - /* mac_txd3 */ - <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>, - /* mac_txd2 */ - <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>; - }; - - rmiim0_pins: rmiim0-pins { - rockchip,pins = - /* mac_mdio */ - <0 11 RK_FUNC_1 &pcfg_pull_none>, - /* mac_txen */ - <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, - /* mac_clk */ - <0 24 RK_FUNC_1 &pcfg_pull_none>, - /* mac_rxer */ - <0 13 RK_FUNC_1 &pcfg_pull_none>, - /* mac_rxdv */ - <0 25 RK_FUNC_1 &pcfg_pull_none>, - /* mac_mdc */ - <0 19 RK_FUNC_1 &pcfg_pull_none>, - /* mac_rxd1 */ - <0 14 RK_FUNC_1 &pcfg_pull_none>, - /* mac_rxd0 */ - <0 15 RK_FUNC_1 &pcfg_pull_none>, - /* mac_txd1 */ - <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, - /* mac_txd0 */ - <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>; + rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; }; }; @@ -1301,157 +1716,128 @@ rgmiim1_pins: rgmiim1-pins { rockchip,pins = /* mac_txclk */ - <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>, + <1 RK_PB4 2 &pcfg_pull_none_8ma>, /* mac_rxclk */ - <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PB5 2 &pcfg_pull_none_4ma>, /* mac_mdio */ - <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PC3 2 &pcfg_pull_none_4ma>, /* mac_txen */ - <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, + <1 RK_PD1 2 &pcfg_pull_none_8ma>, /* mac_clk */ - <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PC5 2 &pcfg_pull_none_4ma>, /* mac_rxdv */ - <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PC6 2 &pcfg_pull_none_4ma>, /* mac_mdc */ - <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PC7 2 &pcfg_pull_none_4ma>, /* mac_rxd1 */ - <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PB2 2 &pcfg_pull_none_4ma>, /* mac_rxd0 */ - <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PB3 2 &pcfg_pull_none_4ma>, /* mac_txd1 */ - <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, + <1 RK_PB0 2 &pcfg_pull_none_8ma>, /* mac_txd0 */ - <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, + <1 RK_PB1 2 &pcfg_pull_none_8ma>, /* mac_rxd3 */ - <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PB6 2 &pcfg_pull_none_4ma>, /* mac_rxd2 */ - <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PB7 2 &pcfg_pull_none_4ma>, /* mac_txd3 */ - <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>, + <1 RK_PC0 2 &pcfg_pull_none_8ma>, /* mac_txd2 */ - <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>, + <1 RK_PC1 2 &pcfg_pull_none_8ma>, /* mac_txclk */ - <0 8 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PB0 1 &pcfg_pull_none_8ma>, /* mac_txen */ - <0 12 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PB4 1 &pcfg_pull_none_8ma>, /* mac_clk */ - <0 24 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PD0 1 &pcfg_pull_none_4ma>, /* mac_txd1 */ - <0 16 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PC0 1 &pcfg_pull_none_8ma>, /* mac_txd0 */ - <0 17 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PC1 1 &pcfg_pull_none_8ma>, /* mac_txd3 */ - <0 23 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PC7 1 &pcfg_pull_none_8ma>, /* mac_txd2 */ - <0 22 RK_FUNC_1 &pcfg_pull_none>; + <0 RK_PC6 1 &pcfg_pull_none_8ma>; }; rmiim1_pins: rmiim1-pins { rockchip,pins = /* mac_mdio */ - <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PC3 2 &pcfg_pull_none_2ma>, /* mac_txen */ - <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, + <1 RK_PD1 2 &pcfg_pull_none_12ma>, /* mac_clk */ - <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PC5 2 &pcfg_pull_none_2ma>, /* mac_rxer */ - <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PD0 2 &pcfg_pull_none_2ma>, /* mac_rxdv */ - <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PC6 2 &pcfg_pull_none_2ma>, /* mac_mdc */ - <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PC7 2 &pcfg_pull_none_2ma>, /* mac_rxd1 */ - <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PB2 2 &pcfg_pull_none_2ma>, /* mac_rxd0 */ - <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PB3 2 &pcfg_pull_none_2ma>, /* mac_txd1 */ - <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, + <1 RK_PB0 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ - <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, + <1 RK_PB1 2 &pcfg_pull_none_12ma>, /* mac_mdio */ - <0 11 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PB3 1 &pcfg_pull_none>, /* mac_txen */ - <0 12 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PB4 1 &pcfg_pull_none>, /* mac_clk */ - <0 24 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PD0 1 &pcfg_pull_none>, /* mac_mdc */ - <0 19 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PC3 1 &pcfg_pull_none>, /* mac_txd1 */ - <0 16 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PC0 1 &pcfg_pull_none>, /* mac_txd0 */ - <0 17 RK_FUNC_1 &pcfg_pull_none>; + <0 RK_PC1 1 &pcfg_pull_none>; }; }; gmac2phy { - fephyled_speed100: fephyled-speed100 { - rockchip,pins = - <0 31 RK_FUNC_1 &pcfg_pull_none>; - }; - fephyled_speed10: fephyled-speed10 { - rockchip,pins = - <0 30 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; }; fephyled_duplex: fephyled-duplex { - rockchip,pins = - <0 30 RK_FUNC_2 &pcfg_pull_none>; - }; - - fephyled_rxm0: fephyled-rxm0 { - rockchip,pins = - <0 29 RK_FUNC_1 &pcfg_pull_none>; - }; - - fephyled_txm0: fephyled-txm0 { - rockchip,pins = - <0 29 RK_FUNC_2 &pcfg_pull_none>; - }; - - fephyled_linkm0: fephyled-linkm0 { - rockchip,pins = - <0 28 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; }; fephyled_rxm1: fephyled-rxm1 { - rockchip,pins = - <2 25 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; }; fephyled_txm1: fephyled-txm1 { - rockchip,pins = - <2 25 RK_FUNC_3 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; }; fephyled_linkm1: fephyled-linkm1 { - rockchip,pins = - <2 24 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; }; }; tsadc_pin { tsadc_int: tsadc-int { - rockchip,pins = - <2 13 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; }; tsadc_gpio: tsadc-gpio { - rockchip,pins = - <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; hdmi_pin { hdmi_cec: hdmi-cec { - rockchip,pins = - <0 3 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; }; hdmi_hpd: hdmi-hpd { - rockchip,pins = - <0 4 RK_FUNC_1 &pcfg_pull_down>; + rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; }; }; @@ -1459,29 +1845,29 @@ dvp_d2d9_m0:dvp-d2d9-m0 { rockchip,pins = /* cif_d0 */ - <3 4 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA4 2 &pcfg_pull_none>, /* cif_d1 */ - <3 5 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA5 2 &pcfg_pull_none>, /* cif_d2 */ - <3 6 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA6 2 &pcfg_pull_none>, /* cif_d3 */ - <3 7 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA7 2 &pcfg_pull_none>, /* cif_d4 */ - <3 8 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PB0 2 &pcfg_pull_none>, /* cif_d5m0 */ - <3 9 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PB1 2 &pcfg_pull_none>, /* cif_d6m0 */ - <3 10 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PB2 2 &pcfg_pull_none>, /* cif_d7m0 */ - <3 11 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PB3 2 &pcfg_pull_none>, /* cif_href */ - <3 1 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA1 2 &pcfg_pull_none>, /* cif_vsync */ - <3 0 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA0 2 &pcfg_pull_none>, /* cif_clkoutm0 */ - <3 3 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA3 2 &pcfg_pull_none>, /* cif_clkin */ - <3 2 RK_FUNC_2 &pcfg_pull_none>; + <3 RK_PA2 2 &pcfg_pull_none>; }; }; @@ -1489,29 +1875,29 @@ dvp_d2d9_m1:dvp-d2d9-m1 { rockchip,pins = /* cif_d0 */ - <3 4 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA4 2 &pcfg_pull_none>, /* cif_d1 */ - <3 5 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA5 2 &pcfg_pull_none>, /* cif_d2 */ - <3 6 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA6 2 &pcfg_pull_none>, /* cif_d3 */ - <3 7 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA7 2 &pcfg_pull_none>, /* cif_d4 */ - <3 8 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PB0 2 &pcfg_pull_none>, /* cif_d5m1 */ - <2 16 RK_FUNC_4 &pcfg_pull_none>, + <2 RK_PC0 4 &pcfg_pull_none>, /* cif_d6m1 */ - <2 17 RK_FUNC_4 &pcfg_pull_none>, + <2 RK_PC1 4 &pcfg_pull_none>, /* cif_d7m1 */ - <2 18 RK_FUNC_4 &pcfg_pull_none>, + <2 RK_PC2 4 &pcfg_pull_none>, /* cif_href */ - <3 1 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA1 2 &pcfg_pull_none>, /* cif_vsync */ - <3 0 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA0 2 &pcfg_pull_none>, /* cif_clkoutm1 */ - <2 15 RK_FUNC_4 &pcfg_pull_none>, + <2 RK_PB7 4 &pcfg_pull_none>, /* cif_clkin */ - <3 2 RK_FUNC_2 &pcfg_pull_none>; + <3 RK_PA2 2 &pcfg_pull_none>; }; }; }; From bab972948e152e468fa5ab34764769fc4cddcaab Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 27 Apr 2020 14:52:53 +0800 Subject: [PATCH 040/237] rockchip: rk3328: Add support for ROC-RK3328-CC board The ROC-RK3328-CC from Firefly and Libre Computer Project is a credit card size development board based on the Rockchip RK3328 SoC, with: - 1/2/4 GB DDR4 DRAM - eMMC connector for optional module - micro SD card slot - 1 x USB 3.0 host port - 2 x USB 2.0 host port - 1 x USB 2.0 OTG port - HDMI video output - TRRS connector with audio and composite video output - gigabit Ethernet - consumer IR receiver - debug UART pins The ROC-RK3328-CC has the enable pin of the SD card power switch tied to GPIO_0_D6. This pin also has the function SDMMC0_PWREN, which is muxed by default. SDMMC0_PWREN is an active high signal controlled by the MMC controller, however the switch enable is active low, and pulled low (enabled) by default to make things work on boot. As such, we need to mux away from SDMMC0_PWREN and use GPIO to enable power to the card. The default GPIO state for the pin is pull-down and input, which doesn't require extra configuration when paired with the external pull-down and active low switch. Deal with this by enabling regulator support in SPL, and setting "u-boot,dm-spl" for the regulator and other device nodes needed for muxing the pin. The device tree file is synced from the Linux kernel next-20200324. Signed-off-by: Chen-Yu Tsai Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 47 ++++ arch/arm/dts/rk3328-roc-cc.dts | 354 +++++++++++++++++++++++++ board/rockchip/evb_rk3328/MAINTAINERS | 7 + configs/roc-cc-rk3328_defconfig | 102 +++++++ doc/README.rockchip | 4 +- 6 files changed, 514 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3328-roc-cc-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-roc-cc.dts create mode 100644 configs/roc-cc-rk3328_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index af7d804b666..a683525e7c6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-evb.dtb \ + rk3328-roc-cc.dtb \ rk3328-rock64.dtb dtb-$(CONFIG_ROCKCHIP_RK3368) += \ diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi new file mode 100644 index 00000000000..e929d86e306 --- /dev/null +++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd + */ + +#include "rk3328-u-boot.dtsi" +#include "rk3328-sdram-ddr4-666.dtsi" +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; + }; +}; + +&gpio0 { + u-boot,dm-spl; +}; + +&pinctrl { + u-boot,dm-spl; +}; + +&sdmmc0m1_gpio { + u-boot,dm-spl; +}; + +&pcfg_pull_up_4ma { + u-boot,dm-spl; +}; + +&usb_host0_xhci { + vbus-supply = <&vcc_host1_5v>; + status = "okay"; +}; + +/* + * This makes XHCI responsible for toggling VBUS. This is needed to work + * around an issue where either XHCI only works with USB 2.0 or OTG doesn't + * work, depending on how VBUS is configured. Having USB 3.0 seems better. + */ +&vcc_host1_5v { + /delete-property/ regulator-always-on; +}; + +/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/rk3328-roc-cc.dts b/arch/arm/dts/rk3328-roc-cc.dts new file mode 100644 index 00000000000..8d553c92182 --- /dev/null +++ b/arch/arm/dts/rk3328-roc-cc.dts @@ -0,0 +1,354 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd + */ + +/dts-v1/; +#include "rk3328.dtsi" + +/ { + model = "Firefly roc-rk3328-cc"; + compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_gpio>; + regulator-boot-on; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vcc_sdio: sdmmcio-regulator { + compatible = "regulator-gpio"; + gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1 + 3300000 0x0>; + regulator-name = "vcc_sdio"; + regulator-type = "voltage"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host_drv>; + regulator-name = "vcc_host1_5v"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + leds { + compatible = "gpio-leds"; + + power { + label = "firefly:blue:power"; + linux,default-trigger = "heartbeat"; + gpios = <&rk805 1 GPIO_ACTIVE_LOW>; + default-state = "on"; + mode = <0x23>; + }; + + user { + label = "firefly:yellow:user"; + linux,default-trigger = "mmc1"; + gpios = <&rk805 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + mode = <0x05>; + }; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <150000000>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + snps,aal; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + snps,rxpbl = <0x4>; + snps,txpbl = <0x4>; + tx_delay = <0x24>; + rx_delay = <0x18>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio1>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_io>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_sdio>; + vccio4-supply = <&vcc_18>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_io>; + pmuio-supply = <&vcc_io>; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + usb20_host_drv: usb20-host-drv { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index c661d2e06ae..89becf41c50 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -5,6 +5,13 @@ F: board/rockchip/evb_rk3328 F: include/configs/evb_rk3328.h F: configs/evb-rk3328_defconfig +ROC-RK3328-CC +M: Loic Devulder +M: Chen-Yu Tsai +S: Maintained +F: configs/roc-cc-rk3328_defconfig +F: arch/arm/dts/rk3328-roc-cc-u-boot.dtsi + ROCK64-RK3328 M: Matwey V. Kornilov S: Maintained diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig new file mode 100644 index 00000000000..933a1c6967d --- /dev/null +++ b/configs/roc-cc-rk3328_defconfig @@ -0,0 +1,102 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3328=y +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_TPL_LIBCOMMON_SUPPORT=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SMBIOS_PRODUCT_NAME="roc-rk3328-cc" +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-roc-cc.dtb" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-roc-cc" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TPL_DM=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y +CONFIG_SMBIOS_MANUFACTURER="firefly" diff --git a/doc/README.rockchip b/doc/README.rockchip index 9b699b9ae5d..70c8798ed2d 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -52,10 +52,12 @@ Two RK3308 boards are supported: - EVB RK3308 - use evb-rk3308 configuration - ROC-CC-RK3308 - use roc-cc-rk3308 configuration -Two RK3328 board are supported: +Three RK3328 boards are supported: - EVB RK3328 - use evb-rk3328_defconfig - Pine64 Rock64 board - use rock64-rk3328_defconfig + - Firefly / Libre Computer Project ROC-RK3328-CC board - + use roc-cc-rk3328_defconfig Size RK3399 boards are supported (aarch64): From 062baa25661ed30af10e16fe9d147bb2300b15bd Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 27 Apr 2020 14:52:54 +0800 Subject: [PATCH 041/237] rockchip: dts: rock64: Fix XHCI usage If the VBUS regulator is always-on, XHCI will fail to detect USB 3.0 devices; USB 2.0 devices will work however. Make the VBUS regulator controllable and tie it to only the XHCI. This makes all three USB ports usable. Signed-off-by: Chen-Yu Tsai Reviewed-by: Kever Yang --- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index e5946d2d2dc..8318bf4e603 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -12,5 +12,16 @@ }; &usb_host0_xhci { + vbus-supply = <&vcc_host_5v>; status = "okay"; }; + +/* + * This makes XHCI responsible for toggling VBUS. This is needed to work + * around an issue where either XHCI only works with USB 2.0 or OTG doesn't + * work, depending on how VBUS is configured. Having USB 3.0 seems better. + */ +&vcc_host_5v { + /delete-property/ regulator-always-on; + /delete-property/ regulator-boot-on; +}; From 4888fbe9350d862c817b9d70a96615d1b40ee434 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 28 Apr 2020 15:30:14 +0530 Subject: [PATCH 042/237] arm64: dts: rk3399-puma: Move u-boot properties into -u-boot.dtsi Move U-Boot specific properties into rk3399-puma u-boot specific dtsi file. This would help to sync the devicetrees from Linux whenever required instead of adding specific nodes. Cc: Peter Robinson Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-puma-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/rk3399-puma.dtsi | 11 ----------- 2 files changed, 16 insertions(+), 11 deletions(-) diff --git a/arch/arm/dts/rk3399-puma-u-boot.dtsi b/arch/arm/dts/rk3399-puma-u-boot.dtsi index 52f62b5d39e..e6647792277 100644 --- a/arch/arm/dts/rk3399-puma-u-boot.dtsi +++ b/arch/arm/dts/rk3399-puma-u-boot.dtsi @@ -22,3 +22,19 @@ }; }; + +&bios_enable { + u-boot,dm-pre-reloc; +}; + +&gpio1 { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + +&spiflash { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index 558b6337dfe..246a892cb7c 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -91,7 +91,6 @@ */ bios_enable: bios_enable { compatible = "regulator-fixed"; - u-boot,dm-pre-reloc; regulator-name = "bios_enable"; enable-active-high; gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; @@ -520,14 +519,6 @@ status = "okay"; }; -&gpio1 { - u-boot,dm-pre-reloc; -}; - -&gpio3 { - u-boot,dm-pre-reloc; -}; - &pinctrl { /* Pins that are not explicitely used by any devices */ pinctrl-names = "default"; @@ -633,8 +624,6 @@ #size-cells = <0>; spiflash: w25q32dw@0 { - u-boot,dm-pre-reloc; - compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <49500000>; From f44bf1b5b169ccfcb4745cf4c36cecfd42709f70 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 28 Apr 2020 15:30:15 +0530 Subject: [PATCH 043/237] arm64: dts: rk3399-evb: Move u-boot properties into -u-boot.dtsi Move U-Boot specific properties into rk3399-evb u-boot specific dtsi file. This would help to sync the devicetrees from Linux whenever required instead of adding specific nodes. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-evb-u-boot.dtsi | 8 ++++++++ arch/arm/dts/rk3399-evb.dts | 2 -- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi index f68a56fdd0b..e5659d79995 100644 --- a/arch/arm/dts/rk3399-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi @@ -15,3 +15,11 @@ &rng { status = "okay"; }; + +&i2c0 { + u-boot,dm-pre-reloc; +}; + +&rk808 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index 4129e902a81..c72719c0d30 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -199,7 +199,6 @@ clock-frequency = <400000>; i2c-scl-falling-time-ns = <50>; i2c-scl-rising-time-ns = <100>; - u-boot,dm-pre-reloc; rk808: pmic@1b { compatible = "rockchip,rk808"; @@ -211,7 +210,6 @@ reg = <0x1b>; rockchip,system-power-controller; #clock-cells = <1>; - u-boot,dm-pre-reloc; status = "okay"; vcc12-supply = <&vcc3v3_sys>; From 96993d7c358e9d87871a3c92fb3af081b2e3ff48 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 28 Apr 2020 15:30:16 +0530 Subject: [PATCH 044/237] clk: rk3399: Set empty for HCLK_SD assigned-clocks Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi have HCLK_SD assigned-clocks which are usually required for Linux and don't require to handle them in U-Boot. assigned-clocks = <&cru HCLK_SD>; So, mark them as empty in clock otherwise device probe on those SD controllers would fail. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3399.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 1f623765956..d822acace14 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -996,6 +996,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) break; case ACLK_VOP1: case HCLK_VOP1: + case HCLK_SD: /** * assigned-clocks handling won't require for vopl, so * return 0 to satisfy clk_set_defaults during device probe. From 167efc2c7a46fdac69be545ae5dbfb66edb4fd01 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 28 Apr 2020 15:30:17 +0530 Subject: [PATCH 045/237] arm64: dts: rk3399: Sync v5.7-rc1 from Linux Sync rk3399 dts(i) files from v5.7-rc1 linux-next. Reason: To get updated PCIe nodes and properties on respective dts(i) files. Summary: - sync won't include new board dts(i) - sync will add required files used on respective dts(i) - rk3399-puma-u-boot.dtsi spiflash label changed to norflash - move puma.dtsi bios_enable into rk3399-puma-u-boot.dtsi - move legacy max-frequency of sdhci into rk3399-u-boot.dtsi - update cross-ec-[keyboard|sbs].dtsi path as per U-Boot - keep roc-rk3399-pc dc_12v changes to -u-boot.dtsi Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/cros-ec-keyboard.dtsi | 10 +- arch/arm/dts/cros-ec-sbs.dtsi | 39 +- arch/arm/dts/rk3399-evb.dts | 538 +++++++++++----- arch/arm/dts/rk3399-ficus.dts | 6 + arch/arm/dts/rk3399-firefly.dts | 251 ++++++-- arch/arm/dts/rk3399-gru-bob.dts | 16 +- arch/arm/dts/rk3399-gru-chromebook.dtsi | 40 +- arch/arm/dts/rk3399-gru-kevin.dts | 34 +- arch/arm/dts/rk3399-gru.dtsi | 89 ++- arch/arm/dts/rk3399-khadas-edge.dtsi | 3 + arch/arm/dts/rk3399-leez-p710.dts | 36 +- arch/arm/dts/rk3399-nanopc-t4.dts | 47 +- arch/arm/dts/rk3399-nanopi4.dtsi | 66 +- arch/arm/dts/rk3399-orangepi.dts | 79 ++- arch/arm/dts/rk3399-puma-u-boot.dtsi | 25 +- arch/arm/dts/rk3399-puma.dtsi | 591 ++++++++---------- arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 26 + arch/arm/dts/rk3399-roc-pc.dts | 3 +- arch/arm/dts/rk3399-roc-pc.dtsi | 35 +- arch/arm/dts/rk3399-rock-pi-4.dts | 129 ++++ arch/arm/dts/rk3399-rock960.dts | 49 ++ arch/arm/dts/rk3399-rock960.dtsi | 13 +- arch/arm/dts/rk3399-rockpro64.dts | 751 +--------------------- arch/arm/dts/rk3399-rockpro64.dtsi | 797 ++++++++++++++++++++++++ arch/arm/dts/rk3399-u-boot.dtsi | 1 + arch/arm/dts/rk3399.dtsi | 583 ++++++++++------- 26 files changed, 2584 insertions(+), 1673 deletions(-) create mode 100644 arch/arm/dts/rk3399-rockpro64.dtsi diff --git a/arch/arm/dts/cros-ec-keyboard.dtsi b/arch/arm/dts/cros-ec-keyboard.dtsi index 9c7fb0acae7..4a0c1037fbc 100644 --- a/arch/arm/dts/cros-ec-keyboard.dtsi +++ b/arch/arm/dts/cros-ec-keyboard.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Keyboard dts fragment for devices that use cros-ec-keyboard * * Copyright (c) 2014 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include @@ -22,6 +19,7 @@ MATRIX_KEY(0x00, 0x02, KEY_F1) MATRIX_KEY(0x00, 0x03, KEY_B) MATRIX_KEY(0x00, 0x04, KEY_F10) + MATRIX_KEY(0x00, 0x05, KEY_RO) MATRIX_KEY(0x00, 0x06, KEY_N) MATRIX_KEY(0x00, 0x08, KEY_EQUAL) MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) @@ -34,6 +32,7 @@ MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) MATRIX_KEY(0x01, 0x09, KEY_F9) MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) + MATRIX_KEY(0x01, 0x0c, KEY_HENKAN) MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) MATRIX_KEY(0x02, 0x01, KEY_TAB) @@ -45,6 +44,7 @@ MATRIX_KEY(0x02, 0x07, KEY_102ND) MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) MATRIX_KEY(0x02, 0x09, KEY_F8) + MATRIX_KEY(0x02, 0x0a, KEY_YEN) MATRIX_KEY(0x03, 0x01, KEY_GRAVE) MATRIX_KEY(0x03, 0x02, KEY_F2) @@ -52,7 +52,9 @@ MATRIX_KEY(0x03, 0x04, KEY_F5) MATRIX_KEY(0x03, 0x06, KEY_6) MATRIX_KEY(0x03, 0x08, KEY_MINUS) + MATRIX_KEY(0x03, 0x09, KEY_F13) MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) + MATRIX_KEY(0x03, 0x0c, KEY_MUHENKAN) MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) MATRIX_KEY(0x04, 0x01, KEY_A) diff --git a/arch/arm/dts/cros-ec-sbs.dtsi b/arch/arm/dts/cros-ec-sbs.dtsi index dfe5ea6ca2c..71f5c5ecce4 100644 --- a/arch/arm/dts/cros-ec-sbs.dtsi +++ b/arch/arm/dts/cros-ec-sbs.dtsi @@ -1,8 +1,45 @@ -// SPDX-License-Identifier: GPL-2.0 /* * Smart battery dts fragment for devices that use cros-ec-sbs * * Copyright (c) 2015 Google, Inc + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ &i2c_tunnel { diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index c72719c0d30..694b0d08d64 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -1,86 +1,18 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd */ /dts-v1/; #include -#include #include "rk3399.dtsi" / { model = "Rockchip RK3399 Evaluation Board"; - compatible = "rockchip,rk3399-evb", "rockchip,rk3399", - "google,rk3399evb-rev2"; - - chosen { - stdout-path = &uart2; - }; - - vdd_center: vdd-center { - compatible = "pwm-regulator"; - pwms = <&pwm3 0 25000 1>; - regulator-name = "vdd_center"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-init-microvolt = <950000>; - regulator-always-on; - regulator-boot-on; - status = "okay"; - }; - - vccsys: vccsys { - compatible = "regulator-fixed"; - regulator-name = "vccsys"; - regulator-boot-on; - regulator-always-on; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; - - vcc5v0_host: vcc5v0-host-en { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; - }; - - vcc5v0_typec0: vcc5v0-typec0-en { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_typec0"; - gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; - }; - - vcc5v0_typec1: vcc5v0-typec1-en { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_typec1"; - gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; + compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; backlight: backlight { compatible = "pwm-backlight"; - power-supply = <&vccsys>; - enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; brightness-levels = < 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 @@ -116,18 +48,98 @@ 248 249 250 251 252 253 254 255>; default-brightness-level = <200>; pwms = <&pwm0 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - pwm-delay-us = <10000>; - status = "disabled"; }; - panel:panel { - compatible = "simple-panel"; - power-supply = <&vcc33_lcd>; + edp_panel: edp-panel { + compatible ="lg,lp079qx1-sp0v"; backlight = <&backlight>; - /*enable-gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;*/ - status = "disabled"; + enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + power-supply = <&vcc3v3_s0>; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + vdd_center: vdd-center { + compatible = "pwm-regulator"; + pwms = <&pwm3 0 25000 0>; + regulator-name = "vdd_center"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + status = "okay"; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + +}; + +&edp { + status = "okay"; + force-hpd; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; }; }; @@ -135,6 +147,244 @@ status = "okay"; }; +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_tp: LDO_REG2 { + regulator-name = "vcc3v0_tp"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-name = "vcc1v8_pmu"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: LDO_REG4 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-name = "vcca1v8_codec"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + &pwm0 { status = "okay"; }; @@ -147,15 +397,6 @@ status = "okay"; }; -&saradc { - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - status = "okay"; -}; - &sdhci { bus-width = <8>; mmc-hs400-1_8v; @@ -164,6 +405,36 @@ status = "okay"; }; +&pcie_phy { + status = "disabled"; +}; + +&pcie0 { + ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + status = "disabled"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + &uart2 { status = "okay"; }; @@ -176,11 +447,6 @@ status = "okay"; }; -&usbdrd3_0 { - vbus-supply = <&vcc5v0_typec0>; - status = "okay"; -}; - &usb_host1_ehci { status = "okay"; }; @@ -189,90 +455,26 @@ status = "okay"; }; -&usbdrd3_1 { - vbus-supply = <&vcc5v0_typec1>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <100>; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - clock-output-names = "xin32k", "wifibt_32kin"; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - reg = <0x1b>; - rockchip,system-power-controller; - #clock-cells = <1>; - status = "okay"; - - vcc12-supply = <&vcc3v3_sys>; - - regulators { - vcc33_lcd: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc33_lcd"; - }; - }; - }; -}; - -&mipi_dsi { - status = "disabled"; - rockchip,panel = <&panel>; - display-timings { - timing0 { - bits-per-pixel = <24>; - clock-frequency = <160000000>; - hfront-porch = <120>; - hsync-len = <20>; - hback-porch = <21>; - hactive = <1200>; - vfront-porch = <21>; - vsync-len = <3>; - vback-porch = <18>; - vactive = <1920>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; -}; - &pinctrl { pmic { pmic_int_l: pmic-int-l { rockchip,pins = - <1 21 RK_FUNC_GPIO &pcfg_pull_up>; + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; }; + }; - pmic_dvs2: pmic-dvs2 { + usb2 { + vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = - <1 18 RK_FUNC_GPIO &pcfg_pull_down>; + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; -&gmac { - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x28>; - rx_delay = <0x11>; +&vopb { + status = "okay"; +}; + +&vopb_mmu { status = "okay"; }; diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts index 6b059bd7a04..ebe2ee77ba1 100644 --- a/arch/arm/dts/rk3399-ficus.dts +++ b/arch/arm/dts/rk3399-ficus.dts @@ -146,6 +146,12 @@ }; }; +&spi1 { + /* On both Low speed and High speed expansion */ + cs-gpios = <0>, <&gpio4 RK_PA6 0>, <&gpio4 RK_PA7 0>; + status = "okay"; +}; + &usbdrd_dwc3_0 { dr_mode = "host"; }; diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts index 89c67fd24cc..d63faf38cc8 100644 --- a/arch/arm/dts/rk3399-firefly.dts +++ b/arch/arm/dts/rk3399-firefly.dts @@ -1,19 +1,20 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. */ /dts-v1/; +#include #include -#include #include "rk3399.dtsi" +#include "rk3399-opp.dtsi" / { model = "Firefly-RK3399 Board"; compatible = "firefly,firefly-rk3399", "rockchip,rk3399"; chosen { - stdout-path = &uart2; + stdout-path = "serial2:1500000n8"; }; backlight: backlight { @@ -63,6 +64,48 @@ #clock-cells = <0>; }; + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>; + + work-led { + label = "work"; + default-state = "on"; + gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + }; + + diy-led { + label = "diy"; + default-state = "off"; + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + }; + }; + rt5640-sound { compatible = "simple-audio-card"; simple-audio-card,name = "rockchip,rt5640-codec"; @@ -102,15 +145,27 @@ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; }; + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + vcc3v3_pcie: vcc3v3-pcie-regulator { compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&pcie_drv>; + pinctrl-0 = <&pcie_pwr_en>; regulator-name = "vcc3v3_pcie"; regulator-always-on; regulator-boot-on; + vin-supply = <&dc_12v>; }; vcc3v3_sys: vcc3v3-sys { @@ -120,32 +175,29 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; }; + /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ vcc5v0_host: vcc5v0-host-regulator { compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; + pinctrl-0 = <&vcc5v0_host_en>; regulator-name = "vcc5v0_host"; regulator-always-on; + vin-supply = <&vcc_sys>; }; - vcc5v0_sys: vcc5v0-sys { + vcc_sys: vcc-sys { compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; + regulator-name = "vcc_sys"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; + vin-supply = <&dc_12v>; }; vdd_log: vdd-log { @@ -156,16 +208,7 @@ regulator-boot-on; regulator-min-microvolt = <430000>; regulator-max-microvolt = <1400000>; - regulator-init-microvolt = <950000>; - }; - - vccadc_ref: vccadc-ref { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_sys>; }; }; @@ -201,15 +244,22 @@ assigned-clocks = <&cru SCLK_RMII_SRC>; assigned-clock-parents = <&clkin_gmac>; clock_in_out = "input"; - phy-supply = <&vcc_phy>; + phy-supply = <&vcc_lan>; phy-mode = "rgmii"; pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; snps,reset-active-low; snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x33>; - rx_delay = <0x45>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; status = "okay"; }; @@ -231,16 +281,16 @@ rockchip,system-power-controller; wakeup-source; - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - vcc10-supply = <&vcc3v3_sys>; - vcc11-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; vcc12-supply = <&vcc3v3_sys>; vddio-supply = <&vcc1v8_pmu>; @@ -301,12 +351,12 @@ }; }; - vcc3v0_tp: LDO_REG2 { - regulator-name = "vcc3v0_tp"; + vcc2v8_dvp: LDO_REG2 { + regulator-name = "vcc2v8_dvp"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; regulator-state-mem { regulator-off-in-suspend; }; @@ -324,8 +374,8 @@ }; }; - vcc_sd: LDO_REG4 { - regulator-name = "vcc_sd"; + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; @@ -382,7 +432,7 @@ }; }; - vcc3v3_s3: SWITCH_REG1 { + vcc3v3_s3: vcc_lan: SWITCH_REG1 { regulator-name = "vcc3v3_s3"; regulator-always-on; regulator-boot-on; @@ -412,7 +462,7 @@ regulator-ramp-delay = <1000>; regulator-always-on; regulator-boot-on; - vin-supply = <&vcc5v0_sys>; + vin-supply = <&vcc_sys>; regulator-state-mem { regulator-off-in-suspend; @@ -429,7 +479,7 @@ regulator-ramp-delay = <1000>; regulator-always-on; regulator-boot-on; - vin-supply = <&vcc5v0_sys>; + vin-supply = <&vcc_sys>; regulator-state-mem { regulator-off-in-suspend; @@ -476,19 +526,16 @@ &i2s0 { rockchip,playback-channels = <8>; rockchip,capture-channels = <8>; - #sound-dai-cells = <0>; status = "okay"; }; &i2s1 { rockchip,playback-channels = <2>; rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; status = "okay"; }; &i2s2 { - #sound-dai-cells = <0>; status = "okay"; }; @@ -497,7 +544,7 @@ bt656-supply = <&vcc1v8_dvp>; audio-supply = <&vcca1v8_codec>; - sdmmc-supply = <&vcc_sd>; + sdmmc-supply = <&vcc_sdio>; gpio1830-supply = <&vcc_3v0>; }; @@ -509,7 +556,7 @@ ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; num-lanes = <4>; pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn>; + pinctrl-0 = <&pcie_clkreqn_cpm>; status = "okay"; }; @@ -532,7 +579,7 @@ }; pcie { - pcie_drv: pcie-drv { + pcie_pwr_en: pcie-pwr-en { rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; }; @@ -570,10 +617,26 @@ }; usb2 { - host_vbus_drv: host-vbus-drv { + vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + work_led_gpio: work_led-gpio { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_gpio: diy_led-gpio { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pwm0 { @@ -585,24 +648,70 @@ }; &saradc { - vref-supply = <&vccadc_ref>; + vref-supply = <&vcca1v8_s3>; status = "okay"; }; +&sdio0 { + /* WiFi & BT combo module Ampak AP6356S */ + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + + /* Power supply */ + vqmmc-supply = &vcc1v8_s3; /* IO line */ + vmmc-supply = &vcc_sdio; /* card's power */ + + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + brcm,drive-strength = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + &sdmmc { bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; status = "okay"; }; &sdhci { bus-width = <8>; - keep-power-in-suspend; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; non-removable; status = "okay"; }; +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + &tsadc { /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-mode = <1>; @@ -662,3 +771,37 @@ &usb_host1_ohci { status = "okay"; }; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-gru-bob.dts b/arch/arm/dts/rk3399-gru-bob.dts index 1ee0dc0d9f1..e6c1c94c8d6 100644 --- a/arch/arm/dts/rk3399-gru-bob.dts +++ b/arch/arm/dts/rk3399-gru-bob.dts @@ -18,11 +18,11 @@ "google,bob", "google,gru", "rockchip,rk3399"; edp_panel: edp-panel { - compatible = "boe,nv101wxmn51", "simple-panel"; + compatible = "boe,nv101wxmn51"; backlight = <&backlight>; power-supply = <&pp3300_disp>; - ports { + port { panel_in_edp: endpoint { remote-endpoint = <&edp_out_panel>; }; @@ -68,12 +68,22 @@ &spi0 { status = "okay"; + + cr50@0 { + compatible = "google,cr50"; + reg = <0>; + interrupt-parent = <&gpio0>; + interrupts = <5 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&h1_int_od_l>; + spi-max-frequency = <800000>; + }; }; &pinctrl { tpm { h1_int_od_l: h1-int-od-l { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; }; diff --git a/arch/arm/dts/rk3399-gru-chromebook.dtsi b/arch/arm/dts/rk3399-gru-chromebook.dtsi index c6495adccae..1384dabbdf4 100644 --- a/arch/arm/dts/rk3399-gru-chromebook.dtsi +++ b/arch/arm/dts/rk3399-gru-chromebook.dtsi @@ -194,20 +194,25 @@ backlight: backlight { compatible = "pwm-backlight"; - brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 - 45 46 47 48 49 50 51 52 53 54 55 56 57 58 - 59 60 61 62 63 64 65 66 67 68 69 70 71 72 - 73 74 75 76 77 78 79 80 81 82 83 84 85 86 - 87 88 89 90 91 92 93 94 95 96 97 98 99 100>; - default-brightness-level = <51>; enable-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; power-supply = <&pp3300_disp>; pinctrl-names = "default"; pinctrl-0 = <&bl_en>; pwm-delay-us = <10000>; }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l>; + + wake_on_bt: wake-on-bt { + label = "Wake-on-Bluetooth"; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; }; &ppvar_bigcpu { @@ -232,7 +237,6 @@ &edp { status = "okay"; - rockchip,panel = <&edp_panel>; ports { edp_out: port@1 { reg = <1>; @@ -287,11 +291,9 @@ ap_i2c_tp: &i2c5 { #pwm-cells = <1>; }; - usbc_extcon1: extcon@1 { + usbc_extcon1: extcon1 { compatible = "google,extcon-usbc-cros-ec"; google,usb-port-id = <1>; - - #extcon-cells = <0>; }; }; @@ -361,27 +363,27 @@ ap_i2c_tp: &i2c5 { &pinctrl { discrete-regulators { pp1500_en: pp1500-en { - rockchip,pins = ; }; pp1800_audio_en: pp1800-audio-en { - rockchip,pins = ; }; pp3000_en: pp3000-en { - rockchip,pins = ; }; pp3300_disp_en: pp3300-disp-en { - rockchip,pins = ; }; wlan_module_pd_l: wlan-module-pd-l { - rockchip,pins = ; }; }; @@ -389,10 +391,10 @@ ap_i2c_tp: &i2c5 { &wifi { wifi_perst_l: wifi-perst-l { - rockchip,pins = <2 27 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; }; wlan_host_wake_l: wlan-host-wake-l { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/arch/arm/dts/rk3399-gru-kevin.dts b/arch/arm/dts/rk3399-gru-kevin.dts index 2cc7c47d6a8..2bbef9fcbe2 100644 --- a/arch/arm/dts/rk3399-gru-kevin.dts +++ b/arch/arm/dts/rk3399-gru-kevin.dts @@ -39,11 +39,25 @@ }; edp_panel: edp-panel { - compatible = "sharp,lq123p1jx31", "simple-panel"; + compatible = "sharp,lq123p1jx31"; backlight = <&backlight>; power-supply = <&pp3300_disp>; - ports { + panel-timing { + clock-frequency = <266666667>; + hactive = <2400>; + hfront-porch = <48>; + hback-porch = <84>; + hsync-len = <32>; + hsync-active = <0>; + vactive = <1600>; + vfront-porch = <3>; + vback-porch = <120>; + vsync-len = <10>; + vsync-active = <0>; + }; + + port { panel_in_edp: endpoint { remote-endpoint = <&edp_out_panel>; }; @@ -118,13 +132,17 @@ map0 { trip = <&ppvar_bigcpu_alert>; cooling-device = - <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; contribution = <4096>; }; map1 { trip = <&ppvar_bigcpu_alert>; cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; contribution = <1024>; }; }; @@ -286,24 +304,24 @@ ap_i2c_dig: &i2c2 { digitizer { /* Has external pullup */ cpu1_dig_irq_l: cpu1-dig-irq-l { - rockchip,pins = <2 4 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; }; /* Has external pullup */ cpu1_dig_pdct_l: cpu1-dig-pdct-l { - rockchip,pins = <2 5 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; discrete-regulators { cpu3_pen_pwr_en: cpu3-pen-pwr-en { - rockchip,pins = <4 30 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; pen { cpu1_pen_eject: cpu1-pen-eject { - rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; }; diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi index 0e2e0471808..7ac88392f2c 100644 --- a/arch/arm/dts/rk3399-gru.dtsi +++ b/arch/arm/dts/rk3399-gru.dtsi @@ -11,13 +11,7 @@ / { chosen { - u-boot,dm-pre-reloc; stdout-path = "serial2:115200n8"; - u-boot,spl-boot-order = &spi_flash; - }; - - config { - u-boot,spl-payload-offset = <0x40000>; }; /* @@ -268,17 +262,11 @@ pp5000_usb_a_vbus: pp5000 { }; - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l>; - - wake_on_bt: wake-on-bt { - label = "Wake-on-Bluetooth"; - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; + ap_rtc_clk: ap-rtc-clk { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; }; max98357a: max98357a { @@ -549,8 +537,7 @@ ap_i2c_audio: &i2c8 { pinctrl-names = "default", "sleep"; pinctrl-1 = <&spi1_sleep>; - spi_flash: spiflash@0 { - u-boot,dm-pre-reloc; + spiflash@0 { compatible = "jedec,spi-nor"; reg = <0>; @@ -565,16 +552,12 @@ ap_i2c_audio: &i2c8 { &spi5 { status = "okay"; - spi-activate-delay = <100>; - spi-max-frequency = <3000000>; - spi-deactivate-delay = <200>; cros_ec: ec@0 { compatible = "google,cros-ec-spi"; reg = <0>; interrupt-parent = <&gpio0>; interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - ec-interrupt = <&gpio0 1 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&ec_ap_int_l>; spi-max-frequency = <3000000>; @@ -586,11 +569,9 @@ ap_i2c_audio: &i2c8 { #size-cells = <0>; }; - usbc_extcon0: extcon@0 { + usbc_extcon0: extcon0 { compatible = "google,extcon-usbc-cros-ec"; google,usb-port-id = <0>; - - #extcon-cells = <0>; }; }; }; @@ -692,29 +673,29 @@ ap_i2c_audio: &i2c8 { backlight-enable { bl_en: bl-en { - rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; cros-ec { ec_ap_int_l: ec-ap-int-l { - rockchip,pins = ; + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; }; }; discrete-regulators { sd_io_pwr_en: sd-io-pwr-en { - rockchip,pins = ; }; sd_pwr_1800_sel: sd-pwr-1800-sel { - rockchip,pins = ; }; sd_slot_pwr_en: sd-slot-pwr-en { - rockchip,pins = ; }; }; @@ -722,17 +703,17 @@ ap_i2c_audio: &i2c8 { codec { /* Has external pullup */ headset_int_l: headset-int-l { - rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; }; mic_int: mic-int { - rockchip,pins = <1 13 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; }; }; max98357a { sdmode_en: sdmode-en { - rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>; }; }; @@ -743,7 +724,7 @@ ap_i2c_audio: &i2c8 { * to hack this as gpio, so the EP could be able to * de-assert it along and make ClockPM(CPM) work. */ - rockchip,pins = <2 26 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -754,20 +735,20 @@ ap_i2c_audio: &i2c8 { */ sdmmc_bus4: sdmmc-bus4 { rockchip,pins = - <4 8 RK_FUNC_1 &pcfg_pull_none_8ma>, - <4 9 RK_FUNC_1 &pcfg_pull_none_8ma>, - <4 10 RK_FUNC_1 &pcfg_pull_none_8ma>, - <4 11 RK_FUNC_1 &pcfg_pull_none_8ma>; + <4 RK_PB0 1 &pcfg_pull_none_8ma>, + <4 RK_PB1 1 &pcfg_pull_none_8ma>, + <4 RK_PB2 1 &pcfg_pull_none_8ma>, + <4 RK_PB3 1 &pcfg_pull_none_8ma>; }; sdmmc_clk: sdmmc-clk { rockchip,pins = - <4 12 RK_FUNC_1 &pcfg_pull_none_8ma>; + <4 RK_PB4 1 &pcfg_pull_none_8ma>; }; sdmmc_cmd: sdmmc-cmd { rockchip,pins = - <4 13 RK_FUNC_1 &pcfg_pull_none_8ma>; + <4 RK_PB5 1 &pcfg_pull_none_8ma>; }; /* @@ -781,12 +762,12 @@ ap_i2c_audio: &i2c8 { */ sdmmc_cd: sdmmc-cd { rockchip,pins = - <0 7 RK_FUNC_1 &pcfg_pull_none>; + <0 RK_PA7 1 &pcfg_pull_none>; }; /* This is where we actually hook up CD; has external pull */ sdmmc_cd_gpio: sdmmc-cd-gpio { - rockchip,pins = <4 24 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -796,47 +777,47 @@ ap_i2c_audio: &i2c8 { * Pull down SPI1 CLK/CS/RX/TX during suspend, to * prevent leakage. */ - rockchip,pins = <1 9 RK_FUNC_GPIO &pcfg_pull_down>, - <1 10 RK_FUNC_GPIO &pcfg_pull_down>, - <1 7 RK_FUNC_GPIO &pcfg_pull_down>, - <1 8 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>, + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>, + <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>, + <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; }; }; touchscreen { touch_int_l: touch-int-l { - rockchip,pins = <3 13 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; }; touch_reset_l: touch-reset-l { - rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; trackpad { ap_i2c_tp_pu_en: ap-i2c-tp-pu-en { - rockchip,pins = <3 12 RK_FUNC_GPIO &pcfg_output_high>; + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>; }; trackpad_int_l: trackpad-int-l { - rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; wifi: wifi { wlan_module_reset_l: wlan-module-reset-l { - rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; bt_host_wake_l: bt-host-wake-l { /* Kevin has an external pull up, but Gru does not */ - rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; }; }; write-protect { ap_fw_wp: ap-fw-wp { - rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; }; }; }; diff --git a/arch/arm/dts/rk3399-khadas-edge.dtsi b/arch/arm/dts/rk3399-khadas-edge.dtsi index 4944d78a0a1..e87a0447744 100644 --- a/arch/arm/dts/rk3399-khadas-edge.dtsi +++ b/arch/arm/dts/rk3399-khadas-edge.dtsi @@ -654,9 +654,12 @@ sd-uhs-sdr104; vqmmc-supply = <&vcc1v8_s3>; vmmc-supply = <&vccio_sd>; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; brcmf: wifi@1 { + reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gpio0>; interrupts = ; diff --git a/arch/arm/dts/rk3399-leez-p710.dts b/arch/arm/dts/rk3399-leez-p710.dts index 32baa57b948..73be38a5379 100644 --- a/arch/arm/dts/rk3399-leez-p710.dts +++ b/arch/arm/dts/rk3399-leez-p710.dts @@ -42,14 +42,14 @@ regulator-max-microvolt = <5000000>; }; - vcc5v0_sys: vcc5v0-sys { + vcc3v3_lan: vcc3v3-lan { compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; + regulator-name = "vcc3v3_lan"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc5v_adp>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vim-supply = <&vcc3v3_sys>; }; vcc3v3_sys: vcc3v3-sys { @@ -83,14 +83,14 @@ vin-supply = <&vcc5v0_sys>; }; - vcc3v3_lan: vcc3v3-lan { + vcc5v0_sys: vcc5v0-sys { compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lan"; + regulator-name = "vcc5v0_sys"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vim-supply = <&vcc3v3_sys>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc5v_adp>; }; vdd_log: vdd-log { @@ -510,6 +510,14 @@ }; }; +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; @@ -522,14 +530,6 @@ status = "okay"; }; -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - &tcphy0 { status = "okay"; }; diff --git a/arch/arm/dts/rk3399-nanopc-t4.dts b/arch/arm/dts/rk3399-nanopc-t4.dts index 84433cf02be..e0d75617bb7 100644 --- a/arch/arm/dts/rk3399-nanopc-t4.dts +++ b/arch/arm/dts/rk3399-nanopc-t4.dts @@ -52,13 +52,58 @@ pinctrl-names = "default"; pinctrl-0 = <&ir_rx>; }; + + fan: pwm-fan { + compatible = "pwm-fan"; + /* + * With 20KHz PWM and an EVERCOOL EC4007H12SA fan, these levels + * work out to 0, ~1200, ~3000, and 5000RPM respectively. + */ + cooling-levels = <0 12 18 255>; + #cooling-cells = <2>; + fan-supply = <&vcc12v0_sys>; + pwms = <&pwm1 0 50000 0>; + }; +}; + +&cpu_thermal { + trips { + cpu_warm: cpu_warm { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_hot: cpu_hot { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map2 { + trip = <&cpu_warm>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map3 { + trip = <&cpu_hot>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + +&pcie0 { + num-lanes = <4>; + vpcie3v3-supply = <&vcc3v3_sys>; }; &pinctrl { ir { ir_rx: ir-rx { /* external pullup to VCC3V3_SYS, despite being 1.8V :/ */ - rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/dts/rk3399-nanopi4.dtsi b/arch/arm/dts/rk3399-nanopi4.dtsi index d325e117287..c88018a0ef3 100644 --- a/arch/arm/dts/rk3399-nanopi4.dtsi +++ b/arch/arm/dts/rk3399-nanopi4.dtsi @@ -48,7 +48,7 @@ }; /* switched by pmic_sleep */ - vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + vcc1v8_s3: vcc1v8-s3 { compatible = "regulator-fixed"; regulator-always-on; regulator-boot-on; @@ -71,6 +71,27 @@ vin-supply = <&vcc3v3_sys>; }; + /* + * Really, this is supplied by vcc_1v8, and vcc1v8_s3 only + * drives the enable pin, but we can't quite model that. + */ + vcca0v9_s3: vcca0v9-s3 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vcca0v9_s3"; + vin-supply = <&vcc1v8_s3>; + }; + + /* As above, actually supplied by vcc3v3_sys */ + vcca1v8_s3: vcca1v8-s3 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_s3"; + vin-supply = <&vcc1v8_s3>; + }; + vbus_typec: vbus-typec { compatible = "regulator-fixed"; regulator-min-microvolt = <5000000>; @@ -148,15 +169,28 @@ assigned-clocks = <&cru SCLK_RMII_SRC>; clock_in_out = "input"; pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; + pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>; + phy-handle = <&rtl8211e>; phy-mode = "rgmii"; phy-supply = <&vcc3v3_s3>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; tx_delay = <0x28>; rx_delay = <0x11>; status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8211e: phy@1 { + reg = <1>; + interrupt-parent = <&gpio3>; + interrupts = ; + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; + }; }; &gpu { @@ -171,6 +205,10 @@ status = "okay"; }; +&hdmi_sound { + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; i2c-scl-rising-time-ns = <160>; @@ -446,6 +484,10 @@ status = "okay"; }; +&i2s2 { + status = "okay"; +}; + &io_domains { bt656-supply = <&vcc_1v8>; audio-supply = <&vcca1v8_codec>; @@ -464,7 +506,9 @@ &pcie0 { ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; max-link-speed = <2>; - num-lanes = <4>; + num-lanes = <2>; + vpcie0v9-supply = <&vcca0v9_s3>; + vpcie1v8-supply = <&vcca1v8_s3>; status = "okay"; }; @@ -481,6 +525,16 @@ }; }; + phy { + phy_intb: phy-intb { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rstb: phy-rstb { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { cpu_b_sleep: cpu-b-sleep { rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; diff --git a/arch/arm/dts/rk3399-orangepi.dts b/arch/arm/dts/rk3399-orangepi.dts index cf37b96a6b7..f9f7246d4d2 100644 --- a/arch/arm/dts/rk3399-orangepi.dts +++ b/arch/arm/dts/rk3399-orangepi.dts @@ -136,13 +136,13 @@ vin-supply = <&vcc_sys>; }; - vcc5v0_typec0: vcc5v0-typec0-regulator { + vbus_typec: vbus-typec-regulator { compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec0_en>; - regulator-name = "vcc5v0_typec0"; + pinctrl-0 = <&vcc5v0_typec_en>; + regulator-name = "vbus_typec"; vin-supply = <&vcc_sys>; }; @@ -202,14 +202,27 @@ clock_in_out = "input"; phy-supply = <&vcc3v3_s3>; phy-mode = "rgmii"; + phy-handle = <&rtl8211e>; pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; + pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>; tx_delay = <0x28>; rx_delay = <0x11>; status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8211e: phy@1 { + reg = <1>; + interrupt-parent = <&gpio3>; + interrupts = ; + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; + }; }; &gpu { @@ -419,6 +432,8 @@ compatible = "silergy,syr827"; reg = <0x40>; fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&cpu_b_sleep>; regulator-name = "vdd_cpu_b"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1500000>; @@ -436,6 +451,8 @@ compatible = "silergy,syr828"; reg = <0x41>; fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gpu_sleep>; regulator-name = "vdd_gpu"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1500000>; @@ -472,6 +489,7 @@ compatible = "asahi-kasei,ak09911"; reg = <0x0c>; vdd-supply = <&vcc3v3_s3>; + vid-supply = <&vcc3v3_s3>; }; mpu6500@68 { @@ -504,6 +522,16 @@ pinctrl-0 = <&light_int_l>; vdd-supply = <&vcc3v3_s3>; }; + + fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&chg_cc_int_l>; + vbus-supply = <&vbus_typec>; + }; }; &io_domains { @@ -526,7 +554,25 @@ }; }; + phy { + phy_intb: phy-intb { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rstb: phy-rstb { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { + cpu_b_sleep: cpu-b-sleep { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + gpu_sleep: gpu-sleep { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + pmic_int_l: pmic-int-l { rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; @@ -536,7 +582,7 @@ sd { sdmmc0_pwr_h: sdmmc0-pwr-h { rockchip,pins = - ; + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -546,7 +592,7 @@ <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; }; - vcc5v0_typec0_en: vcc5v0-typec0-en { + vcc5v0_typec_en: vcc5v0-typec-en { rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; @@ -595,6 +641,12 @@ rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + fusb302 { + chg_cc_int_l: chg-cc-int-l { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; }; &pwm0 { @@ -631,9 +683,12 @@ pinctrl-names = "default"; pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; sd-uhs-sdr104; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; brcmf: wifi@1 { + reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gpio0>; interrupts = ; @@ -676,7 +731,7 @@ status = "okay"; u2phy0_otg: otg-port { - phy-supply = <&vcc5v0_typec0>; + phy-supply = <&vbus_typec>; status = "okay"; }; @@ -707,12 +762,14 @@ bluetooth { compatible = "brcm,bcm43438-bt"; clocks = <&rk808 1>; - clock-names = "ext_clock"; + clock-names = "lpo"; device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; }; }; diff --git a/arch/arm/dts/rk3399-puma-u-boot.dtsi b/arch/arm/dts/rk3399-puma-u-boot.dtsi index e6647792277..3ad11398332 100644 --- a/arch/arm/dts/rk3399-puma-u-boot.dtsi +++ b/arch/arm/dts/rk3399-puma-u-boot.dtsi @@ -13,7 +13,7 @@ chosen { stdout-path = "serial0:115200n8"; u-boot,spl-boot-order = \ - "same-as-spl", &spiflash, &sdhci, &sdmmc; + "same-as-spl", &norflash, &sdhci, &sdmmc; }; aliases { @@ -21,10 +21,23 @@ spi1 = &spi5; }; -}; - -&bios_enable { - u-boot,dm-pre-reloc; + /* + * The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module + * eMMC and SPI flash powered-down initially (in fact it keeps the + * reset signal asserted). Even though it is an enable signal, we + * model this as a regulator. + */ + bios_enable: bios_enable { + compatible = "regulator-fixed"; + u-boot,dm-pre-reloc; + regulator-name = "bios_enable"; + enable-active-high; + gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; &gpio1 { @@ -35,6 +48,6 @@ u-boot,dm-pre-reloc; }; -&spiflash { +&norflash { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index 246a892cb7c..07694b196fd 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -1,30 +1,74 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH */ #include #include "rk3399.dtsi" +#include "rk3399-opp.dtsi" / { - model = "Theobroma Systems RK3399-Q7 SoM"; - compatible = "tsd,rk3399-q7", "tsd,puma", "rockchip,rk3399"; - leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&leds_pins_puma>; + pinctrl-0 = <&led_pin_module>; - module_led { + module-led { label = "module_led"; gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; + panic-indicator; }; + }; - sd_card_led { - label = "sd_card_led"; - gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; + /* + * Overwrite the opp-table for CPUB as this board uses a different + * regulator (FAN53555) that only allows 10mV steps and therefore + * can't reach the operation point target voltages from rk3399-opp.dtsi + */ + /delete-node/ opp-table1; + cluster1_opp: opp-table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <800000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <830000>; + opp-suspend; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <880000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <950000>; + }; + opp05 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1030000>; + }; + opp06 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1100000>; + }; + opp07 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1200000>; + }; + opp08 { + opp-hz = /bits/ 64 <1992000000>; + opp-microvolt = <1230000>; + turbo-mode; }; }; @@ -35,78 +79,14 @@ #clock-cells = <0>; }; - dw_hdmi_audio: dw-hdmi-audio { - status = "enabled"; - compatible = "rockchip,dw-hdmi-audio"; - #sound-dai-cells = <0>; - }; - - hdmi_codec: hdmi-codec { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "HDMI-CODEC"; - - simple-audio-card,cpu { - sound-dai = <&i2s2>; - }; - - simple-audio-card,codec { - sound-dai = <&hdmi>; - }; - }; - - hdmi_sound: hdmi-sound { - status = "disabled"; - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "rockchip,hdmi"; - - simple-audio-card,cpu { - sound-dai = <&i2s2>; - }; - simple-audio-card,codec { - sound-dai = <&hdmi>; - }; - }; - - usbhub_enable: usbhub_enable { + vcc1v2_phy: vcc1v2-phy { compatible = "regulator-fixed"; - regulator-name = "usbhub_enable"; - enable-active-low; - gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - /* - * The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module - * eMMC and SPI flash powered-down initially (in fact it keeps the - * reset signal asserted). Even though it is an enable signal, we - * model this as a regulator. - */ - bios_enable: bios_enable { - compatible = "regulator-fixed"; - regulator-name = "bios_enable"; - enable-active-high; - gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + regulator-name = "vcc1v2_phy"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vccadc_ref: vccadc-ref { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc5v0_sys>; }; vcc3v3_sys: vcc3v3-sys { @@ -116,16 +96,18 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; }; - vcc5v0_otg: vcc5v0-otg-regulator { + vcc5v0_host: vcc5v0-host-regulator { compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + enable-active-low; pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc5v0_otg"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; regulator-always-on; + vin-supply = <&vcc5v0_sys>; }; vcc5v0_sys: vcc5v0-sys { @@ -136,48 +118,55 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; +}; - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - regulator-init-microvolt = <950000>; - }; +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; }; &emmc_phy { status = "okay"; + drive-impedance-ohm = <33>; }; &gmac { - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <2 10000 50000>; assigned-clocks = <&cru SCLK_RMII_SRC>; assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc1v2_phy>; + phy-mode = "rgmii"; pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; tx_delay = <0x10>; rx_delay = <0x10>; status = "okay"; }; -&hdmi { - #sound-dai-cells = <0>; +&gpu { + mali-supply = <&vdd_gpu>; status = "okay"; }; @@ -187,37 +176,17 @@ i2c-scl-falling-time-ns = <4>; clock-frequency = <400000>; - vdd_gpu: vdd_gpu { - status = "okay"; - compatible = "fcs,fan53555"; - reg = <0x60>; - vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "fan53555-reg"; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1230000>; - regulator-ramp-delay = <1000>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-boot-on; - regulator-initial-state = <3>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - rk808: pmic@1b { compatible = "rockchip,rk808"; reg = <0x1b>; interrupt-parent = <&gpio1>; - interrupts = <22 IRQ_TYPE_LEVEL_LOW>; // TODO check interrupt? + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; pinctrl-names = "default"; pinctrl-0 = <&pmic_int_l>; rockchip,system-power-controller; wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; vcc1-supply = <&vcc5v0_sys>; vcc2-supply = <&vcc5v0_sys>; @@ -234,44 +203,44 @@ regulators { vdd_center: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vdd_center"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <1350000>; regulator-ramp-delay = <6001>; - regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vdd_cpu_l: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vdd_cpu_l"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <1350000>; regulator-ramp-delay = <6001>; - regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; regulator-always-on; regulator-boot-on; - regulator-name = "vcc_ddr"; regulator-state-mem { regulator-on-in-suspend; }; }; vcc_1v8: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vcc_1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1800000>; @@ -279,32 +248,32 @@ }; vcc_ldo1: LDO_REG1 { - regulator-boot-on; + regulator-name = "vcc_ldo1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-name = "vcc_ldo1"; + regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vcc1v8_hdmi: LDO_REG2 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vcc1v8_hdmi"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8_hdmi"; + regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vcc1v8_pmu: LDO_REG3 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vcc1v8_pmu"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8_pmu"; + regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1800000>; @@ -312,11 +281,11 @@ }; vcc_sd: LDO_REG4 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vcc_sd"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3000000>; - regulator-name = "vcc_sd"; + regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <3000000>; @@ -324,79 +293,105 @@ }; vcc_ldo5: LDO_REG5 { - regulator-boot-on; + regulator-name = "vcc_ldo5"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; - regulator-name = "vcc_ldo5"; + regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vcc_ldo6: LDO_REG6 { - regulator-boot-on; + regulator-name = "vcc_ldo6"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; - regulator-name = "vcc_ldo6"; + regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vcc0v9_hdmi: LDO_REG7 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vcc0v9_hdmi"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <900000>; - regulator-name = "vcc0v9_hdmi"; + regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vcc_efuse: LDO_REG8 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vcc_efuse"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-name = "vcc_efuse"; + regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; regulator-always-on; regulator-boot-on; - regulator-name = "vcc3v3_s3"; regulator-state-mem { regulator-off-in-suspend; }; }; vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; regulator-always-on; regulator-boot-on; - regulator-name = "vcc3v3_s0"; regulator-state-mem { regulator-off-in-suspend; }; }; }; }; + + vdd_gpu: regulator@60 { + compatible = "fcs,fan53555"; + reg = <0x60>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1230000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&i2c7 { + status = "okay"; + clock-frequency = <400000>; + + fan: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #cooling-cells = <2>; + }; + + rtc_twi: rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; }; &i2c8 { status = "okay"; clock-frequency = <400000>; - vdd_cpu_b: vdd_cpu_b { - status = "okay"; + vdd_cpu_b: regulator@60 { compatible = "fcs,fan53555"; reg = <0x60>; - vsel-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; vin-supply = <&vcc5v0_sys>; - regulator-compatible = "fan53555-reg"; regulator-name = "vdd_cpu_b"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1230000>; @@ -404,48 +399,36 @@ fcs,suspend-voltage-selector = <1>; regulator-always-on; regulator-boot-on; - regulator-initial-state = <3>; - regulator-state-mem { - regulator-off-in-suspend; - }; }; }; &i2s0 { + pinctrl-0 = <&i2s0_2ch_bus>; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; status = "okay"; - rockchip,i2s-broken-burst-len; - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - #sound-dai-cells = <0>; }; -&i2s2 { - #sound-dai-cells = <0>; - status = "okay"; +/* + * As Q7 does not specify neither a global nor a RX clock for I2S these + * signals are not used. Furthermore I2S0_LRCK_RX is used as GPIO. + * Therefore we have to redefine the i2s0_2ch_bus definition to prevent + * conflicts. + */ +&i2s0_2ch_bus { + rockchip,pins = + <3 RK_PD0 1 &pcfg_pull_none>, + <3 RK_PD2 1 &pcfg_pull_none>, + <3 RK_PD3 1 &pcfg_pull_none>, + <3 RK_PD7 1 &pcfg_pull_none>; }; &io_domains { status = "okay"; - - bt656-supply = <&vcc_1v8>; /* bt656_gpio2ab_ms */ - audio-supply = <&vcc_1v8>; /* audio_gpio3d4a_ms */ - sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ - gpio1830-supply = <&vcc_1v8>; /* gpio1833_gpio4cd_ms */ -}; - -&pcie0 { - assigned-clocks = <&cru SCLK_PCIEPHY_REF>; - assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; - assigned-clock-rates = <100000000>; - ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn>; - status = "okay"; -}; - -&pcie_phy { - status = "okay"; + bt656-supply = <&vcc_1v8>; + audio-supply = <&vcc_1v8>; + sdmmc-supply = <&vcc_sd>; + gpio1830-supply = <&vcc_1v8>; }; &pmu_io_domains { @@ -453,185 +436,99 @@ pmu1830-supply = <&vcc_1v8>; }; -&pwm0 { - status = "okay"; -}; - &pwm2 { status = "okay"; }; -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - supports-emmc; - non-removable; - keep-power-in-suspend; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&sdmmc { - clock-frequency = <150000000>; - max-frequency = <40000000>; - supports-sd; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - num-slots = <1>; - vqmmc-supply = <&vcc_sd>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "disabled"; -}; - -&usb_host0_ohci { - status = "disabled"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usb_host1_ehci { - status = "disabled"; -}; - -&usb_host1_ohci { - status = "disabled"; -}; - -&usbdrd3_1 { - status = "okay"; - tsd,usb-port-power = "usbhub_enable"; -}; - -&vopb { - status = "okay"; -}; - &pinctrl { - /* Pins that are not explicitely used by any devices */ - pinctrl-names = "default"; - pinctrl-0 = <&puma_pin_hog>; - - hog { - puma_pin_hog: puma_pin_hog { + i2c8 { + i2c8_xfer_a: i2c8-xfer { rockchip,pins = - /* We need pull-ups on Q7 buttons */ - , /* LID_BTN# */ - , /* BATLOW# */ - , /* SLP_BTN# */ - ; /* BIOS_DISABLE# */ + <1 RK_PC4 1 &pcfg_pull_up>, + <1 RK_PC5 1 &pcfg_pull_up>; + }; + }; + + leds { + led_pin_module: led-module-gpio { + rockchip,pins = + <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; pmic { pmic_int_l: pmic-int-l { rockchip,pins = - ; + <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; }; }; - leds_pins_puma: led_pins@0 { - rockchip,pins = - , - ; - }; - usb2 { - otg_vbus_drv: otg-vbus-drv { + vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = - ; - }; - - host_vbus_drv: host-vbus-drv { - rockchip,pins = - ; - }; - }; - - i2c8 { - i2c8_xfer_a: i2c8-xfer { - rockchip,pins = - , - ; + <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; -&i2c1 { - status = "okay"; - clock-frequency = <400000>; -}; -&i2c2 { - status = "okay"; - clock-frequency = <400000>; -}; -&i2c4 { - status = "okay"; - clock-frequency = <400000>; -}; -&i2c6 { - status = "okay"; - clock-frequency = <400000>; -}; - -&i2c6_xfer { - /* Enable pull-ups, the pins would float otherwise. */ - rockchip,pins = - , - ; -}; - -&i2c7 { - status = "okay"; - clock-frequency = <400000>; - - rtc_twi: rtc@6f { - compatible = "isil,isl1208"; - reg = <0x6f>; - }; - fan: fan@18 { - compatible = "ti,amc6821"; - reg = <0x18>; - cooling-min-state = <0>; - cooling-max-state = <9>; - #cooling-cells = <2>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts>; +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; status = "okay"; }; +&sdmmc { + vqmmc-supply = <&vcc_sd>; +}; &spi1 { status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - spiflash: w25q32dw@0 { + norflash: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <49500000>; - spi-cpol; - spi-cpha; + spi-max-frequency = <50000000>; }; }; -&spi5 { +&tcphy1 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { status = "okay"; }; diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi index 598e0e227cb..141dd0b3067 100644 --- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi +++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi @@ -26,7 +26,33 @@ }; }; +/* + * should be placed inside mp8859, but not until mp8859 has + * its own dt-binding. + */ +&dc_12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&vcc_vbus_typec0>; +}; + &vdd_log { regulator-min-microvolt = <430000>; regulator-init-microvolt = <950000>; }; + +&vcc5v0_host { + regulator-always-on; +}; + +&vcc_sys { + regulator-always-on; +}; + +&vcc_sdio { + regulator-always-on; +}; diff --git a/arch/arm/dts/rk3399-roc-pc.dts b/arch/arm/dts/rk3399-roc-pc.dts index 6a909e4eefd..cd419542530 100644 --- a/arch/arm/dts/rk3399-roc-pc.dts +++ b/arch/arm/dts/rk3399-roc-pc.dts @@ -8,6 +8,5 @@ / { model = "Firefly ROC-RK3399-PC Board"; - compatible = "libretech,roc-rk3399-pc", "firefly,roc-rk3399-pc", - "rockchip,rk3399"; + compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; }; diff --git a/arch/arm/dts/rk3399-roc-pc.dtsi b/arch/arm/dts/rk3399-roc-pc.dtsi index 9a1ce3a4ae1..9f225e9c3d5 100644 --- a/arch/arm/dts/rk3399-roc-pc.dtsi +++ b/arch/arm/dts/rk3399-roc-pc.dtsi @@ -110,20 +110,6 @@ regulator-max-microvolt = <5000000>; }; - /* - * should be placed inside mp8859, but not until mp8859 has - * its own dt-binding. - */ - dc_12v: mp8859-dcdc1 { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <&vcc_vbus_typec0>; - }; - /* switched by pmic_sleep */ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { compatible = "regulator-fixed"; @@ -176,7 +162,6 @@ pinctrl-names = "default"; pinctrl-0 = <&vcc5v0_host_en &hub_rst>; regulator-name = "vcc5v0_host"; - regulator-always-on; vin-supply = <&vcc_sys>; }; @@ -198,7 +183,6 @@ pinctrl-names = "default"; pinctrl-0 = <&vcc_sys_en>; regulator-name = "vcc_sys"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -392,7 +376,6 @@ vcc_sdio: LDO_REG4 { regulator-name = "vcc_sdio"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3000000>; @@ -549,6 +532,24 @@ vbus-supply = <&vcc_vbus_typec0>; status = "okay"; }; + + mp8859: regulator@66 { + compatible = "mps,mp8859"; + reg = <0x66>; + dc_12v: mp8859_dcdc { + regulator-name = "dc_12v"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_vbus_typec0>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + }; }; &i2s0 { diff --git a/arch/arm/dts/rk3399-rock-pi-4.dts b/arch/arm/dts/rk3399-rock-pi-4.dts index 4a543f2117d..3923ec01ef6 100644 --- a/arch/arm/dts/rk3399-rock-pi-4.dts +++ b/arch/arm/dts/rk3399-rock-pi-4.dts @@ -25,6 +25,15 @@ #clock-cells = <0>; }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + vcc12v_dcin: dc-12v { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -44,6 +53,16 @@ vin-supply = <&vcc12v_dcin>; }; + vcc_0v9: vcc-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vcc_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + vcc3v3_pcie: vcc3v3-pcie-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -157,12 +176,22 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &hdmi { + ddc-i2c-bus = <&i2c3>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_cec>; status = "okay"; }; +&hdmi_sound { + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; i2c-scl-rising-time-ns = <168>; @@ -444,13 +473,60 @@ pmu1830-supply = <&vcc_3v0>; }; +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; + max-link-speed = <2>; + num-lanes = <4>; + pinctrl-0 = <&pcie_clkreqnb_cpm>; + pinctrl-names = "default"; + vpcie0v9-supply = <&vcc_0v9>; + vpcie1v8-supply = <&vcc_1v8>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + &pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pcie { pcie_pwr_en: pcie-pwr-en { rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + sdio0 { + sdio0_bus4: sdio0-bus4 { + rockchip,pins = <2 RK_PC4 1 &pcfg_pull_up_20ma>, + <2 RK_PC5 1 &pcfg_pull_up_20ma>, + <2 RK_PC6 1 &pcfg_pull_up_20ma>, + <2 RK_PC7 1 &pcfg_pull_up_20ma>; + }; + + sdio0_cmd: sdio0-cmd { + rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up_20ma>; + }; + + sdio0_clk: sdio0-clk { + rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none_20ma>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; @@ -476,6 +552,16 @@ rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pwm2 { @@ -488,6 +574,32 @@ vref-supply = <&vcc_1v8>; }; +&sdio0 { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + clock-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; @@ -551,6 +663,23 @@ }; }; +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + }; +}; + &uart2 { status = "okay"; }; diff --git a/arch/arm/dts/rk3399-rock960.dts b/arch/arm/dts/rk3399-rock960.dts index 12285c51cce..437a75f31ad 100644 --- a/arch/arm/dts/rk3399-rock960.dts +++ b/arch/arm/dts/rk3399-rock960.dts @@ -114,6 +114,55 @@ }; }; +&spi0 { + /* On Low speed expansion (LS-SPI0) */ + status = "okay"; +}; + +&spi4 { + /* On High speed expansion (HS-SPI1) */ + status = "okay"; +}; + +&thermal_zones { + cpu_thermal: cpu { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&tsadc 0>; + sustainable-power = <1550>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <65000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_alert1: cpu_alert1 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu_crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + + trip = <&cpu_alert1>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + &usbdrd_dwc3_0 { dr_mode = "otg"; }; diff --git a/arch/arm/dts/rk3399-rock960.dtsi b/arch/arm/dts/rk3399-rock960.dtsi index c7d48d41e18..ba7c75c9f2a 100644 --- a/arch/arm/dts/rk3399-rock960.dtsi +++ b/arch/arm/dts/rk3399-rock960.dtsi @@ -76,6 +76,15 @@ regulator-always-on; vin-supply = <&vcc5v0_sys>; }; + + vcc_0v9: vcc-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vcc_0v9"; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; }; &cpu_l0 { @@ -384,6 +393,8 @@ num-lanes = <4>; pinctrl-names = "default"; pinctrl-0 = <&pcie_clkreqn_cpm>; + vpcie0v9-supply = <&vcc_0v9>; + vpcie1v8-supply = <&vcca_1v8>; vpcie3v3-supply = <&vcc3v3_pcie>; status = "okay"; }; @@ -531,7 +542,7 @@ cap-mmc-highspeed; cap-sd-highspeed; clock-frequency = <100000000>; - clock-freq-min-max = <100000 100000000>; + max-frequency = <100000000>; cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; disable-wp; sd-uhs-sdr104; diff --git a/arch/arm/dts/rk3399-rockpro64.dts b/arch/arm/dts/rk3399-rockpro64.dts index e544deb61d2..4b42717800f 100644 --- a/arch/arm/dts/rk3399-rockpro64.dts +++ b/arch/arm/dts/rk3399-rockpro64.dts @@ -2,752 +2,29 @@ /* * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. * Copyright (c) 2018 Akash Gajjar + * Copyright (c) 2019 Katsuhiro Suzuki */ /dts-v1/; -#include -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" +#include "rk3399-rockpro64.dtsi" / { - model = "Pine64 RockPro64"; - compatible = "pine64,rockpro64", "rockchip,rk3399"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>; - - work-led { - label = "work"; - default-state = "on"; - gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; - }; - - diy-led { - label = "diy"; - default-state = "off"; - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - fan-supply = <&vcc12v_dcin>; - pwms = <&pwm1 0 50000 0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - /* switched by pmic_sleep */ - vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_1v8>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pwr_en>; - regulator-name = "vcc3v3_pcie"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc12v_dcin>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_typec: vcc5v0-typec-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec_en>; - regulator-name = "vcc5v0_typec"; - regulator-always-on; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1700000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio3>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc5v0_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcca_1v8>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_dvp: LDO_REG1 { - regulator-name = "vcc1v8_dvp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v0_touch: LDO_REG2 { - regulator-name = "vcc3v0_touch"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca_1v8: LDO_REG3 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca1v8_codec: LDO_REG7 { - regulator-name = "vcca1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: vcc_lan: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel1_gpio>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel2_gpio>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; + model = "Pine64 RockPro64 v2.1"; + compatible = "pine64,rockpro64-v2.1", "pine64,rockpro64", "rockchip,rk3399"; }; &i2c1 { - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; + es8316: codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - fusb0: typec-portc@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&fusb0_int>; - vbus-supply = <&vcc5v0_typec>; - status = "okay"; - }; -}; - -&i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - status = "okay"; -}; - -&i2s1 { - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - bt656-supply = <&vcc1v8_dvp>; - audio-supply = <&vcc_3v0>; - sdmmc-supply = <&vcc_sdio>; - gpio1830-supply = <&vcc_3v0>; -}; - -&pcie0 { - ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_perst>; - vpcie12v-supply = <&vcc12v_dcin>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pinctrl { - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - fusb302x { - fusb0_int: fusb0-int { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - work_led_gpio: work_led-gpio { - rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - diy_led_gpio: diy_led-gpio { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - pcie_perst: pcie-perst { - rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_pwr_en: pcie-pwr-en { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_gpio: vsel1-gpio { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_gpio: vsel2-gpio { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - vcc5v0_typec_en: vcc5v0_typec_en { - rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s1_p0_0>; + }; }; }; }; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - status = "okay"; -}; - -&spi1 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - }; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "otg"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-rockpro64.dtsi b/arch/arm/dts/rk3399-rockpro64.dtsi new file mode 100644 index 00000000000..9bca2580126 --- /dev/null +++ b/arch/arm/dts/rk3399-rockpro64.dtsi @@ -0,0 +1,797 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + * Copyright (c) 2018 Akash Gajjar + */ + +#include +#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>; + + work-led { + label = "work"; + default-state = "on"; + gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + diy-led { + label = "diy"; + default-state = "off"; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + fan-supply = <&vcc12v_dcin>; + pwms = <&pwm1 0 50000 0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "audio-graph-card"; + label = "rockchip,rk3399"; + dais = <&i2s1_p0>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwr_en>; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_typec: vcc5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec_en>; + regulator-name = "vcc5v0_typec"; + regulator-always-on; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1700000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio3>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcca_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_touch: LDO_REG2 { + regulator-name = "vcc3v0_touch"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: vcc_lan: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + fusb0: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vcc5v0_typec>; + status = "okay"; + }; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; + + i2s1_p0: port { + i2s1_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc1v8_dvp>; + audio-supply = <&vcc_3v0>; + sdmmc-supply = <&vcc_sdio>; + gpio1830-supply = <&vcc_3v0>; +}; + +&pcie0 { + ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_perst>; + vpcie12v-supply = <&vcc12v_dcin>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + fusb302x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + work_led_gpio: work_led-gpio { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_gpio: diy_led-gpio { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_perst: pcie-perst { + rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_pwr_en: pcie-pwr-en { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio: vsel1-gpio { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + vcc5v0_typec_en: vcc5v0_typec_en { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&spi1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 757b8c10a24..9bb130a92a9 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -85,6 +85,7 @@ }; &sdhci { + max-frequency = <200000000>; u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index 6b7c136ab8c..74f2c3d4909 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd. + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd */ #include @@ -19,6 +19,7 @@ #size-cells = <2>; aliases { + ethernet0 = &gmac; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -67,53 +68,102 @@ cpu_l0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <485>; clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <100>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu_l1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; + capacity-dmips-mhz = <485>; clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <100>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu_l2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; + capacity-dmips-mhz = <485>; clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <100>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu_l3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; + capacity-dmips-mhz = <485>; clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <100>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu_b0: cpu@100 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x0 0x100>; enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; clocks = <&cru ARMCLKB>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <436>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu_b1: cpu@101 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x0 0x101>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; clocks = <&cru ARMCLKB>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <436>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <120>; + exit-latency-us = <250>; + min-residency-us = <900>; + }; + + CLUSTER_SLEEP: cluster-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + }; + }; + + display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vopl_out>, <&vopb_out>; }; pmu_a53 { @@ -147,7 +197,7 @@ #clock-cells = <0>; }; - amba { + amba: bus { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -183,7 +233,7 @@ #size-cells = <2>; #interrupt-cells = <1>; aspm-no-l0s; - bus-range = <0x0 0x1>; + bus-range = <0x0 0x1f>; clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; clock-names = "aclk", "aclk-perf", @@ -200,10 +250,12 @@ linux,pci-domain = <0>; max-link-speed = <1>; msi-map = <0x0 &its 0x0 0x1000>; - phys = <&pcie_phy>; - phy-names = "pcie-phy"; - ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000 - 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>; + phys = <&pcie_phy 0>, <&pcie_phy 1>, + <&pcie_phy 2>, <&pcie_phy 3>; + phy-names = "pcie-phy-0", "pcie-phy-1", + "pcie-phy-2", "pcie-phy-3"; + ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 + 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, @@ -236,10 +288,11 @@ resets = <&cru SRST_A_GMAC>; reset-names = "stmmaceth"; rockchip,grf = <&grf>; + snps,txpbl = <0x4>; status = "disabled"; }; - sdio0: dwmmc@fe310000 { + sdio0: mmc@fe310000 { compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe310000 0x0 0x4000>; @@ -255,12 +308,14 @@ status = "disabled"; }; - sdmmc: dwmmc@fe320000 { + sdmmc: mmc@fe320000 { compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe320000 0x0 0x4000>; interrupts = ; max-frequency = <150000000>; + assigned-clocks = <&cru HCLK_SD>; + assigned-clock-rates = <200000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; @@ -278,7 +333,6 @@ arasan,soc-ctl-syscon = <&grf>; assigned-clocks = <&cru SCLK_EMMC>; assigned-clock-rates = <200000000>; - max-frequency = <200000000>; clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; clock-names = "clk_xin", "clk_ahb"; clock-output-names = "emmc_cardclock"; @@ -286,6 +340,7 @@ phys = <&emmc_phy>; phy-names = "phy_arasan"; power-domains = <&power RK3399_PD_EMMC>; + disable-cqe-dcmd; status = "disabled"; }; @@ -295,11 +350,8 @@ interrupts = ; clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, <&u2phy0>; - clock-names = "usbhost", "arbiter", - "utmi"; phys = <&u2phy0_host>; phy-names = "usb"; - power-domains = <&power RK3399_PD_PERIHP>; status = "disabled"; }; @@ -309,11 +361,8 @@ interrupts = ; clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, <&u2phy0>; - clock-names = "usbhost", "arbiter", - "utmi"; phys = <&u2phy0_host>; phy-names = "usb"; - power-domains = <&power RK3399_PD_PERIHP>; status = "disabled"; }; @@ -323,11 +372,8 @@ interrupts = ; clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, <&u2phy1>; - clock-names = "usbhost", "arbiter", - "utmi"; phys = <&u2phy1_host>; phy-names = "usb"; - power-domains = <&power RK3399_PD_PERIHP>; status = "disabled"; }; @@ -337,15 +383,12 @@ interrupts = ; clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, <&u2phy1>; - clock-names = "usbhost", "arbiter", - "utmi"; phys = <&u2phy1_host>; phy-names = "usb"; - power-domains = <&power RK3399_PD_PERIHP>; status = "disabled"; }; - usbdrd3_0: dwc3_typec0: usb@fe800000 { + usbdrd3_0: usb@fe800000 { compatible = "rockchip,rk3399-dwc3"; #address-cells = <2>; #size-cells = <2>; @@ -364,6 +407,9 @@ compatible = "snps,dwc3"; reg = <0x0 0xfe800000 0x0 0x100000>; interrupts = ; + clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, + <&cru SCLK_USB3OTG0_SUSPEND>; + clock-names = "ref", "bus_early", "suspend"; dr_mode = "otg"; phys = <&u2phy0_otg>, <&tcphy0_usb3>; phy-names = "usb2-phy", "usb3-phy"; @@ -378,7 +424,7 @@ }; }; - dwc3_typec1: usbdrd3_1: usb@fe900000 { + usbdrd3_1: usb@fe900000 { compatible = "rockchip,rk3399-dwc3"; #address-cells = <2>; #size-cells = <2>; @@ -397,6 +443,9 @@ compatible = "snps,dwc3"; reg = <0x0 0xfe900000 0x0 0x100000>; interrupts = ; + clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, + <&cru SCLK_USB3OTG1_SUSPEND>; + clock-names = "ref", "bus_early", "suspend"; dr_mode = "otg"; phys = <&u2phy1_otg>, <&tcphy1_usb3>; phy-names = "usb2-phy", "usb3-phy"; @@ -464,6 +513,7 @@ its: interrupt-controller@fee20000 { compatible = "arm,gic-v3-its"; msi-controller; + #msi-cells = <1>; reg = <0x0 0xfee20000 0x0 0x20000>; }; @@ -612,7 +662,6 @@ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; interrupts = ; - clock-frequency = <24000000>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -639,6 +688,8 @@ clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; clock-names = "spiclk", "apb_pclk"; interrupts = ; + dmas = <&dmac_peri 10>, <&dmac_peri 11>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; #address-cells = <1>; @@ -652,6 +703,8 @@ clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; clock-names = "spiclk", "apb_pclk"; interrupts = ; + dmas = <&dmac_peri 12>, <&dmac_peri 13>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; #address-cells = <1>; @@ -665,6 +718,8 @@ clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; clock-names = "spiclk", "apb_pclk"; interrupts = ; + dmas = <&dmac_peri 14>, <&dmac_peri 15>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; #address-cells = <1>; @@ -678,6 +733,8 @@ clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; clock-names = "spiclk", "apb_pclk"; interrupts = ; + dmas = <&dmac_peri 18>, <&dmac_peri 19>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; #address-cells = <1>; @@ -691,8 +748,11 @@ clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; clock-names = "spiclk", "apb_pclk"; interrupts = ; + dmas = <&dmac_bus 8>, <&dmac_bus 9>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; + power-domains = <&power RK3399_PD_SDIOAUDIO>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -727,13 +787,18 @@ map0 { trip = <&cpu_alert0>; cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu_alert1>; cooling-device = <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -761,7 +826,7 @@ map0 { trip = <&gpu_alert0>; cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -980,22 +1045,11 @@ <&cru PCLK_GMAC>; pm_qos = <&qos_gmac>; }; - pd_perihp@RK3399_PD_PERIHP { - reg = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru ACLK_PERIHP>; - pm_qos = <&qos_perihp>, - <&qos_pcie>, - <&qos_usb_host0>, - <&qos_usb_host1>; - - pd_sd@RK3399_PD_SD { - reg = ; - clocks = <&cru HCLK_SDMMC>, - <&cru SCLK_SDMMC>; - pm_qos = <&qos_sd>; - }; + pd_sd@RK3399_PD_SD { + reg = ; + clocks = <&cru HCLK_SDMMC>, + <&cru SCLK_SDMMC>; + pm_qos = <&qos_sd>; }; pd_sdioaudio@RK3399_PD_SDIOAUDIO { reg = ; @@ -1070,6 +1124,8 @@ pmugrf: syscon@ff320000 { compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xff320000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; pmu_io_domains: io-domains { compatible = "rockchip,rk3399-pmu-io-voltage-domain"; @@ -1192,6 +1248,62 @@ status = "disabled"; }; + vpu: video-codec@ff650000 { + compatible = "rockchip,rk3399-vpu"; + reg = <0x0 0xff650000 0x0 0x800>; + interrupts = , + ; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; + power-domains = <&power RK3399_PD_VCODEC>; + }; + + vpu_mmu: iommu@ff650800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff650800 0x0 0x40>; + interrupts = ; + interrupt-names = "vpu_mmu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3399_PD_VCODEC>; + }; + + vdec_mmu: iommu@ff660480 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; + interrupts = ; + interrupt-names = "vdec_mmu"; + clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + iep_mmu: iommu@ff670800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff670800 0x0 0x40>; + interrupts = ; + interrupt-names = "iep_mmu"; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + rga: rga@ff680000 { + compatible = "rockchip,rk3399-rga"; + reg = <0x0 0xff680000 0x0 0x10000>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; + reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3399_PD_RGA>; + }; + efuse0: efuse@ff690000 { compatible = "rockchip,rk3399-efuse"; reg = <0x0 0xff690000 0x0 0x80>; @@ -1342,8 +1454,9 @@ compatible = "rockchip,rk3399-pcie-phy"; clocks = <&cru SCLK_PCIEPHY_REF>; clock-names = "refclk"; - #phy-cells = <0>; + #phy-cells = <1>; resets = <&cru SRST_PCIEPHY>; + drive-impedance-ohm = <50>; reset-names = "phy"; status = "disabled"; }; @@ -1592,11 +1705,11 @@ reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; interrupts = ; interrupt-names = "isp0_mmu"; - clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>; + clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; clock-names = "aclk", "iface"; #iommu-cells = <0>; + power-domains = <&power RK3399_PD_ISP0>; rockchip,disable-mmu-reset; - status = "disabled"; }; isp1_mmu: iommu@ff924000 { @@ -1604,11 +1717,11 @@ reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; interrupts = ; interrupt-names = "isp1_mmu"; - clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>; + clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; clock-names = "aclk", "iface"; #iommu-cells = <0>; + power-domains = <&power RK3399_PD_ISP1>; rockchip,disable-mmu-reset; - status = "disabled"; }; hdmi_sound: hdmi-sound { @@ -1660,21 +1773,29 @@ }; mipi_dsi: mipi@ff960000 { - compatible = "rockchip,rk3399_mipi_dsi"; + compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff960000 0x0 0x8000>; interrupts = ; - clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, - <&cru SCLK_DPHY_TX0_CFG>; - clock-names = "ref", "pclk", "phy_cfg"; + clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, + <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; + clock-names = "ref", "pclk", "phy_cfg", "grf"; + power-domains = <&power RK3399_PD_VIO>; + resets = <&cru SRST_P_MIPI_DSI0>; + reset-names = "apb"; rockchip,grf = <&grf>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; + ports { - reg = <1>; - mipi_in: port { + #address-cells = <1>; + #size-cells = <0>; + + mipi_in: port@0 { + reg = <0>; #address-cells = <1>; #size-cells = <0>; + mipi_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_mipi>; @@ -1698,6 +1819,8 @@ resets = <&cru SRST_P_MIPI_DSI1>; reset-names = "apb"; rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; ports { @@ -1765,6 +1888,7 @@ ; interrupt-names = "gpu", "job", "mmu"; clocks = <&cru ACLK_GPU>; + #cooling-cells = <2>; power-domains = <&power RK3399_PD_GPU>; status = "disabled"; }; @@ -1929,14 +2053,14 @@ clock { clk_32k: clk-32k { - rockchip,pins = <0 RK_PA0 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; }; }; edp { edp_hpd: edp-hpd { rockchip,pins = - <4 RK_PC7 RK_FUNC_2 &pcfg_pull_none>; + <4 RK_PC7 2 &pcfg_pull_none>; }; }; @@ -1944,382 +2068,409 @@ rgmii_pins: rgmii-pins { rockchip,pins = /* mac_txclk */ - <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_13ma>, + <3 RK_PC1 1 &pcfg_pull_none_13ma>, /* mac_rxclk */ - <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PB6 1 &pcfg_pull_none>, /* mac_mdio */ - <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PB5 1 &pcfg_pull_none>, /* mac_txen */ - <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>, + <3 RK_PB4 1 &pcfg_pull_none_13ma>, /* mac_clk */ - <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PB3 1 &pcfg_pull_none>, /* mac_rxdv */ - <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PB1 1 &pcfg_pull_none>, /* mac_mdc */ - <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PB0 1 &pcfg_pull_none>, /* mac_rxd1 */ - <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PA7 1 &pcfg_pull_none>, /* mac_rxd0 */ - <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PA6 1 &pcfg_pull_none>, /* mac_txd1 */ - <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>, + <3 RK_PA5 1 &pcfg_pull_none_13ma>, /* mac_txd0 */ - <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>, + <3 RK_PA4 1 &pcfg_pull_none_13ma>, /* mac_rxd3 */ - <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PA3 1 &pcfg_pull_none>, /* mac_rxd2 */ - <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PA2 1 &pcfg_pull_none>, /* mac_txd3 */ - <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none_13ma>, + <3 RK_PA1 1 &pcfg_pull_none_13ma>, /* mac_txd2 */ - <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_13ma>; + <3 RK_PA0 1 &pcfg_pull_none_13ma>; }; rmii_pins: rmii-pins { rockchip,pins = /* mac_mdio */ - <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PB5 1 &pcfg_pull_none>, /* mac_txen */ - <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>, + <3 RK_PB4 1 &pcfg_pull_none_13ma>, /* mac_clk */ - <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PB3 1 &pcfg_pull_none>, /* mac_rxer */ - <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PB2 1 &pcfg_pull_none>, /* mac_rxdv */ - <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PB1 1 &pcfg_pull_none>, /* mac_mdc */ - <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PB0 1 &pcfg_pull_none>, /* mac_rxd1 */ - <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PA7 1 &pcfg_pull_none>, /* mac_rxd0 */ - <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PA6 1 &pcfg_pull_none>, /* mac_txd1 */ - <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>, + <3 RK_PA5 1 &pcfg_pull_none_13ma>, /* mac_txd0 */ - <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>; + <3 RK_PA4 1 &pcfg_pull_none_13ma>; }; }; i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = - <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; + <1 RK_PB7 2 &pcfg_pull_none>, + <1 RK_PC0 2 &pcfg_pull_none>; }; }; i2c1 { i2c1_xfer: i2c1-xfer { rockchip,pins = - <4 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, - <4 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; + <4 RK_PA2 1 &pcfg_pull_none>, + <4 RK_PA1 1 &pcfg_pull_none>; }; }; i2c2 { i2c2_xfer: i2c2-xfer { rockchip,pins = - <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>, - <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>; + <2 RK_PA1 2 &pcfg_pull_none_12ma>, + <2 RK_PA0 2 &pcfg_pull_none_12ma>; }; }; i2c3 { i2c3_xfer: i2c3-xfer { rockchip,pins = - <4 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, - <4 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; + <4 RK_PC1 1 &pcfg_pull_none>, + <4 RK_PC0 1 &pcfg_pull_none>; }; }; i2c4 { i2c4_xfer: i2c4-xfer { rockchip,pins = - <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, - <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; + <1 RK_PB4 1 &pcfg_pull_none>, + <1 RK_PB3 1 &pcfg_pull_none>; }; }; i2c5 { i2c5_xfer: i2c5-xfer { rockchip,pins = - <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>, - <3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>; + <3 RK_PB3 2 &pcfg_pull_none>, + <3 RK_PB2 2 &pcfg_pull_none>; }; }; i2c6 { i2c6_xfer: i2c6-xfer { rockchip,pins = - <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>, - <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; + <2 RK_PB2 2 &pcfg_pull_none>, + <2 RK_PB1 2 &pcfg_pull_none>; }; }; i2c7 { i2c7_xfer: i2c7-xfer { rockchip,pins = - <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>, - <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; + <2 RK_PB0 2 &pcfg_pull_none>, + <2 RK_PA7 2 &pcfg_pull_none>; }; }; i2c8 { i2c8_xfer: i2c8-xfer { rockchip,pins = - <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, - <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; + <1 RK_PC5 1 &pcfg_pull_none>, + <1 RK_PC4 1 &pcfg_pull_none>; }; }; i2s0 { + i2s0_2ch_bus: i2s0-2ch-bus { + rockchip,pins = + <3 RK_PD0 1 &pcfg_pull_none>, + <3 RK_PD1 1 &pcfg_pull_none>, + <3 RK_PD2 1 &pcfg_pull_none>, + <3 RK_PD3 1 &pcfg_pull_none>, + <3 RK_PD7 1 &pcfg_pull_none>, + <4 RK_PA0 1 &pcfg_pull_none>; + }; + i2s0_8ch_bus: i2s0-8ch-bus { rockchip,pins = - <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>, - <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, - <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, - <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>, - <3 RK_PD4 RK_FUNC_1 &pcfg_pull_none>, - <3 RK_PD5 RK_FUNC_1 &pcfg_pull_none>, - <3 RK_PD6 RK_FUNC_1 &pcfg_pull_none>, - <3 RK_PD7 RK_FUNC_1 &pcfg_pull_none>, - <4 RK_PA0 RK_FUNC_1 &pcfg_pull_none>; + <3 RK_PD0 1 &pcfg_pull_none>, + <3 RK_PD1 1 &pcfg_pull_none>, + <3 RK_PD2 1 &pcfg_pull_none>, + <3 RK_PD3 1 &pcfg_pull_none>, + <3 RK_PD4 1 &pcfg_pull_none>, + <3 RK_PD5 1 &pcfg_pull_none>, + <3 RK_PD6 1 &pcfg_pull_none>, + <3 RK_PD7 1 &pcfg_pull_none>, + <4 RK_PA0 1 &pcfg_pull_none>; }; }; i2s1 { i2s1_2ch_bus: i2s1-2ch-bus { rockchip,pins = - <4 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, - <4 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, - <4 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, - <4 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, - <4 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; + <4 RK_PA3 1 &pcfg_pull_none>, + <4 RK_PA4 1 &pcfg_pull_none>, + <4 RK_PA5 1 &pcfg_pull_none>, + <4 RK_PA6 1 &pcfg_pull_none>, + <4 RK_PA7 1 &pcfg_pull_none>; }; }; sdio0 { sdio0_bus1: sdio0-bus1 { rockchip,pins = - <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; + <2 RK_PC4 1 &pcfg_pull_up>; }; sdio0_bus4: sdio0-bus4 { rockchip,pins = - <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>; + <2 RK_PC4 1 &pcfg_pull_up>, + <2 RK_PC5 1 &pcfg_pull_up>, + <2 RK_PC6 1 &pcfg_pull_up>, + <2 RK_PC7 1 &pcfg_pull_up>; }; sdio0_cmd: sdio0-cmd { rockchip,pins = - <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>; + <2 RK_PD0 1 &pcfg_pull_up>; }; sdio0_clk: sdio0-clk { rockchip,pins = - <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; + <2 RK_PD1 1 &pcfg_pull_none>; }; sdio0_cd: sdio0-cd { rockchip,pins = - <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>; + <2 RK_PD2 1 &pcfg_pull_up>; }; sdio0_pwr: sdio0-pwr { rockchip,pins = - <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>; + <2 RK_PD3 1 &pcfg_pull_up>; }; sdio0_bkpwr: sdio0-bkpwr { rockchip,pins = - <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; + <2 RK_PD4 1 &pcfg_pull_up>; }; sdio0_wp: sdio0-wp { rockchip,pins = - <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>; + <0 RK_PA3 1 &pcfg_pull_up>; }; sdio0_int: sdio0-int { rockchip,pins = - <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>; + <0 RK_PA4 1 &pcfg_pull_up>; }; }; sdmmc { sdmmc_bus1: sdmmc-bus1 { rockchip,pins = - <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; + <4 RK_PB0 1 &pcfg_pull_up>; }; sdmmc_bus4: sdmmc-bus4 { rockchip,pins = - <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>, - <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>, - <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, - <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; + <4 RK_PB0 1 &pcfg_pull_up>, + <4 RK_PB1 1 &pcfg_pull_up>, + <4 RK_PB2 1 &pcfg_pull_up>, + <4 RK_PB3 1 &pcfg_pull_up>; }; sdmmc_clk: sdmmc-clk { rockchip,pins = - <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; + <4 RK_PB4 1 &pcfg_pull_none>; }; sdmmc_cmd: sdmmc-cmd { rockchip,pins = - <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>; + <4 RK_PB5 1 &pcfg_pull_up>; }; sdmmc_cd: sdmmc-cd { rockchip,pins = - <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>; + <0 RK_PA7 1 &pcfg_pull_up>; }; sdmmc_wp: sdmmc-wp { rockchip,pins = - <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; + <0 RK_PB0 1 &pcfg_pull_up>; }; }; sleep { ap_pwroff: ap-pwroff { - rockchip,pins = <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; }; ddrio_pwroff: ddrio-pwroff { - rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; }; }; spdif { spdif_bus: spdif-bus { rockchip,pins = - <4 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; + <4 RK_PC5 1 &pcfg_pull_none>; }; spdif_bus_1: spdif-bus-1 { rockchip,pins = - <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; + <3 RK_PC0 3 &pcfg_pull_none>; }; }; spi0 { spi0_clk: spi0-clk { rockchip,pins = - <3 RK_PA6 RK_FUNC_2 &pcfg_pull_up>; + <3 RK_PA6 2 &pcfg_pull_up>; }; spi0_cs0: spi0-cs0 { rockchip,pins = - <3 RK_PA7 RK_FUNC_2 &pcfg_pull_up>; + <3 RK_PA7 2 &pcfg_pull_up>; }; spi0_cs1: spi0-cs1 { rockchip,pins = - <3 RK_PB0 RK_FUNC_2 &pcfg_pull_up>; + <3 RK_PB0 2 &pcfg_pull_up>; }; spi0_tx: spi0-tx { rockchip,pins = - <3 RK_PA5 RK_FUNC_2 &pcfg_pull_up>; + <3 RK_PA5 2 &pcfg_pull_up>; }; spi0_rx: spi0-rx { rockchip,pins = - <3 RK_PA4 RK_FUNC_2 &pcfg_pull_up>; + <3 RK_PA4 2 &pcfg_pull_up>; }; }; spi1 { spi1_clk: spi1-clk { rockchip,pins = - <1 RK_PB1 RK_FUNC_2 &pcfg_pull_up>; + <1 RK_PB1 2 &pcfg_pull_up>; }; spi1_cs0: spi1-cs0 { rockchip,pins = - <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up>; + <1 RK_PB2 2 &pcfg_pull_up>; }; spi1_rx: spi1-rx { rockchip,pins = - <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up>; + <1 RK_PA7 2 &pcfg_pull_up>; }; spi1_tx: spi1-tx { rockchip,pins = - <1 RK_PB0 RK_FUNC_2 &pcfg_pull_up>; + <1 RK_PB0 2 &pcfg_pull_up>; }; }; spi2 { spi2_clk: spi2-clk { rockchip,pins = - <2 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; + <2 RK_PB3 1 &pcfg_pull_up>; }; spi2_cs0: spi2-cs0 { rockchip,pins = - <2 RK_PB4 RK_FUNC_1 &pcfg_pull_up>; + <2 RK_PB4 1 &pcfg_pull_up>; }; spi2_rx: spi2-rx { rockchip,pins = - <2 RK_PB1 RK_FUNC_1 &pcfg_pull_up>; + <2 RK_PB1 1 &pcfg_pull_up>; }; spi2_tx: spi2-tx { rockchip,pins = - <2 RK_PB2 RK_FUNC_1 &pcfg_pull_up>; + <2 RK_PB2 1 &pcfg_pull_up>; }; }; spi3 { spi3_clk: spi3-clk { rockchip,pins = - <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>; + <1 RK_PC1 1 &pcfg_pull_up>; }; spi3_cs0: spi3-cs0 { rockchip,pins = - <1 RK_PC2 RK_FUNC_1 &pcfg_pull_up>; + <1 RK_PC2 1 &pcfg_pull_up>; }; spi3_rx: spi3-rx { rockchip,pins = - <1 RK_PB7 RK_FUNC_1 &pcfg_pull_up>; + <1 RK_PB7 1 &pcfg_pull_up>; }; spi3_tx: spi3-tx { rockchip,pins = - <1 RK_PC0 RK_FUNC_1 &pcfg_pull_up>; + <1 RK_PC0 1 &pcfg_pull_up>; }; }; spi4 { spi4_clk: spi4-clk { rockchip,pins = - <3 RK_PA2 RK_FUNC_2 &pcfg_pull_up>; + <3 RK_PA2 2 &pcfg_pull_up>; }; spi4_cs0: spi4-cs0 { rockchip,pins = - <3 RK_PA3 RK_FUNC_2 &pcfg_pull_up>; + <3 RK_PA3 2 &pcfg_pull_up>; }; spi4_rx: spi4-rx { rockchip,pins = - <3 RK_PA0 RK_FUNC_2 &pcfg_pull_up>; + <3 RK_PA0 2 &pcfg_pull_up>; }; spi4_tx: spi4-tx { rockchip,pins = - <3 RK_PA1 RK_FUNC_2 &pcfg_pull_up>; + <3 RK_PA1 2 &pcfg_pull_up>; }; }; spi5 { spi5_clk: spi5-clk { rockchip,pins = - <2 RK_PC6 RK_FUNC_2 &pcfg_pull_up>; + <2 RK_PC6 2 &pcfg_pull_up>; }; spi5_cs0: spi5-cs0 { rockchip,pins = - <2 RK_PC7 RK_FUNC_2 &pcfg_pull_up>; + <2 RK_PC7 2 &pcfg_pull_up>; }; spi5_rx: spi5-rx { rockchip,pins = - <2 RK_PC4 RK_FUNC_2 &pcfg_pull_up>; + <2 RK_PC4 2 &pcfg_pull_up>; }; spi5_tx: spi5-tx { rockchip,pins = - <2 RK_PC5 RK_FUNC_2 &pcfg_pull_up>; + <2 RK_PC5 2 &pcfg_pull_up>; + }; + }; + + testclk { + test_clkout0: test-clkout0 { + rockchip,pins = + <0 RK_PA0 1 &pcfg_pull_none>; + }; + + test_clkout1: test-clkout1 { + rockchip,pins = + <2 RK_PD1 2 &pcfg_pull_none>; + }; + + test_clkout2: test-clkout2 { + rockchip,pins = + <0 RK_PB0 3 &pcfg_pull_none>; }; }; @@ -2329,168 +2480,168 @@ }; otp_out: otp-out { - rockchip,pins = <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; }; }; uart0 { uart0_xfer: uart0-xfer { rockchip,pins = - <2 RK_PC0 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; + <2 RK_PC0 1 &pcfg_pull_up>, + <2 RK_PC1 1 &pcfg_pull_none>; }; uart0_cts: uart0-cts { rockchip,pins = - <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; + <2 RK_PC2 1 &pcfg_pull_none>; }; uart0_rts: uart0-rts { rockchip,pins = - <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; + <2 RK_PC3 1 &pcfg_pull_none>; }; }; uart1 { uart1_xfer: uart1-xfer { rockchip,pins = - <3 RK_PB4 RK_FUNC_2 &pcfg_pull_up>, - <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; + <3 RK_PB4 2 &pcfg_pull_up>, + <3 RK_PB5 2 &pcfg_pull_none>; }; }; uart2a { uart2a_xfer: uart2a-xfer { rockchip,pins = - <4 RK_PB0 RK_FUNC_2 &pcfg_pull_up>, - <4 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; + <4 RK_PB0 2 &pcfg_pull_up>, + <4 RK_PB1 2 &pcfg_pull_none>; }; }; uart2b { uart2b_xfer: uart2b-xfer { rockchip,pins = - <4 RK_PC0 RK_FUNC_2 &pcfg_pull_up>, - <4 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; + <4 RK_PC0 2 &pcfg_pull_up>, + <4 RK_PC1 2 &pcfg_pull_none>; }; }; uart2c { uart2c_xfer: uart2c-xfer { rockchip,pins = - <4 RK_PC3 RK_FUNC_1 &pcfg_pull_up>, - <4 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; + <4 RK_PC3 1 &pcfg_pull_up>, + <4 RK_PC4 1 &pcfg_pull_none>; }; }; uart3 { uart3_xfer: uart3-xfer { rockchip,pins = - <3 RK_PB6 RK_FUNC_2 &pcfg_pull_up>, - <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; + <3 RK_PB6 2 &pcfg_pull_up>, + <3 RK_PB7 2 &pcfg_pull_none>; }; uart3_cts: uart3-cts { rockchip,pins = - <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; + <3 RK_PC0 2 &pcfg_pull_none>; }; uart3_rts: uart3-rts { rockchip,pins = - <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; + <3 RK_PC1 2 &pcfg_pull_none>; }; }; uart4 { uart4_xfer: uart4-xfer { rockchip,pins = - <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up>, - <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; + <1 RK_PA7 1 &pcfg_pull_up>, + <1 RK_PB0 1 &pcfg_pull_none>; }; }; uarthdcp { uarthdcp_xfer: uarthdcp-xfer { rockchip,pins = - <4 RK_PC5 RK_FUNC_2 &pcfg_pull_up>, - <4 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; + <4 RK_PC5 2 &pcfg_pull_up>, + <4 RK_PC6 2 &pcfg_pull_none>; }; }; pwm0 { pwm0_pin: pwm0-pin { rockchip,pins = - <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; + <4 RK_PC2 1 &pcfg_pull_none>; + }; + + pwm0_pin_pull_down: pwm0-pin-pull-down { + rockchip,pins = + <4 RK_PC2 1 &pcfg_pull_down>; }; vop0_pwm_pin: vop0-pwm-pin { rockchip,pins = - <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; + <4 RK_PC2 2 &pcfg_pull_none>; + }; + + vop1_pwm_pin: vop1-pwm-pin { + rockchip,pins = + <4 RK_PC2 3 &pcfg_pull_none>; }; }; pwm1 { pwm1_pin: pwm1-pin { rockchip,pins = - <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; + <4 RK_PC6 1 &pcfg_pull_none>; }; - vop1_pwm_pin: vop1-pwm-pin { + pwm1_pin_pull_down: pwm1-pin-pull-down { rockchip,pins = - <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; + <4 RK_PC6 1 &pcfg_pull_down>; }; }; pwm2 { pwm2_pin: pwm2-pin { rockchip,pins = - <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; + <1 RK_PC3 1 &pcfg_pull_none>; }; pwm2_pin_pull_down: pwm2-pin-pull-down { rockchip,pins = - <1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>; + <1 RK_PC3 1 &pcfg_pull_down>; }; }; pwm3a { pwm3a_pin: pwm3a-pin { rockchip,pins = - <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; + <0 RK_PA6 1 &pcfg_pull_none>; }; }; pwm3b { pwm3b_pin: pwm3b-pin { rockchip,pins = - <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; + <1 RK_PB6 1 &pcfg_pull_none>; }; }; hdmi { hdmi_i2c_xfer: hdmi-i2c-xfer { rockchip,pins = - <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>, - <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; + <4 RK_PC1 3 &pcfg_pull_none>, + <4 RK_PC0 3 &pcfg_pull_none>; }; hdmi_cec: hdmi-cec { rockchip,pins = - <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>; + <4 RK_PC7 1 &pcfg_pull_none>; }; }; pcie { - pcie_clkreqn: pci-clkreqn { - rockchip,pins = - <2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>; - }; - - pcie_clkreqnb: pci-clkreqnb { - rockchip,pins = - <4 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; - }; - pcie_clkreqn_cpm: pci-clkreqn-cpm { rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; From fb3f5cdbf1e2c338e148f49834ecc0efafde8095 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 28 Apr 2020 15:30:18 +0530 Subject: [PATCH 046/237] arm: dts: rk3399: Sync roc-pc-mezzanine from v5.7-rc1 Sync Firefly ROC-RK3399-PC Mezzanine Board dts file from Linux v5.7-rc1. Signed-off-by: Suniel Mahesh Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-roc-pc-mezzanine.dts | 93 ++++++++++++++++++++++++ 2 files changed, 94 insertions(+) create mode 100644 arch/arm/dts/rk3399-roc-pc-mezzanine.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a683525e7c6..e1be8b4a338 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -132,6 +132,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-puma-ddr1600.dtb \ rk3399-puma-ddr1866.dtb \ rk3399-roc-pc.dtb \ + rk3399-roc-pc-mezzanine.dtb \ rk3399-rock-pi-4.dtb \ rk3399-rock960.dtb \ rk3399-rockpro64.dtb diff --git a/arch/arm/dts/rk3399-roc-pc-mezzanine.dts b/arch/arm/dts/rk3399-roc-pc-mezzanine.dts new file mode 100644 index 00000000000..2acb3d500fb --- /dev/null +++ b/arch/arm/dts/rk3399-roc-pc-mezzanine.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd + * Copyright (c) 2019 Markus Reichl + */ + +/dts-v1/; +#include "rk3399-roc-pc.dtsi" + +/ { + model = "Firefly ROC-RK3399-PC Mezzanine Board"; + compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399"; + + vcc3v3_ngff: vcc3v3-ngff { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_ngff"; + enable-active-high; + gpio = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_ngff_en>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_pcie: vcc3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + enable-active-high; + gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie_en>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_perst>; + vpcie3v3-supply = <&vcc3v3_pcie>; + vpcie1v8-supply = <&vcc1v8_pmu>; + vpcie0v9-supply = <&vcca_0v9>; + status = "okay"; +}; + +&pinctrl { + ngff { + vcc3v3_ngff_en: vcc3v3-ngff-en { + rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + vcc3v3_pcie_en: vcc3v3-pcie-en { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_perst: pcie-perst { + rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_ngff>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; +}; From f417d71ea78be5b8d506531911b747beae87cb54 Mon Sep 17 00:00:00 2001 From: Suniel Mahesh Date: Tue, 28 Apr 2020 15:30:19 +0530 Subject: [PATCH 047/237] rk3399: Add ROC-RK3399-PC Mezzanine board Add Firefly ROC-RK3399-PC Mezzanine board which is an extension board on top of roc-rk3399-pc. Will drop the separate defconfig file, once we support the board detection at runtime. Signed-off-by: Suniel Mahesh Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- .../dts/rk3399-roc-pc-mezzanine-u-boot.dtsi | 6 ++ board/firefly/roc-pc-rk3399/MAINTAINERS | 2 + configs/roc-pc-mezzanine-rk3399_defconfig | 67 +++++++++++++++++++ 3 files changed, 75 insertions(+) create mode 100644 arch/arm/dts/rk3399-roc-pc-mezzanine-u-boot.dtsi create mode 100644 configs/roc-pc-mezzanine-rk3399_defconfig diff --git a/arch/arm/dts/rk3399-roc-pc-mezzanine-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-mezzanine-u-boot.dtsi new file mode 100644 index 00000000000..f50c18dd3df --- /dev/null +++ b/arch/arm/dts/rk3399-roc-pc-mezzanine-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#include "rk3399-roc-pc-u-boot.dtsi" diff --git a/board/firefly/roc-pc-rk3399/MAINTAINERS b/board/firefly/roc-pc-rk3399/MAINTAINERS index 7564dd252de..68a5b757d1d 100644 --- a/board/firefly/roc-pc-rk3399/MAINTAINERS +++ b/board/firefly/roc-pc-rk3399/MAINTAINERS @@ -1,6 +1,8 @@ ROC-RK3399-PC M: Levin Du +M: Suniel Mahesh S: Maintained F: board/firefly/roc-pc-rk3399 F: include/configs/roc-pc-rk3399.h F: configs/roc-pc-rk3399_defconfig +F: configs/roc-pc-mezzanine-rk3399_defconfig diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig new file mode 100644 index 00000000000..5a694edc03f --- /dev/null +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_ROC_PC_RK3399=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_TPL_GPIO_SUPPORT=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc-mezzanine" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_KEYBOARD=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_BPP16=y +CONFIG_VIDEO_BPP32=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y From d597e613745155d2c48ed90617b3fce81af92fbd Mon Sep 17 00:00:00 2001 From: Deepak Das Date: Sun, 26 Apr 2020 16:11:50 +0530 Subject: [PATCH 048/237] rockchip: rk3399: Add Nanopi M4 2GB board support commit b2f5da9dd068 ("rockchip: rk3399: Add Nanopi M4 board support") added support for Nanopi M4 board with Dual-Channel 4GB LPDDR3-1866 RAM. This patch adds another variant of NanoPi M4 board with Dual-Channel 2GB DDR3-1866 RAM. Signed-off-by: Deepak Das --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi | 8 +++ arch/arm/dts/rk3399-nanopi-m4-2gb.dts | 66 +++++++++++++++++++ board/rockchip/evb_rk3399/MAINTAINERS | 7 ++ configs/nanopi-m4-2gb-rk3399_defconfig | 63 ++++++++++++++++++ 5 files changed, 145 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-m4-2gb.dts create mode 100644 configs/nanopi-m4-2gb-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e1be8b4a338..23aa1254de9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -126,6 +126,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-leez-p710.dtb \ rk3399-nanopc-t4.dtb \ rk3399-nanopi-m4.dtb \ + rk3399-nanopi-m4-2gb.dtb \ rk3399-nanopi-neo4.dtb \ rk3399-orangepi.dtb \ rk3399-puma-ddr1333.dtb \ diff --git a/arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi new file mode 100644 index 00000000000..a2f9786473e --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + * Copyright (C) 2020 Deepak Das + */ + +#include "rk3399-nanopi4-u-boot.dtsi" +#include "rk3399-sdram-ddr3-1866.dtsi" diff --git a/arch/arm/dts/rk3399-nanopi-m4-2gb.dts b/arch/arm/dts/rk3399-nanopi-m4-2gb.dts new file mode 100644 index 00000000000..60358ab8c7d --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-m4-2gb.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * FriendlyElec NanoPi M4 board device tree source + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2019 Arm Ltd. + */ + +/dts-v1/; +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyElec NanoPi M4"; + compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399"; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_core: vcc5v0-core { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_core"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v>; + }; + + vcc5v0_usb1: vcc5v0-usb1 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb1"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb2: vcc5v0-usb2 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb2"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&vcc3v3_sys { + vin-supply = <&vcc5v0_core>; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_usb1>; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_usb2>; +}; + +&vbus_typec { + regulator-always-on; + vin-supply = <&vdd_5v>; +}; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 0834254f6de..792df1087f5 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -42,6 +42,13 @@ S: Maintained F: configs/nanopi-m4-rk3399_defconfig F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi +NANOPI-M4-2GB +M: Jagan Teki +M: Deepak Das +S: Maintained +F: configs/nanopi-m4-2gb-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi + NANOPI-NEO4 M: Jagan Teki S: Maintained diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig new file mode 100644 index 00000000000..93c8db979c3 --- /dev/null +++ b/configs/nanopi-m4-2gb-rk3399_defconfig @@ -0,0 +1,63 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4-2gb.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4-2gb" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_KEYBOARD=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_BPP16=y +CONFIG_VIDEO_BPP32=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y From f2c5564f7552369e2d5648eb8ac2e1164755c8f7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 4 Apr 2020 12:21:57 +0200 Subject: [PATCH 049/237] net: Fix warning when including netdev.h on DM systems If the DM_ETH is enabled and netdev.h is included somewhere, the struct eth_device may not be defined, yet it is used in the header file as an argument to fecmxc_register_mii_postcall. Add forward declaration to remove the warning. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- include/netdev.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/netdev.h b/include/netdev.h index 68a3fceab66..f2d21c45d0f 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -125,6 +125,7 @@ int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, /* * Allow FEC to fine-tune MII configuration on boards which require this. */ +struct eth_device; int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)); #endif From 635a76b703f3bd5b20e28bfc86caee9889f536c2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 18 Apr 2020 01:44:12 +0200 Subject: [PATCH 050/237] net: pcnet: Remove CONFIG_PCNET_79C97x These macros guard one switch-case statement, which grows mips malta by some 20 bytes if debug is enabled, and even less if it is not. To make the code simpler, just support all the NICs and be done with it. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/pcnet.c | 8 -------- include/configs/malta.h | 1 - scripts/config_whitelist.txt | 2 -- 3 files changed, 11 deletions(-) diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index b4ad11d3fa5..59241c95bcd 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -21,10 +21,6 @@ #define PCNET_DEBUG2(fmt,args...) \ debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args) -#if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) -#error "Macro for PCnet chip version is not defined!" -#endif - /* * Set the number of Tx and Rx buffers, using Log_2(# buffers). * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. @@ -254,16 +250,12 @@ static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr) case 0x2621: chipname = "PCnet/PCI II 79C970A"; /* PCI */ break; -#ifdef CONFIG_PCNET_79C973 case 0x2625: chipname = "PCnet/FAST III 79C973"; /* PCI */ break; -#endif -#ifdef CONFIG_PCNET_79C975 case 0x2627: chipname = "PCnet/FAST III 79C975"; /* PCI */ break; -#endif default: printf("%s: PCnet version %#x not supported\n", dev->name, chip_version); diff --git a/include/configs/malta.h b/include/configs/malta.h index bb8a44433eb..d41b80c7dc2 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -16,7 +16,6 @@ #define CONFIG_PCI_GT64120 #define CONFIG_PCI_MSC01 #define CONFIG_PCNET -#define CONFIG_PCNET_79C973 #define PCNET_HAS_PROM #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 12a6698958e..27125d7b8af 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1292,8 +1292,6 @@ CONFIG_PCI_SYS_BUS CONFIG_PCI_SYS_PHYS CONFIG_PCI_SYS_SIZE CONFIG_PCNET -CONFIG_PCNET_79C973 -CONFIG_PCNET_79C975 CONFIG_PEN_ADDR_BIG_ENDIAN CONFIG_PERIF1_FREQ CONFIG_PERIF2_FREQ From 171f5e580e3388090d589aa4c0f123576948ab52 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 18 Apr 2020 01:56:51 +0200 Subject: [PATCH 051/237] net: tulip: Remove CONFIG_TULIP_* These macros are not used by any board, remove them to simplify the driver. The EEPROM accessors are still retained however, as those might still be useful. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- README | 2 - drivers/net/dc2114x.c | 88 ++---------------------------------- scripts/config_whitelist.txt | 3 -- 3 files changed, 5 insertions(+), 88 deletions(-) diff --git a/README b/README index 08348506765..2e8ad3bc0cb 100644 --- a/README +++ b/README @@ -896,8 +896,6 @@ The following options need to be configured: CONFIG_TULIP Support for Digital 2114x chips. - Optional CONFIG_TULIP_SELECT_MEDIA for board specific - modem chip initialisation (KS8761/QS6611). CONFIG_NATSEMI Support for National dp83815 chips. diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index 43c2253f10d..40bfc5281b2 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -77,15 +77,6 @@ #define POLL_DEMAND 1 -#ifdef CONFIG_TULIP_FIX_DAVICOM -#define RESET_DM9102(dev) {\ - unsigned long i;\ - i=INL(dev, 0x0);\ - udelay(1000);\ - OUTL(dev, i | BMR_SWR, DE4X5_BMR);\ - udelay(1000);\ -} -#else #define RESET_DE4X5(dev) {\ int i;\ i=INL(dev, DE4X5_BMR);\ @@ -97,7 +88,6 @@ for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\ udelay(1000);\ } -#endif #define START_DE4X5(dev) {\ s32 omr; \ @@ -114,11 +104,7 @@ } #define NUM_RX_DESC PKTBUFSRX -#ifndef CONFIG_TULIP_FIX_DAVICOM - #define NUM_TX_DESC 1 /* Number of TX descriptors */ -#else - #define NUM_TX_DESC 4 -#endif +#define NUM_TX_DESC 1 /* Number of TX descriptors */ #define RX_BUFF_SZ PKTSIZE_ALIGN #define TOUT_LOOP 1000000 @@ -140,29 +126,22 @@ static int tx_new; /* TX descriptor ring pointer */ static char rxRingSize; static char txRingSize; -#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) static void sendto_srom(struct eth_device* dev, u_int command, u_long addr); static int getfrom_srom(struct eth_device* dev, u_long addr); static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len); static int do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len); -#endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ #ifdef UPDATE_SROM static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value); static void update_srom(struct eth_device *dev, bd_t *bis); #endif -#ifndef CONFIG_TULIP_FIX_DAVICOM static int read_srom(struct eth_device *dev, u_long ioaddr, int index); static void read_hw_addr(struct eth_device* dev, bd_t * bis); -#endif /* CONFIG_TULIP_FIX_DAVICOM */ static void send_setup_frame(struct eth_device* dev, bd_t * bis); static int dc21x4x_init(struct eth_device* dev, bd_t* bis); static int dc21x4x_send(struct eth_device *dev, void *packet, int length); static int dc21x4x_recv(struct eth_device* dev); static void dc21x4x_halt(struct eth_device* dev); -#ifdef CONFIG_TULIP_SELECT_MEDIA -extern void dc21x4x_select_media(struct eth_device* dev); -#endif #if defined(CONFIG_E500) #define phys_to_bus(a) (a) @@ -183,9 +162,6 @@ static void OUTL(struct eth_device* dev, int command, u_long addr) static struct pci_device_id supported[] = { { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST }, { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 }, -#ifdef CONFIG_TULIP_FIX_DAVICOM - { PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DAVICOM_DM9102A }, -#endif { } }; @@ -209,35 +185,22 @@ int dc21x4x_initialize(bd_t *bis) /* Get the chip configuration revision register. */ pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv); -#ifndef CONFIG_TULIP_FIX_DAVICOM if ((cfrv & CFRV_RN) < DC2114x_BRK ) { printf("Error: The chip is not DC21143.\n"); continue; } -#endif pci_read_config_word(devbusfn, PCI_COMMAND, &status); status |= -#ifdef CONFIG_TULIP_USE_IO - PCI_COMMAND_IO | -#else PCI_COMMAND_MEMORY | -#endif PCI_COMMAND_MASTER; pci_write_config_word(devbusfn, PCI_COMMAND, status); pci_read_config_word(devbusfn, PCI_COMMAND, &status); -#ifdef CONFIG_TULIP_USE_IO - if (!(status & PCI_COMMAND_IO)) { - printf("Error: Can not enable I/O access.\n"); - continue; - } -#else if (!(status & PCI_COMMAND_MEMORY)) { printf("Error: Can not enable MEMORY access.\n"); continue; } -#endif if (!(status & PCI_COMMAND_MASTER)) { printf("Error: Can not enable Bus Mastering.\n"); @@ -251,15 +214,9 @@ int dc21x4x_initialize(bd_t *bis) pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60); } -#ifdef CONFIG_TULIP_USE_IO - /* read BAR for memory space access */ - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase); - iobase &= PCI_BASE_ADDRESS_IO_MASK; -#else /* read BAR for memory space access */ pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase); iobase &= PCI_BASE_ADDRESS_MEM_MASK; -#endif debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase); dev = (struct eth_device*) malloc(sizeof *dev); @@ -270,17 +227,9 @@ int dc21x4x_initialize(bd_t *bis) } memset(dev, 0, sizeof(*dev)); -#ifdef CONFIG_TULIP_FIX_DAVICOM - sprintf(dev->name, "Davicom#%d", card_number); -#else sprintf(dev->name, "dc21x4x#%d", card_number); -#endif -#ifdef CONFIG_TULIP_USE_IO - dev->iobase = pci_io_to_phys(devbusfn, iobase); -#else dev->iobase = pci_mem_to_phys(devbusfn, iobase); -#endif dev->priv = (void*) devbusfn; dev->init = dc21x4x_init; dev->halt = dc21x4x_halt; @@ -292,9 +241,8 @@ int dc21x4x_initialize(bd_t *bis) udelay(10 * 1000); -#ifndef CONFIG_TULIP_FIX_DAVICOM read_hw_addr(dev, bis); -#endif + eth_register(dev); card_number++; @@ -311,46 +259,28 @@ static int dc21x4x_init(struct eth_device* dev, bd_t* bis) /* Ensure we're not sleeping. */ pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); -#ifdef CONFIG_TULIP_FIX_DAVICOM - RESET_DM9102(dev); -#else RESET_DE4X5(dev); -#endif if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) { printf("Error: Cannot reset ethernet controller.\n"); return -1; } -#ifdef CONFIG_TULIP_SELECT_MEDIA - dc21x4x_select_media(dev); -#else OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); -#endif for (i = 0; i < NUM_RX_DESC; i++) { rx_ring[i].status = cpu_to_le32(R_OWN); rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); rx_ring[i].buf = cpu_to_le32( phys_to_bus((u32)net_rx_packets[i])); -#ifdef CONFIG_TULIP_FIX_DAVICOM - rx_ring[i].next = cpu_to_le32( - phys_to_bus((u32)&rx_ring[(i + 1) % NUM_RX_DESC])); -#else rx_ring[i].next = 0; -#endif } for (i=0; i < NUM_TX_DESC; i++) { tx_ring[i].status = 0; tx_ring[i].des1 = 0; tx_ring[i].buf = 0; - -#ifdef CONFIG_TULIP_FIX_DAVICOM - tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC])); -#else tx_ring[i].next = 0; -#endif } rxRingSize = NUM_RX_DESC; @@ -520,9 +450,7 @@ Done: return; } -#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) -/* SROM Read and write routines. - */ +/* SROM Read and write routines. */ static void sendto_srom(struct eth_device* dev, u_int command, u_long addr) { @@ -594,13 +522,12 @@ static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, i return retval; } -#endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ -/* This executes a generic EEPROM command, typically a write or write +/* + * This executes a generic EEPROM command, typically a write or write * enable. It returns the data output from the EEPROM, and thus may * also be used for reads. */ -#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len) { unsigned retval = 0; @@ -636,9 +563,7 @@ static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd return retval; } -#endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ -#ifndef CONFIG_TULIP_FIX_DAVICOM static int read_srom(struct eth_device *dev, u_long ioaddr, int index) { int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; @@ -647,7 +572,6 @@ static int read_srom(struct eth_device *dev, u_long ioaddr, int index) (((SROM_READ_CMD << ee_addr_size) | index) << 16) | 0xffff, 3 + ee_addr_size + 16); } -#endif /* CONFIG_TULIP_FIX_DAVICOM */ #ifdef UPDATE_SROM static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value) @@ -695,7 +619,6 @@ static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_ } #endif -#ifndef CONFIG_TULIP_FIX_DAVICOM static void read_hw_addr(struct eth_device *dev, bd_t *bis) { u_short tmp, *p = (u_short *)(&dev->enetaddr[0]); @@ -721,7 +644,6 @@ Done: #endif return; } -#endif /* CONFIG_TULIP_FIX_DAVICOM */ #ifdef UPDATE_SROM static void update_srom(struct eth_device *dev, bd_t *bis) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 27125d7b8af..9b9f7df8c42 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -4076,9 +4076,6 @@ CONFIG_TSECV2_1 CONFIG_TSEC_TBI CONFIG_TSEC_TBICR_SETTINGS CONFIG_TULIP -CONFIG_TULIP_FIX_DAVICOM -CONFIG_TULIP_SELECT_MEDIA -CONFIG_TULIP_USE_IO CONFIG_TWL6030_INPUT CONFIG_TWL6030_POWER CONFIG_TWR From 3c0bcb97d6d7ed7f9b4c46eb2a6dd0e910214faf Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 18 Apr 2020 02:32:19 +0200 Subject: [PATCH 052/237] net: pcnet: Replace mips-specific accessors Replace mips-specific UNCACHED_SDRAM() macro with standard map_physmem(), which permits the driver to work on other systems than mips. Signed-off-by: Marek Vasut Cc: Daniel Schwierzeck Cc: Joe Hershberger --- drivers/net/pcnet.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 59241c95bcd..e7d6c8d714c 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -332,7 +332,9 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis) addr = (unsigned long)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->uc)); flush_dcache_range(addr, addr + sizeof(*lp->uc)); - addr = UNCACHED_SDRAM(addr); + addr = (unsigned long)map_physmem(addr, + roundup(sizeof(*lp->uc), ARCH_DMA_MINALIGN), + MAP_NOCACHE); lp->uc = (struct pcnet_uncached_priv *)addr; addr = (unsigned long)memalign(ARCH_DMA_MINALIGN, From 69529c912059ed4585f648cc6cde1a2fbd5b722b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 18 Apr 2020 05:11:05 +0200 Subject: [PATCH 053/237] net: pcnet: Switch to PCI memory access Replace the PCI IO access with PCI memory access, the card supports both, but the former does not work with QEMU SH4. Signed-off-by: Marek Vasut Cc: Daniel Schwierzeck Cc: Joe Hershberger --- drivers/net/pcnet.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index e7d6c8d714c..34a5a16cfe8 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -179,14 +179,14 @@ int pcnet_initialize(bd_t *bis) /* * Setup the PCI device. */ - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &bar); - dev->iobase = pci_io_to_phys(devbusfn, bar); + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar); + dev->iobase = pci_mem_to_phys(devbusfn, bar); dev->iobase &= ~0xf; PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ", dev->name, devbusfn, (unsigned long)dev->iobase); - command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; + command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; pci_write_config_word(devbusfn, PCI_COMMAND, command); pci_read_config_word(devbusfn, PCI_COMMAND, &status); if ((status & command) != command) { From ca5cb04b7fef31d66461cb58872d9ea32a24628b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 19 Apr 2020 03:09:47 +0200 Subject: [PATCH 054/237] net: dc2114x: Clean up init code Clean up the driver init code to bring it up to standards with U-Boot coding style, no functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/dc2114x.c | 64 +++++++++++++++++++++---------------------- 1 file changed, 31 insertions(+), 33 deletions(-) diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index 40bfc5281b2..d302d0362a9 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -167,33 +167,30 @@ static struct pci_device_id supported[] = { int dc21x4x_initialize(bd_t *bis) { - int idx=0; - int card_number = 0; - unsigned int cfrv; - unsigned char timer; - pci_dev_t devbusfn; - unsigned int iobase; - unsigned short status; - struct eth_device* dev; + struct eth_device *dev; + unsigned short status; + unsigned char timer; + unsigned int iobase; + int card_number = 0; + pci_dev_t devbusfn; + unsigned int cfrv; + int idx = 0; - while(1) { - devbusfn = pci_find_devices(supported, idx++); - if (devbusfn == -1) { + while (1) { + devbusfn = pci_find_devices(supported, idx++); + if (devbusfn == -1) break; - } /* Get the chip configuration revision register. */ pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv); - if ((cfrv & CFRV_RN) < DC2114x_BRK ) { + if ((cfrv & CFRV_RN) < DC2114x_BRK) { printf("Error: The chip is not DC21143.\n"); continue; } pci_read_config_word(devbusfn, PCI_COMMAND, &status); - status |= - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER; + status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; pci_write_config_word(devbusfn, PCI_COMMAND, status); pci_read_config_word(devbusfn, PCI_COMMAND, &status); @@ -211,30 +208,31 @@ int dc21x4x_initialize(bd_t *bis) pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer); if (timer < 0x60) { - pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60); + pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, + 0x60); } /* read BAR for memory space access */ pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase); iobase &= PCI_BASE_ADDRESS_MEM_MASK; - debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase); - - dev = (struct eth_device*) malloc(sizeof *dev); + debug("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase); + dev = (struct eth_device *)malloc(sizeof(*dev)); if (!dev) { printf("Can not allocalte memory of dc21x4x\n"); break; } + memset(dev, 0, sizeof(*dev)); sprintf(dev->name, "dc21x4x#%d", card_number); dev->iobase = pci_mem_to_phys(devbusfn, iobase); - dev->priv = (void*) devbusfn; - dev->init = dc21x4x_init; - dev->halt = dc21x4x_halt; - dev->send = dc21x4x_send; - dev->recv = dc21x4x_recv; + dev->priv = (void *)devbusfn; + dev->init = dc21x4x_init; + dev->halt = dc21x4x_halt; + dev->send = dc21x4x_send; + dev->recv = dc21x4x_recv; /* Ensure we're not sleeping. */ pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); @@ -251,10 +249,10 @@ int dc21x4x_initialize(bd_t *bis) return card_number; } -static int dc21x4x_init(struct eth_device* dev, bd_t* bis) +static int dc21x4x_init(struct eth_device *dev, bd_t *bis) { - int i; - int devbusfn = (int) dev->priv; + int i; + int devbusfn = (int)dev->priv; /* Ensure we're not sleeping. */ pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); @@ -271,12 +269,12 @@ static int dc21x4x_init(struct eth_device* dev, bd_t* bis) for (i = 0; i < NUM_RX_DESC; i++) { rx_ring[i].status = cpu_to_le32(R_OWN); rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); - rx_ring[i].buf = cpu_to_le32( - phys_to_bus((u32)net_rx_packets[i])); + rx_ring[i].buf = + cpu_to_le32(phys_to_bus((u32)net_rx_packets[i])); rx_ring[i].next = 0; } - for (i=0; i < NUM_TX_DESC; i++) { + for (i = 0; i < NUM_TX_DESC; i++) { tx_ring[i].status = 0; tx_ring[i].des1 = 0; tx_ring[i].buf = 0; @@ -291,8 +289,8 @@ static int dc21x4x_init(struct eth_device* dev, bd_t* bis) tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER); /* Tell the adapter where the TX/RX rings are located. */ - OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA); - OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA); + OUTL(dev, phys_to_bus((u32)&rx_ring), DE4X5_RRBA); + OUTL(dev, phys_to_bus((u32)&tx_ring), DE4X5_TRBA); START_DE4X5(dev); From 7c53e3364e4dc7dc4752a75f18a3d72548098365 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 19 Apr 2020 03:10:14 +0200 Subject: [PATCH 055/237] net: dc2114x: Clean up dc21x4x_send() Clean up the driver send code to bring it up to standards with U-Boot coding style, invert the loops where applicable to cut down the level of indent. No functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/dc2114x.c | 42 ++++++++++++++++++++---------------------- 1 file changed, 20 insertions(+), 22 deletions(-) diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index d302d0362a9..11ebea9c1a6 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -304,47 +304,45 @@ static int dc21x4x_init(struct eth_device *dev, bd_t *bis) static int dc21x4x_send(struct eth_device *dev, void *packet, int length) { - int status = -1; - int i; + int status = -1; + int i; if (length <= 0) { printf("%s: bad packet size: %d\n", dev->name, length); - goto Done; + goto done; } - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { - if (i >= TOUT_LOOP) { - printf("%s: tx error buffer not ready\n", dev->name); - goto Done; - } + for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { + if (i < TOUT_LOOP) + continue; + + printf("%s: tx error buffer not ready\n", dev->name); + goto done; } - tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) packet)); - tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length); + tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)packet)); + tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length); tx_ring[tx_new].status = cpu_to_le32(T_OWN); OUTL(dev, POLL_DEMAND, DE4X5_TPD); - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { - if (i >= TOUT_LOOP) { - printf(".%s: tx buffer not ready\n", dev->name); - goto Done; - } + for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { + if (i < TOUT_LOOP) + continue; + + printf(".%s: tx buffer not ready\n", dev->name); + goto done; } if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) { -#if 0 /* test-only */ - printf("TX error status = 0x%08X\n", - le32_to_cpu(tx_ring[tx_new].status)); -#endif tx_ring[tx_new].status = 0x0; - goto Done; + goto done; } status = length; - Done: - tx_new = (tx_new+1) % NUM_TX_DESC; +done: + tx_new = (tx_new + 1) % NUM_TX_DESC; return status; } From 9308df81a206e73687a8ba7a1f1b3753e2f2fd79 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 19 Apr 2020 03:10:25 +0200 Subject: [PATCH 056/237] net: dc2114x: Clean up dc21x4x_recv() Clean up the driver recv code to bring it up to standards with U-Boot coding style. No functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/dc2114x.c | 42 ++++++++++++++++++------------------------ 1 file changed, 18 insertions(+), 24 deletions(-) diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index 11ebea9c1a6..4d2e11672e1 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -346,46 +346,40 @@ done: return status; } -static int dc21x4x_recv(struct eth_device* dev) +static int dc21x4x_recv(struct eth_device *dev) { - s32 status; - int length = 0; + int length = 0; + u32 status; - for ( ; ; ) { - status = (s32)le32_to_cpu(rx_ring[rx_new].status); + while (true) { + status = le32_to_cpu(rx_ring[rx_new].status); - if (status & R_OWN) { + if (status & R_OWN) break; - } if (status & RD_LS) { - /* Valid frame status. - */ + /* Valid frame status. */ if (status & RD_ES) { - - /* There was an error. - */ + /* There was an error. */ printf("RX error status = 0x%08X\n", status); } else { - /* A valid frame received. - */ - length = (le32_to_cpu(rx_ring[rx_new].status) >> 16); + /* A valid frame received. */ + length = (le32_to_cpu(rx_ring[rx_new].status) + >> 16); - /* Pass the packet up to the protocol - * layers. - */ - net_process_received_packet( - net_rx_packets[rx_new], length - 4); + /* Pass the packet up to the protocol layers */ + net_process_received_packet + (net_rx_packets[rx_new], length - 4); } - /* Change buffer ownership for this frame, back - * to the adapter. + /* + * Change buffer ownership for this frame, + * back to the adapter. */ rx_ring[rx_new].status = cpu_to_le32(R_OWN); } - /* Update entry information. - */ + /* Update entry information. */ rx_new = (rx_new + 1) % rxRingSize; } From 5b4e7dfb879c4b127f27bd92bac68e114d5e0b70 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 19 Apr 2020 03:10:30 +0200 Subject: [PATCH 057/237] net: dc2114x: Clean up dc21x4x_halt() Clean up the driver halt code to bring it up to standards with U-Boot coding style. No functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/dc2114x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index 4d2e11672e1..6fe05113cae 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -386,9 +386,9 @@ static int dc21x4x_recv(struct eth_device *dev) return length; } -static void dc21x4x_halt(struct eth_device* dev) +static void dc21x4x_halt(struct eth_device *dev) { - int devbusfn = (int) dev->priv; + int devbusfn = (int)dev->priv; STOP_DE4X5(dev); OUTL(dev, 0, DE4X5_SICR); From 5a0c332a8a6fee7deadda5c8439782aa5f7b9ca2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 19 Apr 2020 03:10:50 +0200 Subject: [PATCH 058/237] net: dc2114x: Clean up send_setup_frame() Clean up the send_setup_frame() to bring it up to standards with U-Boot coding style, invert the loops where applicable to cut down the level of indent. No functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/dc2114x.c | 44 +++++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index 6fe05113cae..bd64c75af4c 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -396,48 +396,48 @@ static void dc21x4x_halt(struct eth_device *dev) pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP); } -static void send_setup_frame(struct eth_device* dev, bd_t *bis) +static void send_setup_frame(struct eth_device *dev, bd_t *bis) { - int i; - char setup_frame[SETUP_FRAME_LEN]; - char *pa = &setup_frame[0]; + char setup_frame[SETUP_FRAME_LEN]; + char *pa = &setup_frame[0]; + int i; memset(pa, 0xff, SETUP_FRAME_LEN); for (i = 0; i < ETH_ALEN; i++) { *(pa + (i & 1)) = dev->enetaddr[i]; - if (i & 0x01) { + if (i & 0x01) pa += 4; - } } - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { - if (i >= TOUT_LOOP) { - printf("%s: tx error buffer not ready\n", dev->name); - goto Done; - } + for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { + if (i < TOUT_LOOP) + continue; + + printf("%s: tx error buffer not ready\n", dev->name); + return; } - tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0])); - tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN); + tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)&setup_frame[0])); + tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET | SETUP_FRAME_LEN); tx_ring[tx_new].status = cpu_to_le32(T_OWN); OUTL(dev, POLL_DEMAND, DE4X5_TPD); - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { - if (i >= TOUT_LOOP) { - printf("%s: tx buffer not ready\n", dev->name); - goto Done; - } + for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { + if (i < TOUT_LOOP) + continue; + + printf("%s: tx buffer not ready\n", dev->name); + return; } if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) { - printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status)); + printf("TX error status2 = 0x%08X\n", + le32_to_cpu(tx_ring[tx_new].status)); } - tx_new = (tx_new+1) % NUM_TX_DESC; -Done: - return; + tx_new = (tx_new + 1) % NUM_TX_DESC; } /* SROM Read and write routines. */ From 2e5c2a103edeed19bfbf393e8550a7bd77e62dfa Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 19 Apr 2020 03:11:06 +0200 Subject: [PATCH 059/237] net: dc2114x: Clean up SROM operations Clean up the SROM accessors to bring them up to standards with U-Boot coding style. Sort variable into reverse xmas tree. No functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/dc2114x.c | 117 +++++++++++++++++++++++------------------- 1 file changed, 63 insertions(+), 54 deletions(-) diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index bd64c75af4c..b375906e27d 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -441,30 +441,27 @@ static void send_setup_frame(struct eth_device *dev, bd_t *bis) } /* SROM Read and write routines. */ -static void -sendto_srom(struct eth_device* dev, u_int command, u_long addr) +static void sendto_srom(struct eth_device *dev, u_int command, u_long addr) { OUTL(dev, command, addr); udelay(1); } -static int -getfrom_srom(struct eth_device* dev, u_long addr) +static int getfrom_srom(struct eth_device *dev, u_long addr) { - s32 tmp; + s32 tmp = INL(dev, addr); - tmp = INL(dev, addr); udelay(1); - return tmp; } /* Note: this routine returns extra data bits for size detection. */ -static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len) +static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, + int addr_len) { - int i; - unsigned retval = 0; int read_cmd = location | (SROM_READ_CMD << addr_len); + unsigned int retval = 0; + int i; sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); @@ -476,14 +473,18 @@ static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, i /* Shift the read command bits out. */ for (i = 4 + addr_len; i >= 0; i--) { short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; - sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr); + + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, + ioaddr); udelay(10); - sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr); + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, + ioaddr); udelay(10); #ifdef DEBUG_SROM2 printf("%X", getfrom_srom(dev, ioaddr) & 15); #endif - retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0); + retval = (retval << 1) | + !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ); } sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); @@ -498,7 +499,8 @@ static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, i #ifdef DEBUG_SROM2 printf("%X", getfrom_srom(dev, ioaddr) & 15); #endif - retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0); + retval = (retval << 1) | + !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ); sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); udelay(10); } @@ -518,34 +520,38 @@ static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, i * enable. It returns the data output from the EEPROM, and thus may * also be used for reads. */ -static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len) +static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, + int cmd_len) { - unsigned retval = 0; + unsigned int retval = 0; #ifdef DEBUG_SROM printf(" EEPROM op 0x%x: ", cmd); #endif - sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr); + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr); /* Shift the command bits out. */ do { - short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0; - sendto_srom(dev,dataval, ioaddr); + short dataval = (cmd & BIT(cmd_len)) ? EE_WRITE_1 : EE_WRITE_0; + + sendto_srom(dev, dataval, ioaddr); udelay(10); #ifdef DEBUG_SROM2 - printf("%X", getfrom_srom(dev,ioaddr) & 15); + printf("%X", getfrom_srom(dev, ioaddr) & 15); #endif - sendto_srom(dev,dataval | DT_CLK, ioaddr); + sendto_srom(dev, dataval | DT_CLK, ioaddr); udelay(10); - retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0); + retval = (retval << 1) | + !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ); } while (--cmd_len >= 0); - sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr); + + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); /* Terminate the EEPROM access. */ - sendto_srom(dev,SROM_RD | SROM_SR, ioaddr); + sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); #ifdef DEBUG_SROM printf(" EEPROM result is 0x%5.5x.\n", retval); @@ -556,21 +562,26 @@ static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd static int read_srom(struct eth_device *dev, u_long ioaddr, int index) { - int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; + int ee_addr_size; - return do_eeprom_cmd(dev, ioaddr, - (((SROM_READ_CMD << ee_addr_size) | index) << 16) - | 0xffff, 3 + ee_addr_size + 16); + ee_addr_size = (do_read_eeprom(dev, ioaddr, 0xff, 8) & BIT(18)) ? 8 : 6; + + return do_eeprom_cmd(dev, ioaddr, 0xffff | + (((SROM_READ_CMD << ee_addr_size) | index) << 16), + 3 + ee_addr_size + 16); } #ifdef UPDATE_SROM -static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value) +static int write_srom(struct eth_device *dev, u_long ioaddr, int index, + int new_value) { - int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; - int i; unsigned short newval; + int ee_addr_size; + int i; - udelay(10*1000); /* test-only */ + ee_addr_size = (do_read_eeprom(dev, ioaddr, 0xff, 8) & BIT(18)) ? 8 : 6; + + udelay(10 * 1000); /* test-only */ #ifdef DEBUG_SROM printf("ee_addr_size=%d.\n", ee_addr_size); @@ -578,33 +589,37 @@ static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_ #endif /* Enable programming modes. */ - do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size); + do_eeprom_cmd(dev, ioaddr, 0x4f << (ee_addr_size - 4), + 3 + ee_addr_size); /* Do the actual write. */ - do_eeprom_cmd(dev, ioaddr, - (((SROM_WRITE_CMD<> 1); i++) { - tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i)); + tmp = read_srom(dev, DE4X5_APROM, (SROM_HWADD >> 1) + i); *p = le16_to_cpu(tmp); j += *p++; } - if ((j == 0) || (j == 0x2fffd)) { - memset (dev->enetaddr, 0, ETH_ALEN); - debug ("Warning: can't read HW address from SROM.\n"); - goto Done; - } - - return; - -Done: + if (!j || j == 0x2fffd) { + memset(dev->enetaddr, 0, ETH_ALEN); + debug("Warning: can't read HW address from SROM.\n"); #ifdef UPDATE_SROM - update_srom(dev, bis); + update_srom(dev, bis); #endif - return; + } } #ifdef UPDATE_SROM static void update_srom(struct eth_device *dev, bd_t *bis) { - int i; static unsigned short eeprom[0x40] = { 0x140b, 0x6610, 0x0000, 0x0000, /* 00 */ 0x0000, 0x0000, 0x0000, 0x0000, /* 04 */ @@ -658,16 +666,17 @@ static void update_srom(struct eth_device *dev, bd_t *bis) 0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */ }; uchar enetaddr[6]; + int i; /* Ethernet Addr... */ if (!eth_env_get_enetaddr("ethaddr", enetaddr)) return; + eeprom[0x0a] = (enetaddr[1] << 8) | enetaddr[0]; eeprom[0x0b] = (enetaddr[3] << 8) | enetaddr[2]; eeprom[0x0c] = (enetaddr[5] << 8) | enetaddr[4]; - for (i=0; i<0x40; i++) { + for (i = 0; i < 0x40; i++) write_srom(dev, DE4X5_APROM, i, eeprom[i]); - } } -#endif /* UPDATE_SROM */ +#endif /* UPDATE_SROM */ From eb216f1e0005ea1b3e125efeb32d72d1691eea2d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 19 Apr 2020 03:09:26 +0200 Subject: [PATCH 060/237] net: dc2114x: Clean up remaining driver code Clean up the remaining driver code, macro space alignment, function declaration indent, replace __attribute__((aligned(32))) with plain __aligned(32). No functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/dc2114x.c | 82 +++++++++++++++++++++---------------------- 1 file changed, 41 insertions(+), 41 deletions(-) diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index b375906e27d..007e4cecb69 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -12,19 +12,17 @@ #undef UPDATE_SROM -/* PCI Registers. - */ -#define PCI_CFDA_PSM 0x43 +/* PCI Registers. */ +#define PCI_CFDA_PSM 0x43 #define CFRV_RN 0x000000f0 /* Revision Number */ #define WAKEUP 0x00 /* Power Saving Wakeup */ #define SLEEP 0x80 /* Power Saving Sleep Mode */ -#define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */ +#define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */ -/* Ethernet chip registers. - */ +/* Ethernet chip registers. */ #define DE4X5_BMR 0x000 /* Bus Mode Register */ #define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */ #define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */ @@ -34,8 +32,7 @@ #define DE4X5_SICR 0x068 /* SIA Connectivity Register */ #define DE4X5_APROM 0x048 /* Ethernet Address PROM */ -/* Register bits. - */ +/* Register bits. */ #define BMR_SWR 0x00000001 /* Software Reset */ #define STS_TS 0x00700000 /* Transmit Process State */ #define STS_RS 0x000e0000 /* Receive Process State */ @@ -45,8 +42,7 @@ #define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */ #define OMR_PM 0x00000080 /* Pass All Multicast */ -/* Descriptor bits. - */ +/* Descriptor bits. */ #define R_OWN 0x80000000 /* Own Bit */ #define RD_RER 0x02000000 /* Receive End Of Ring */ #define RD_LS 0x00000100 /* Last Descriptor */ @@ -63,12 +59,12 @@ #define SROM_READ_CMD 6 #define SROM_ERASE_CMD 7 -#define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */ +#define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */ #define SROM_RD 0x00004000 /* Read from Boot ROM */ -#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ -#define EE_WRITE_0 0x4801 -#define EE_WRITE_1 0x4805 -#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ +#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ +#define EE_WRITE_0 0x4801 +#define EE_WRITE_1 0x4805 +#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ #define SROM_SR 0x00000800 /* Select Serial ROM when set */ #define DT_IN 0x00000004 /* Serial Data In */ @@ -79,13 +75,13 @@ #define RESET_DE4X5(dev) {\ int i;\ - i=INL(dev, DE4X5_BMR);\ + i = INL(dev, DE4X5_BMR);\ udelay(1000);\ OUTL(dev, i | BMR_SWR, DE4X5_BMR);\ udelay(1000);\ OUTL(dev, i, DE4X5_BMR);\ udelay(1000);\ - for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\ + for (i = 0; i < 5; i++) {INL(dev, DE4X5_BMR); udelay(10000); } \ udelay(1000);\ } @@ -99,7 +95,7 @@ #define STOP_DE4X5(dev) {\ s32 omr; \ omr = INL(dev, DE4X5_OMR);\ - omr &= ~(OMR_ST|OMR_SR);\ + omr &= ~(OMR_ST | OMR_SR);\ OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ \ } @@ -118,30 +114,34 @@ struct de4x5_desc { u32 next; }; -static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring */ -static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring */ -static int rx_new; /* RX descriptor ring pointer */ -static int tx_new; /* TX descriptor ring pointer */ +/* RX and TX descriptor ring */ +static struct de4x5_desc rx_ring[NUM_RX_DESC] __aligned(32); +static struct de4x5_desc tx_ring[NUM_TX_DESC] __aligned(32); +static int rx_new; /* RX descriptor ring pointer */ +static int tx_new; /* TX descriptor ring pointer */ -static char rxRingSize; -static char txRingSize; +static char rx_ring_size; +static char tx_ring_size; -static void sendto_srom(struct eth_device* dev, u_int command, u_long addr); -static int getfrom_srom(struct eth_device* dev, u_long addr); -static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len); -static int do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len); +static void sendto_srom(struct eth_device *dev, u_int command, u_long addr); +static int getfrom_srom(struct eth_device *dev, u_long addr); +static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, + int cmd, int cmd_len); +static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, + int location, int addr_len); #ifdef UPDATE_SROM -static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value); +static int write_srom(struct eth_device *dev, u_long ioaddr, + int index, int new_value); static void update_srom(struct eth_device *dev, bd_t *bis); #endif static int read_srom(struct eth_device *dev, u_long ioaddr, int index); -static void read_hw_addr(struct eth_device* dev, bd_t * bis); -static void send_setup_frame(struct eth_device* dev, bd_t * bis); +static void read_hw_addr(struct eth_device *dev, bd_t *bis); +static void send_setup_frame(struct eth_device *dev, bd_t *bis); -static int dc21x4x_init(struct eth_device* dev, bd_t* bis); +static int dc21x4x_init(struct eth_device *dev, bd_t *bis); static int dc21x4x_send(struct eth_device *dev, void *packet, int length); -static int dc21x4x_recv(struct eth_device* dev); -static void dc21x4x_halt(struct eth_device* dev); +static int dc21x4x_recv(struct eth_device *dev); +static void dc21x4x_halt(struct eth_device *dev); #if defined(CONFIG_E500) #define phys_to_bus(a) (a) @@ -149,12 +149,12 @@ static void dc21x4x_halt(struct eth_device* dev); #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) #endif -static int INL(struct eth_device* dev, u_long addr) +static int INL(struct eth_device *dev, u_long addr) { return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase)); } -static void OUTL(struct eth_device* dev, int command, u_long addr) +static void OUTL(struct eth_device *dev, int command, u_long addr) { *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command); } @@ -281,12 +281,12 @@ static int dc21x4x_init(struct eth_device *dev, bd_t *bis) tx_ring[i].next = 0; } - rxRingSize = NUM_RX_DESC; - txRingSize = NUM_TX_DESC; + rx_ring_size = NUM_RX_DESC; + tx_ring_size = NUM_TX_DESC; /* Write the end of list marker to the descriptor lists. */ - rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER); - tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER); + rx_ring[rx_ring_size - 1].des1 |= cpu_to_le32(RD_RER); + tx_ring[tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER); /* Tell the adapter where the TX/RX rings are located. */ OUTL(dev, phys_to_bus((u32)&rx_ring), DE4X5_RRBA); @@ -380,7 +380,7 @@ static int dc21x4x_recv(struct eth_device *dev) } /* Update entry information. */ - rx_new = (rx_new + 1) % rxRingSize; + rx_new = (rx_new + 1) % rx_ring_size; } return length; From 04da06120909729bc9d0d3974d06dc2ef758e821 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 19 Apr 2020 03:36:46 +0200 Subject: [PATCH 061/237] net: dc2114x: Clean up DE4X5 macros Replace these macros with static functions to permit the compiler to do type checking on the functions. The INL()/OUTL() functions have to be moved in this patch as well, as those DE4X5 macros are using them. No functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/dc2114x.c | 89 ++++++++++++++++++++++++------------------- 1 file changed, 50 insertions(+), 39 deletions(-) diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index 007e4cecb69..a85fb76d53c 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -73,30 +73,57 @@ #define POLL_DEMAND 1 -#define RESET_DE4X5(dev) {\ - int i;\ - i = INL(dev, DE4X5_BMR);\ - udelay(1000);\ - OUTL(dev, i | BMR_SWR, DE4X5_BMR);\ - udelay(1000);\ - OUTL(dev, i, DE4X5_BMR);\ - udelay(1000);\ - for (i = 0; i < 5; i++) {INL(dev, DE4X5_BMR); udelay(10000); } \ - udelay(1000);\ +#if defined(CONFIG_E500) +#define phys_to_bus(a) (a) +#else +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) +#endif + +static int INL(struct eth_device *dev, u_long addr) +{ + return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase)); } -#define START_DE4X5(dev) {\ - s32 omr; \ - omr = INL(dev, DE4X5_OMR);\ - omr |= OMR_ST | OMR_SR;\ - OUTL(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */\ +static void OUTL(struct eth_device *dev, int command, u_long addr) +{ + *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command); } -#define STOP_DE4X5(dev) {\ - s32 omr; \ - omr = INL(dev, DE4X5_OMR);\ - omr &= ~(OMR_ST | OMR_SR);\ - OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ \ +static void reset_de4x5(struct eth_device *dev) +{ + int i; + + i = INL(dev, DE4X5_BMR); + mdelay(1); + OUTL(dev, i | BMR_SWR, DE4X5_BMR); + mdelay(1); + OUTL(dev, i, DE4X5_BMR); + mdelay(1); + + for (i = 0; i < 5; i++) { + INL(dev, DE4X5_BMR); + mdelay(10); + } + + mdelay(1); +} + +static void start_de4x5(struct eth_device *dev) +{ + s32 omr; + + omr = INL(dev, DE4X5_OMR); + omr |= OMR_ST | OMR_SR; + OUTL(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */ +} + +static void stop_de4x5(struct eth_device *dev) +{ + s32 omr; + + omr = INL(dev, DE4X5_OMR); + omr &= ~(OMR_ST | OMR_SR); + OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ } #define NUM_RX_DESC PKTBUFSRX @@ -143,22 +170,6 @@ static int dc21x4x_send(struct eth_device *dev, void *packet, int length); static int dc21x4x_recv(struct eth_device *dev); static void dc21x4x_halt(struct eth_device *dev); -#if defined(CONFIG_E500) -#define phys_to_bus(a) (a) -#else -#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) -#endif - -static int INL(struct eth_device *dev, u_long addr) -{ - return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase)); -} - -static void OUTL(struct eth_device *dev, int command, u_long addr) -{ - *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command); -} - static struct pci_device_id supported[] = { { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST }, { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 }, @@ -257,7 +268,7 @@ static int dc21x4x_init(struct eth_device *dev, bd_t *bis) /* Ensure we're not sleeping. */ pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); - RESET_DE4X5(dev); + reset_de4x5(dev); if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) { printf("Error: Cannot reset ethernet controller.\n"); @@ -292,7 +303,7 @@ static int dc21x4x_init(struct eth_device *dev, bd_t *bis) OUTL(dev, phys_to_bus((u32)&rx_ring), DE4X5_RRBA); OUTL(dev, phys_to_bus((u32)&tx_ring), DE4X5_TRBA); - START_DE4X5(dev); + start_de4x5(dev); tx_new = 0; rx_new = 0; @@ -390,7 +401,7 @@ static void dc21x4x_halt(struct eth_device *dev) { int devbusfn = (int)dev->priv; - STOP_DE4X5(dev); + stop_de4x5(dev); OUTL(dev, 0, DE4X5_SICR); pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP); From 3b7b9e2e71e7334198d696a03f3552bbc812ce9b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 19 Apr 2020 03:40:03 +0200 Subject: [PATCH 062/237] net: dc2114x: Clean up INL/OUTL functions Rename these functions to dc2114x_{inl,outl}(), use u32 values in them instead of plain signed integers as all those values are in fact register values and the driver code does bitwise operations on them. No functional change intended. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/dc2114x.c | 48 +++++++++++++++++++++---------------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index a85fb76d53c..2bbe4e5d602 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -79,29 +79,29 @@ #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) #endif -static int INL(struct eth_device *dev, u_long addr) +static u32 dc2114x_inl(struct eth_device *dev, u32 addr) { - return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase)); + return le32_to_cpu(*(volatile u32 *)(addr + dev->iobase)); } -static void OUTL(struct eth_device *dev, int command, u_long addr) +static void dc2114x_outl(struct eth_device *dev, u32 command, u32 addr) { - *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command); + *(volatile u32 *)(addr + dev->iobase) = cpu_to_le32(command); } static void reset_de4x5(struct eth_device *dev) { - int i; + u32 i; - i = INL(dev, DE4X5_BMR); + i = dc2114x_inl(dev, DE4X5_BMR); mdelay(1); - OUTL(dev, i | BMR_SWR, DE4X5_BMR); + dc2114x_outl(dev, i | BMR_SWR, DE4X5_BMR); mdelay(1); - OUTL(dev, i, DE4X5_BMR); + dc2114x_outl(dev, i, DE4X5_BMR); mdelay(1); for (i = 0; i < 5; i++) { - INL(dev, DE4X5_BMR); + dc2114x_inl(dev, DE4X5_BMR); mdelay(10); } @@ -110,20 +110,20 @@ static void reset_de4x5(struct eth_device *dev) static void start_de4x5(struct eth_device *dev) { - s32 omr; + u32 omr; - omr = INL(dev, DE4X5_OMR); + omr = dc2114x_inl(dev, DE4X5_OMR); omr |= OMR_ST | OMR_SR; - OUTL(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */ + dc2114x_outl(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */ } static void stop_de4x5(struct eth_device *dev) { - s32 omr; + u32 omr; - omr = INL(dev, DE4X5_OMR); + omr = dc2114x_inl(dev, DE4X5_OMR); omr &= ~(OMR_ST | OMR_SR); - OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ + dc2114x_outl(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ } #define NUM_RX_DESC PKTBUFSRX @@ -270,12 +270,12 @@ static int dc21x4x_init(struct eth_device *dev, bd_t *bis) reset_de4x5(dev); - if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) { + if (dc2114x_inl(dev, DE4X5_STS) & (STS_TS | STS_RS)) { printf("Error: Cannot reset ethernet controller.\n"); return -1; } - OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); + dc2114x_outl(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); for (i = 0; i < NUM_RX_DESC; i++) { rx_ring[i].status = cpu_to_le32(R_OWN); @@ -300,8 +300,8 @@ static int dc21x4x_init(struct eth_device *dev, bd_t *bis) tx_ring[tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER); /* Tell the adapter where the TX/RX rings are located. */ - OUTL(dev, phys_to_bus((u32)&rx_ring), DE4X5_RRBA); - OUTL(dev, phys_to_bus((u32)&tx_ring), DE4X5_TRBA); + dc2114x_outl(dev, phys_to_bus((u32)&rx_ring), DE4X5_RRBA); + dc2114x_outl(dev, phys_to_bus((u32)&tx_ring), DE4X5_TRBA); start_de4x5(dev); @@ -335,7 +335,7 @@ static int dc21x4x_send(struct eth_device *dev, void *packet, int length) tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length); tx_ring[tx_new].status = cpu_to_le32(T_OWN); - OUTL(dev, POLL_DEMAND, DE4X5_TPD); + dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD); for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { if (i < TOUT_LOOP) @@ -402,7 +402,7 @@ static void dc21x4x_halt(struct eth_device *dev) int devbusfn = (int)dev->priv; stop_de4x5(dev); - OUTL(dev, 0, DE4X5_SICR); + dc2114x_outl(dev, 0, DE4X5_SICR); pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP); } @@ -433,7 +433,7 @@ static void send_setup_frame(struct eth_device *dev, bd_t *bis) tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET | SETUP_FRAME_LEN); tx_ring[tx_new].status = cpu_to_le32(T_OWN); - OUTL(dev, POLL_DEMAND, DE4X5_TPD); + dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD); for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { if (i < TOUT_LOOP) @@ -454,13 +454,13 @@ static void send_setup_frame(struct eth_device *dev, bd_t *bis) /* SROM Read and write routines. */ static void sendto_srom(struct eth_device *dev, u_int command, u_long addr) { - OUTL(dev, command, addr); + dc2114x_outl(dev, command, addr); udelay(1); } static int getfrom_srom(struct eth_device *dev, u_long addr) { - s32 tmp = INL(dev, addr); + u32 tmp = dc2114x_inl(dev, addr); udelay(1); return tmp; From dbe9c0c1457dad8446f1d9aac5f4cbd4ee6db060 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 19 Apr 2020 04:00:49 +0200 Subject: [PATCH 063/237] net: dc2114x: Reorganize driver Move the functions in the driver around to better fit future DM conversion, drop function forward declarations. No functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/dc2114x.c | 672 ++++++++++++++++++++---------------------- 1 file changed, 325 insertions(+), 347 deletions(-) diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index 2bbe4e5d602..9de9634cd51 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -79,6 +79,30 @@ #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) #endif +#define NUM_RX_DESC PKTBUFSRX +#define NUM_TX_DESC 1 /* Number of TX descriptors */ +#define RX_BUFF_SZ PKTSIZE_ALIGN + +#define TOUT_LOOP 1000000 + +#define SETUP_FRAME_LEN 192 + +struct de4x5_desc { + volatile s32 status; + u32 des1; + u32 buf; + u32 next; +}; + +/* RX and TX descriptor ring */ +static struct de4x5_desc rx_ring[NUM_RX_DESC] __aligned(32); +static struct de4x5_desc tx_ring[NUM_TX_DESC] __aligned(32); +static int rx_new; /* RX descriptor ring pointer */ +static int tx_new; /* TX descriptor ring pointer */ + +static char rx_ring_size; +static char tx_ring_size; + static u32 dc2114x_inl(struct eth_device *dev, u32 addr) { return le32_to_cpu(*(volatile u32 *)(addr + dev->iobase)); @@ -126,331 +150,6 @@ static void stop_de4x5(struct eth_device *dev) dc2114x_outl(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ } -#define NUM_RX_DESC PKTBUFSRX -#define NUM_TX_DESC 1 /* Number of TX descriptors */ -#define RX_BUFF_SZ PKTSIZE_ALIGN - -#define TOUT_LOOP 1000000 - -#define SETUP_FRAME_LEN 192 - -struct de4x5_desc { - volatile s32 status; - u32 des1; - u32 buf; - u32 next; -}; - -/* RX and TX descriptor ring */ -static struct de4x5_desc rx_ring[NUM_RX_DESC] __aligned(32); -static struct de4x5_desc tx_ring[NUM_TX_DESC] __aligned(32); -static int rx_new; /* RX descriptor ring pointer */ -static int tx_new; /* TX descriptor ring pointer */ - -static char rx_ring_size; -static char tx_ring_size; - -static void sendto_srom(struct eth_device *dev, u_int command, u_long addr); -static int getfrom_srom(struct eth_device *dev, u_long addr); -static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, - int cmd, int cmd_len); -static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, - int location, int addr_len); -#ifdef UPDATE_SROM -static int write_srom(struct eth_device *dev, u_long ioaddr, - int index, int new_value); -static void update_srom(struct eth_device *dev, bd_t *bis); -#endif -static int read_srom(struct eth_device *dev, u_long ioaddr, int index); -static void read_hw_addr(struct eth_device *dev, bd_t *bis); -static void send_setup_frame(struct eth_device *dev, bd_t *bis); - -static int dc21x4x_init(struct eth_device *dev, bd_t *bis); -static int dc21x4x_send(struct eth_device *dev, void *packet, int length); -static int dc21x4x_recv(struct eth_device *dev); -static void dc21x4x_halt(struct eth_device *dev); - -static struct pci_device_id supported[] = { - { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST }, - { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 }, - { } -}; - -int dc21x4x_initialize(bd_t *bis) -{ - struct eth_device *dev; - unsigned short status; - unsigned char timer; - unsigned int iobase; - int card_number = 0; - pci_dev_t devbusfn; - unsigned int cfrv; - int idx = 0; - - while (1) { - devbusfn = pci_find_devices(supported, idx++); - if (devbusfn == -1) - break; - - /* Get the chip configuration revision register. */ - pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv); - - if ((cfrv & CFRV_RN) < DC2114x_BRK) { - printf("Error: The chip is not DC21143.\n"); - continue; - } - - pci_read_config_word(devbusfn, PCI_COMMAND, &status); - status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; - pci_write_config_word(devbusfn, PCI_COMMAND, status); - - pci_read_config_word(devbusfn, PCI_COMMAND, &status); - if (!(status & PCI_COMMAND_MEMORY)) { - printf("Error: Can not enable MEMORY access.\n"); - continue; - } - - if (!(status & PCI_COMMAND_MASTER)) { - printf("Error: Can not enable Bus Mastering.\n"); - continue; - } - - /* Check the latency timer for values >= 0x60. */ - pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer); - - if (timer < 0x60) { - pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, - 0x60); - } - - /* read BAR for memory space access */ - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase); - iobase &= PCI_BASE_ADDRESS_MEM_MASK; - debug("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase); - - dev = (struct eth_device *)malloc(sizeof(*dev)); - if (!dev) { - printf("Can not allocalte memory of dc21x4x\n"); - break; - } - - memset(dev, 0, sizeof(*dev)); - - sprintf(dev->name, "dc21x4x#%d", card_number); - - dev->iobase = pci_mem_to_phys(devbusfn, iobase); - dev->priv = (void *)devbusfn; - dev->init = dc21x4x_init; - dev->halt = dc21x4x_halt; - dev->send = dc21x4x_send; - dev->recv = dc21x4x_recv; - - /* Ensure we're not sleeping. */ - pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); - - udelay(10 * 1000); - - read_hw_addr(dev, bis); - - eth_register(dev); - - card_number++; - } - - return card_number; -} - -static int dc21x4x_init(struct eth_device *dev, bd_t *bis) -{ - int i; - int devbusfn = (int)dev->priv; - - /* Ensure we're not sleeping. */ - pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); - - reset_de4x5(dev); - - if (dc2114x_inl(dev, DE4X5_STS) & (STS_TS | STS_RS)) { - printf("Error: Cannot reset ethernet controller.\n"); - return -1; - } - - dc2114x_outl(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); - - for (i = 0; i < NUM_RX_DESC; i++) { - rx_ring[i].status = cpu_to_le32(R_OWN); - rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); - rx_ring[i].buf = - cpu_to_le32(phys_to_bus((u32)net_rx_packets[i])); - rx_ring[i].next = 0; - } - - for (i = 0; i < NUM_TX_DESC; i++) { - tx_ring[i].status = 0; - tx_ring[i].des1 = 0; - tx_ring[i].buf = 0; - tx_ring[i].next = 0; - } - - rx_ring_size = NUM_RX_DESC; - tx_ring_size = NUM_TX_DESC; - - /* Write the end of list marker to the descriptor lists. */ - rx_ring[rx_ring_size - 1].des1 |= cpu_to_le32(RD_RER); - tx_ring[tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER); - - /* Tell the adapter where the TX/RX rings are located. */ - dc2114x_outl(dev, phys_to_bus((u32)&rx_ring), DE4X5_RRBA); - dc2114x_outl(dev, phys_to_bus((u32)&tx_ring), DE4X5_TRBA); - - start_de4x5(dev); - - tx_new = 0; - rx_new = 0; - - send_setup_frame(dev, bis); - - return 0; -} - -static int dc21x4x_send(struct eth_device *dev, void *packet, int length) -{ - int status = -1; - int i; - - if (length <= 0) { - printf("%s: bad packet size: %d\n", dev->name, length); - goto done; - } - - for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { - if (i < TOUT_LOOP) - continue; - - printf("%s: tx error buffer not ready\n", dev->name); - goto done; - } - - tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)packet)); - tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length); - tx_ring[tx_new].status = cpu_to_le32(T_OWN); - - dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD); - - for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { - if (i < TOUT_LOOP) - continue; - - printf(".%s: tx buffer not ready\n", dev->name); - goto done; - } - - if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) { - tx_ring[tx_new].status = 0x0; - goto done; - } - - status = length; - -done: - tx_new = (tx_new + 1) % NUM_TX_DESC; - return status; -} - -static int dc21x4x_recv(struct eth_device *dev) -{ - int length = 0; - u32 status; - - while (true) { - status = le32_to_cpu(rx_ring[rx_new].status); - - if (status & R_OWN) - break; - - if (status & RD_LS) { - /* Valid frame status. */ - if (status & RD_ES) { - /* There was an error. */ - printf("RX error status = 0x%08X\n", status); - } else { - /* A valid frame received. */ - length = (le32_to_cpu(rx_ring[rx_new].status) - >> 16); - - /* Pass the packet up to the protocol layers */ - net_process_received_packet - (net_rx_packets[rx_new], length - 4); - } - - /* - * Change buffer ownership for this frame, - * back to the adapter. - */ - rx_ring[rx_new].status = cpu_to_le32(R_OWN); - } - - /* Update entry information. */ - rx_new = (rx_new + 1) % rx_ring_size; - } - - return length; -} - -static void dc21x4x_halt(struct eth_device *dev) -{ - int devbusfn = (int)dev->priv; - - stop_de4x5(dev); - dc2114x_outl(dev, 0, DE4X5_SICR); - - pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP); -} - -static void send_setup_frame(struct eth_device *dev, bd_t *bis) -{ - char setup_frame[SETUP_FRAME_LEN]; - char *pa = &setup_frame[0]; - int i; - - memset(pa, 0xff, SETUP_FRAME_LEN); - - for (i = 0; i < ETH_ALEN; i++) { - *(pa + (i & 1)) = dev->enetaddr[i]; - if (i & 0x01) - pa += 4; - } - - for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { - if (i < TOUT_LOOP) - continue; - - printf("%s: tx error buffer not ready\n", dev->name); - return; - } - - tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)&setup_frame[0])); - tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET | SETUP_FRAME_LEN); - tx_ring[tx_new].status = cpu_to_le32(T_OWN); - - dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD); - - for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { - if (i < TOUT_LOOP) - continue; - - printf("%s: tx buffer not ready\n", dev->name); - return; - } - - if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) { - printf("TX error status2 = 0x%08X\n", - le32_to_cpu(tx_ring[tx_new].status)); - } - - tx_new = (tx_new + 1) % NUM_TX_DESC; -} - /* SROM Read and write routines. */ static void sendto_srom(struct eth_device *dev, u_int command, u_long addr) { @@ -633,29 +332,7 @@ static int write_srom(struct eth_device *dev, u_long ioaddr, int index, return 1; } -#endif -static void read_hw_addr(struct eth_device *dev, bd_t *bis) -{ - u_short tmp, *p = (u_short *)(&dev->enetaddr[0]); - int i, j = 0; - - for (i = 0; i < (ETH_ALEN >> 1); i++) { - tmp = read_srom(dev, DE4X5_APROM, (SROM_HWADD >> 1) + i); - *p = le16_to_cpu(tmp); - j += *p++; - } - - if (!j || j == 0x2fffd) { - memset(dev->enetaddr, 0, ETH_ALEN); - debug("Warning: can't read HW address from SROM.\n"); -#ifdef UPDATE_SROM - update_srom(dev, bis); -#endif - } -} - -#ifdef UPDATE_SROM static void update_srom(struct eth_device *dev, bd_t *bis) { static unsigned short eeprom[0x40] = { @@ -691,3 +368,304 @@ static void update_srom(struct eth_device *dev, bd_t *bis) write_srom(dev, DE4X5_APROM, i, eeprom[i]); } #endif /* UPDATE_SROM */ + +static void send_setup_frame(struct eth_device *dev, bd_t *bis) +{ + char setup_frame[SETUP_FRAME_LEN]; + char *pa = &setup_frame[0]; + int i; + + memset(pa, 0xff, SETUP_FRAME_LEN); + + for (i = 0; i < ETH_ALEN; i++) { + *(pa + (i & 1)) = dev->enetaddr[i]; + if (i & 0x01) + pa += 4; + } + + for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { + if (i < TOUT_LOOP) + continue; + + printf("%s: tx error buffer not ready\n", dev->name); + return; + } + + tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)&setup_frame[0])); + tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET | SETUP_FRAME_LEN); + tx_ring[tx_new].status = cpu_to_le32(T_OWN); + + dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD); + + for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { + if (i < TOUT_LOOP) + continue; + + printf("%s: tx buffer not ready\n", dev->name); + return; + } + + if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) { + printf("TX error status2 = 0x%08X\n", + le32_to_cpu(tx_ring[tx_new].status)); + } + + tx_new = (tx_new + 1) % NUM_TX_DESC; +} + +static int dc21x4x_send(struct eth_device *dev, void *packet, int length) +{ + int status = -1; + int i; + + if (length <= 0) { + printf("%s: bad packet size: %d\n", dev->name, length); + goto done; + } + + for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { + if (i < TOUT_LOOP) + continue; + + printf("%s: tx error buffer not ready\n", dev->name); + goto done; + } + + tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)packet)); + tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length); + tx_ring[tx_new].status = cpu_to_le32(T_OWN); + + dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD); + + for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { + if (i < TOUT_LOOP) + continue; + + printf(".%s: tx buffer not ready\n", dev->name); + goto done; + } + + if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) { + tx_ring[tx_new].status = 0x0; + goto done; + } + + status = length; + +done: + tx_new = (tx_new + 1) % NUM_TX_DESC; + return status; +} + +static int dc21x4x_recv(struct eth_device *dev) +{ + int length = 0; + u32 status; + + while (true) { + status = le32_to_cpu(rx_ring[rx_new].status); + + if (status & R_OWN) + break; + + if (status & RD_LS) { + /* Valid frame status. */ + if (status & RD_ES) { + /* There was an error. */ + printf("RX error status = 0x%08X\n", status); + } else { + /* A valid frame received. */ + length = (le32_to_cpu(rx_ring[rx_new].status) + >> 16); + + /* Pass the packet up to the protocol layers */ + net_process_received_packet + (net_rx_packets[rx_new], length - 4); + } + + /* + * Change buffer ownership for this frame, + * back to the adapter. + */ + rx_ring[rx_new].status = cpu_to_le32(R_OWN); + } + + /* Update entry information. */ + rx_new = (rx_new + 1) % rx_ring_size; + } + + return length; +} + +static int dc21x4x_init(struct eth_device *dev, bd_t *bis) +{ + int i; + int devbusfn = (int)dev->priv; + + /* Ensure we're not sleeping. */ + pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); + + reset_de4x5(dev); + + if (dc2114x_inl(dev, DE4X5_STS) & (STS_TS | STS_RS)) { + printf("Error: Cannot reset ethernet controller.\n"); + return -1; + } + + dc2114x_outl(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); + + for (i = 0; i < NUM_RX_DESC; i++) { + rx_ring[i].status = cpu_to_le32(R_OWN); + rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); + rx_ring[i].buf = + cpu_to_le32(phys_to_bus((u32)net_rx_packets[i])); + rx_ring[i].next = 0; + } + + for (i = 0; i < NUM_TX_DESC; i++) { + tx_ring[i].status = 0; + tx_ring[i].des1 = 0; + tx_ring[i].buf = 0; + tx_ring[i].next = 0; + } + + rx_ring_size = NUM_RX_DESC; + tx_ring_size = NUM_TX_DESC; + + /* Write the end of list marker to the descriptor lists. */ + rx_ring[rx_ring_size - 1].des1 |= cpu_to_le32(RD_RER); + tx_ring[tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER); + + /* Tell the adapter where the TX/RX rings are located. */ + dc2114x_outl(dev, phys_to_bus((u32)&rx_ring), DE4X5_RRBA); + dc2114x_outl(dev, phys_to_bus((u32)&tx_ring), DE4X5_TRBA); + + start_de4x5(dev); + + tx_new = 0; + rx_new = 0; + + send_setup_frame(dev, bis); + + return 0; +} + +static void dc21x4x_halt(struct eth_device *dev) +{ + int devbusfn = (int)dev->priv; + + stop_de4x5(dev); + dc2114x_outl(dev, 0, DE4X5_SICR); + + pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP); +} + +static void read_hw_addr(struct eth_device *dev, bd_t *bis) +{ + u_short tmp, *p = (u_short *)(&dev->enetaddr[0]); + int i, j = 0; + + for (i = 0; i < (ETH_ALEN >> 1); i++) { + tmp = read_srom(dev, DE4X5_APROM, (SROM_HWADD >> 1) + i); + *p = le16_to_cpu(tmp); + j += *p++; + } + + if (!j || j == 0x2fffd) { + memset(dev->enetaddr, 0, ETH_ALEN); + debug("Warning: can't read HW address from SROM.\n"); +#ifdef UPDATE_SROM + update_srom(dev, bis); +#endif + } +} + +static struct pci_device_id supported[] = { + { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST }, + { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 }, + { } +}; + +int dc21x4x_initialize(bd_t *bis) +{ + struct eth_device *dev; + unsigned short status; + unsigned char timer; + unsigned int iobase; + int card_number = 0; + pci_dev_t devbusfn; + unsigned int cfrv; + int idx = 0; + + while (1) { + devbusfn = pci_find_devices(supported, idx++); + if (devbusfn == -1) + break; + + /* Get the chip configuration revision register. */ + pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv); + + if ((cfrv & CFRV_RN) < DC2114x_BRK) { + printf("Error: The chip is not DC21143.\n"); + continue; + } + + pci_read_config_word(devbusfn, PCI_COMMAND, &status); + status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + pci_write_config_word(devbusfn, PCI_COMMAND, status); + + pci_read_config_word(devbusfn, PCI_COMMAND, &status); + if (!(status & PCI_COMMAND_MEMORY)) { + printf("Error: Can not enable MEMORY access.\n"); + continue; + } + + if (!(status & PCI_COMMAND_MASTER)) { + printf("Error: Can not enable Bus Mastering.\n"); + continue; + } + + /* Check the latency timer for values >= 0x60. */ + pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer); + + if (timer < 0x60) { + pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, + 0x60); + } + + /* read BAR for memory space access */ + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase); + iobase &= PCI_BASE_ADDRESS_MEM_MASK; + debug("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase); + + dev = (struct eth_device *)malloc(sizeof(*dev)); + if (!dev) { + printf("Can not allocalte memory of dc21x4x\n"); + break; + } + + memset(dev, 0, sizeof(*dev)); + + sprintf(dev->name, "dc21x4x#%d", card_number); + + dev->iobase = pci_mem_to_phys(devbusfn, iobase); + dev->priv = (void *)devbusfn; + dev->init = dc21x4x_init; + dev->halt = dc21x4x_halt; + dev->send = dc21x4x_send; + dev->recv = dc21x4x_recv; + + /* Ensure we're not sleeping. */ + pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); + + udelay(10 * 1000); + + read_hw_addr(dev, bis); + + eth_register(dev); + + card_number++; + } + + return card_number; +} From c2abfca9be3a62a98c1a1b77a11cd01092c0160f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 19 Apr 2020 04:05:44 +0200 Subject: [PATCH 064/237] net: dc2114x: Switch DEBUG_SROM{,2} to debug_cond() Replace the adhoc debugging ifdeffery with debug_cond() and an internal SROM_DEBUG macro to select the debug level. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/dc2114x.c | 57 ++++++++++++++++--------------------------- 1 file changed, 21 insertions(+), 36 deletions(-) diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index 9de9634cd51..d008696b0ff 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -7,8 +7,7 @@ #include #include -#undef DEBUG_SROM -#undef DEBUG_SROM2 +#define SROM_DLEVEL 0 #undef UPDATE_SROM @@ -176,9 +175,7 @@ static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); -#ifdef DEBUG_SROM - printf(" EEPROM read at %d ", location); -#endif + debug_cond(SROM_DLEVEL >= 1, " EEPROM read at %d ", location); /* Shift the read command bits out. */ for (i = 4 + addr_len; i >= 0; i--) { @@ -190,25 +187,21 @@ static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr); udelay(10); -#ifdef DEBUG_SROM2 - printf("%X", getfrom_srom(dev, ioaddr) & 15); -#endif + debug_cond(SROM_DLEVEL >= 2, "%X", + getfrom_srom(dev, ioaddr) & 15); retval = (retval << 1) | !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ); } sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); -#ifdef DEBUG_SROM2 - printf(" :%X:", getfrom_srom(dev, ioaddr) & 15); -#endif + debug_cond(SROM_DLEVEL >= 2, " :%X:", getfrom_srom(dev, ioaddr) & 15); for (i = 16; i > 0; i--) { sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr); udelay(10); -#ifdef DEBUG_SROM2 - printf("%X", getfrom_srom(dev, ioaddr) & 15); -#endif + debug_cond(SROM_DLEVEL >= 2, "%X", + getfrom_srom(dev, ioaddr) & 15); retval = (retval << 1) | !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ); sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); @@ -218,9 +211,8 @@ static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, /* Terminate the EEPROM access. */ sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); -#ifdef DEBUG_SROM2 - printf(" EEPROM value at %d is %5.5x.\n", location, retval); -#endif + debug_cond(SROM_DLEVEL >= 2, " EEPROM value at %d is %5.5x.\n", + location, retval); return retval; } @@ -235,9 +227,7 @@ static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, { unsigned int retval = 0; -#ifdef DEBUG_SROM - printf(" EEPROM op 0x%x: ", cmd); -#endif + debug_cond(SROM_DLEVEL >= 1, " EEPROM op 0x%x: ", cmd); sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr); @@ -248,9 +238,8 @@ static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, sendto_srom(dev, dataval, ioaddr); udelay(10); -#ifdef DEBUG_SROM2 - printf("%X", getfrom_srom(dev, ioaddr) & 15); -#endif + debug_cond(SROM_DLEVEL >= 2, "%X", + getfrom_srom(dev, ioaddr) & 15); sendto_srom(dev, dataval | DT_CLK, ioaddr); udelay(10); @@ -263,9 +252,7 @@ static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, /* Terminate the EEPROM access. */ sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); -#ifdef DEBUG_SROM - printf(" EEPROM result is 0x%5.5x.\n", retval); -#endif + debug_cond(SROM_DLEVEL >= 1, " EEPROM result is 0x%5.5x.\n", retval); return retval; } @@ -293,10 +280,10 @@ static int write_srom(struct eth_device *dev, u_long ioaddr, int index, udelay(10 * 1000); /* test-only */ -#ifdef DEBUG_SROM - printf("ee_addr_size=%d.\n", ee_addr_size); - printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index); -#endif + debug_cond(SROM_DLEVEL >= 1, "ee_addr_size=%d.\n", ee_addr_size); + debug_cond(SROM_DLEVEL >= 1, + "Writing new entry 0x%4.4x to offset %d.\n", + new_value, index); /* Enable programming modes. */ do_eeprom_cmd(dev, ioaddr, 0x4f << (ee_addr_size - 4), @@ -314,9 +301,7 @@ static int write_srom(struct eth_device *dev, u_long ioaddr, int index, break; } -#ifdef DEBUG_SROM - printf(" Write finished after %d ticks.\n", i); -#endif + debug_cond(SROM_DLEVEL >= 1, " Write finished after %d ticks.\n", i); /* Disable programming. */ do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size - 4)), @@ -326,9 +311,9 @@ static int write_srom(struct eth_device *dev, u_long ioaddr, int index, newval = do_eeprom_cmd(dev, ioaddr, (((SROM_READ_CMD << ee_addr_size) | index) << 16) | 0xffff, 3 + ee_addr_size + 16); -#ifdef DEBUG_SROM - printf(" New value at offset %d is %4.4x.\n", index, newval); -#endif + + debug_cond(SROM_DLEVEL >= 1, " New value at offset %d is %4.4x.\n", + index, newval); return 1; } From 4332d8061785b697ae7bdf3945adb55ba4da696b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 23 Mar 2020 02:02:57 +0100 Subject: [PATCH 065/237] net: dwc_eth_qos: Fully rewrite RX descriptor field 3 The RX descriptor field 3 should contain only OWN and BUF1V bits before being used for receiving data by the DMA engine. However, right now, if the descriptor was already used for receiving data and is being cleared, the field 3 is only modified and the aforementioned two bits are ORRed into the field. This could lead to a residual dirty bits being left in the field 3 from previous transfer, and it generally does. Fully set the field 3 instead to clear those residual dirty bits. Reviewed-by: Patrick Delaunay Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Ramon Fried Cc: Stephen Warren --- drivers/net/dwc_eth_qos.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 63f2086dece..4f245206910 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1288,7 +1288,7 @@ static int eqos_start(struct udevice *dev) struct eqos_desc *rx_desc = &(eqos->rx_descs[i]); rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf + (i * EQOS_MAX_PACKET_SIZE)); - rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; + rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; } eqos->config->ops->eqos_flush_desc(eqos->descs); @@ -1482,7 +1482,7 @@ static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length) * writes to the rest of the descriptor too. */ mb(); - rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; + rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; eqos->config->ops->eqos_flush_desc(rx_desc); writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer); From 83858d87954627af7a576ccc7c93034b055faa7b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 23 Mar 2020 02:03:50 +0100 Subject: [PATCH 066/237] net: dwc_eth_qos: Correctly wrap around TX descriptor tail pointer This code programs the next descriptor in the TX descriptor ring into the hardware as the last valid TX descriptor. The problem is that if the currenty descriptor is the last one in the array, the code will not wrap around correctly and use TX descriptor 0 again, but instead will use TX descriptor at address right past the TX descriptor ring, which is the first descriptor in the RX ring. Fix this by adding the necessary wrap-around. Reviewed-by: Patrick Delaunay Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Ramon Fried Cc: Stephen Warren --- drivers/net/dwc_eth_qos.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 4f245206910..e2fb690a1c2 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1419,7 +1419,8 @@ static int eqos_send(struct udevice *dev, void *packet, int length) tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length; eqos->config->ops->eqos_flush_desc(tx_desc); - writel((ulong)(tx_desc + 1), &eqos->dma_regs->ch0_txdesc_tail_pointer); + writel((ulong)(&(eqos->tx_descs[eqos->tx_desc_idx])), + &eqos->dma_regs->ch0_txdesc_tail_pointer); for (i = 0; i < 1000000; i++) { eqos->config->ops->eqos_inval_desc(tx_desc); From dd90c2e1ea0a7abdfa501e604523c23d6f77ffdd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 23 Mar 2020 02:09:01 +0100 Subject: [PATCH 067/237] net: dwc_eth_qos: Flush the RX descriptors on init Currently the code only flushes the first RX descriptor, not every entry in the RX descriptor ring. Fix this, to make sure the DMA engine can pick the RX descriptors correctly. Reviewed-by: Patrick Delaunay Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Ramon Fried Cc: Stephen Warren --- drivers/net/dwc_eth_qos.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index e2fb690a1c2..e33f3045fea 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1289,8 +1289,8 @@ static int eqos_start(struct udevice *dev) rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf + (i * EQOS_MAX_PACKET_SIZE)); rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; + eqos->config->ops->eqos_flush_desc(rx_desc); } - eqos->config->ops->eqos_flush_desc(eqos->descs); writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress); writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address); From 738ee270fe17ea9e48fee8823eb356ed03656e7c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 23 Mar 2020 02:09:21 +0100 Subject: [PATCH 068/237] net: dwc_eth_qos: Invalidate RX descriptor before reading The current code polls the RX desciptor ring for new packets by reading the RX descriptor status. This works by accident, as the RX descriptors are often in non-cacheable memory. However, the driver does support use of RX descriptors in cacheable memory. This patch adds a missing RX descriptor invalidation, which assures the CPU will read a fresh copy of the RX descriptor instead of a cached one. Reviewed-by: Patrick Delaunay Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Ramon Fried Cc: Stephen Warren --- drivers/net/dwc_eth_qos.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index e33f3045fea..2b37cc3cded 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1443,6 +1443,7 @@ static int eqos_recv(struct udevice *dev, int flags, uchar **packetp) debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags); rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]); + eqos->config->ops->eqos_inval_desc(rx_desc); if (rx_desc->des3 & EQOS_DESC3_OWN) { debug("%s: RX packet not available\n", __func__); return -EAGAIN; From a83ca0c280dd41dda576d6a8f15a8534a84b782c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 23 Mar 2020 02:09:55 +0100 Subject: [PATCH 069/237] net: dwc_eth_qos: Invalidate RX packet DMA buffer This patch prevents an issue where the RX packet might have been accessed by the CPU, which now has cached data from the packet in the caches and possibly various write buffers, and these data may be evicted from the caches into the DRAM while the buffer is also written by the DMA. By invalidating the buffer after the CPU accessed it and before the DMA populates the buffer, it is assured that the buffer will not be corrupted. Reviewed-by: Patrick Delaunay Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Ramon Fried Cc: Stephen Warren --- drivers/net/dwc_eth_qos.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 2b37cc3cded..a195fe5c275 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1476,6 +1476,9 @@ static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length) } rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]); + + eqos->config->ops->eqos_inval_buffer(packet, length); + rx_desc->des0 = (u32)(ulong)packet; rx_desc->des1 = 0; rx_desc->des2 = 0; @@ -1538,6 +1541,9 @@ static int eqos_probe_resources_core(struct udevice *dev) } debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt); + eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf, + EQOS_MAX_PACKET_SIZE * EQOS_DESCRIPTORS_RX); + debug("%s: OK\n", __func__); return 0; From 24891dd8d40d71c034023d2a037c97df1714393b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 23 Mar 2020 02:11:46 +0100 Subject: [PATCH 070/237] net: dwc_eth_qos: Prevent DMA from writing updated RX DMA descriptor The DMA may attempt to write a DMA descriptor in the ring while it is being updated. By writing the DMA descriptor buffer address to 0, it is assured the DMA will not use such a buffer and the buffer can be updated without any interference. Reviewed-by: Patrick Delaunay Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Ramon Fried Cc: Stephen Warren --- drivers/net/dwc_eth_qos.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index a195fe5c275..60dfd17a74d 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1477,8 +1477,10 @@ static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length) rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]); + rx_desc->des0 = 0; + mb(); + eqos->config->ops->eqos_flush_desc(rx_desc); eqos->config->ops->eqos_inval_buffer(packet, length); - rx_desc->des0 = (u32)(ulong)packet; rx_desc->des1 = 0; rx_desc->des2 = 0; From a5e66e515b0e6615d6e6fed91e20361d9a476831 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 12 Apr 2020 20:47:26 +0200 Subject: [PATCH 071/237] net: rtl8139: Register macro cleanup Clean up the horrible register definitions in the RTL8139 driver. This does create a couple of checkpatch errors, but the driver is full of them anyway, and those will be cleaned up later. No functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/rtl8139.c | 263 ++++++++++++++++++++++++------------------ 1 file changed, 152 insertions(+), 111 deletions(-) diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index bb59629f81c..9898f20c391 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -99,77 +99,96 @@ #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) /* Symbolic offsets to registers. */ -enum RTL8139_registers { - MAC0=0, /* Ethernet hardware address. */ - MAR0=8, /* Multicast filter. */ - TxStatus0=0x10, /* Transmit status (four 32bit registers). */ - TxAddr0=0x20, /* Tx descriptors (also four 32bit). */ - RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36, - ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A, - IntrMask=0x3C, IntrStatus=0x3E, - TxConfig=0x40, RxConfig=0x44, - Timer=0x48, /* general-purpose counter. */ - RxMissed=0x4C, /* 24 bits valid, write clears. */ - Cfg9346=0x50, Config0=0x51, Config1=0x52, - TimerIntrReg=0x54, /* intr if gp counter reaches this value */ - MediaStatus=0x58, - Config3=0x59, - MultiIntr=0x5C, - RevisionID=0x5E, /* revision of the RTL8139 chip */ - TxSummary=0x60, - MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68, - NWayExpansion=0x6A, - DisconnectCnt=0x6C, FalseCarrierCnt=0x6E, - NWayTestReg=0x70, - RxCnt=0x72, /* packet received counter */ - CSCR=0x74, /* chip status and configuration register */ - PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80, /* undocumented */ - /* from 0x84 onwards are a number of power management/wakeup frame - * definitions we will probably never need to know about. */ -}; +/* Ethernet hardware address. */ +#define RTL_REG_MAC0 0x00 +/* Multicast filter. */ +#define RTL_REG_MAR0 0x08 +/* Transmit status (four 32bit registers). */ +#define RTL_REG_TXSTATUS0 0x10 +/* Tx descriptors (also four 32bit). */ +#define RTL_REG_TXADDR0 0x20 +#define RTL_REG_RXBUF 0x30 +#define RTL_REG_RXEARLYCNT 0x34 +#define RTL_REG_RXEARLYSTATUS 0x36 +#define RTL_REG_CHIPCMD 0x37 +#define RTL_REG_CHIPCMD_CMDRESET BIT(4) +#define RTL_REG_CHIPCMD_CMDRXENB BIT(3) +#define RTL_REG_CHIPCMD_CMDTXENB BIT(2) +#define RTL_REG_CHIPCMD_RXBUFEMPTY BIT(0) +#define RTL_REG_RXBUFPTR 0x38 +#define RTL_REG_RXBUFADDR 0x3A +#define RTL_REG_INTRMASK 0x3C +#define RTL_REG_INTRSTATUS 0x3E +#define RTL_REG_INTRSTATUS_PCIERR BIT(15) +#define RTL_REG_INTRSTATUS_PCSTIMEOUT BIT(14) +#define RTL_REG_INTRSTATUS_CABLELENCHANGE BIT(13) +#define RTL_REG_INTRSTATUS_RXFIFOOVER BIT(6) +#define RTL_REG_INTRSTATUS_RXUNDERRUN BIT(5) +#define RTL_REG_INTRSTATUS_RXOVERFLOW BIT(4) +#define RTL_REG_INTRSTATUS_TXERR BIT(3) +#define RTL_REG_INTRSTATUS_TXOK BIT(2) +#define RTL_REG_INTRSTATUS_RXERR BIT(1) +#define RTL_REG_INTRSTATUS_RXOK BIT(0) +#define RTL_REG_TXCONFIG 0x40 +#define RTL_REG_RXCONFIG 0x44 +#define RTL_REG_RXCONFIG_RXCFGWRAP BIT(7) +#define RTL_REG_RXCONFIG_ACCEPTERR BIT(5) +#define RTL_REG_RXCONFIG_ACCEPTRUNT BIT(4) +#define RTL_REG_RXCONFIG_ACCEPTBROADCAST BIT(3) +#define RTL_REG_RXCONFIG_ACCEPTMULTICAST BIT(2) +#define RTL_REG_RXCONFIG_ACCEPTMYPHYS BIT(1) +#define RTL_REG_RXCONFIG_ACCEPTALLPHYS BIT(0) +/* general-purpose counter. */ +#define RTL_REG_TIMER 0x48 +/* 24 bits valid, write clears. */ +#define RTL_REG_RXMISSED 0x4C +#define RTL_REG_CFG9346 0x50 +#define RTL_REG_CONFIG0 0x51 +#define RTL_REG_CONFIG1 0x52 +/* intr if gp counter reaches this value */ +#define RTL_REG_TIMERINTRREG 0x54 +#define RTL_REG_MEDIASTATUS 0x58 +#define RTL_REG_MEDIASTATUS_MSRTXFLOWENABLE BIT(7) +#define RTL_REG_MEDIASTATUS_MSRRXFLOWENABLE BIT(6) +#define RTL_REG_MEDIASTATUS_MSRSPEED10 BIT(3) +#define RTL_REG_MEDIASTATUS_MSRLINKFAIL BIT(2) +#define RTL_REG_MEDIASTATUS_MSRRXPAUSEFLAG BIT(1) +#define RTL_REG_MEDIASTATUS_MSRTXPAUSEFLAG BIT(0) +#define RTL_REG_CONFIG3 0x59 +#define RTL_REG_MULTIINTR 0x5C +/* revision of the RTL8139 chip */ +#define RTL_REG_REVISIONID 0x5E +#define RTL_REG_TXSUMMARY 0x60 +#define RTL_REG_MII_BMCR 0x62 +#define RTL_REG_MII_BMSR 0x64 +#define RTL_REG_NWAYADVERT 0x66 +#define RTL_REG_NWAYLPAR 0x68 +#define RTL_REG_NWAYEXPANSION 0x6A +#define RTL_REG_DISCONNECTCNT 0x6C +#define RTL_REG_FALSECARRIERCNT 0x6E +#define RTL_REG_NWAYTESTREG 0x70 +/* packet received counter */ +#define RTL_REG_RXCNT 0x72 +/* chip status and configuration register */ +#define RTL_REG_CSCR 0x74 +#define RTL_REG_PHYPARM1 0x78 +#define RTL_REG_TWISTERPARM 0x7c +/* undocumented */ +#define RTL_REG_PHYPARM2 0x80 +/* + * from 0x84 onwards are a number of power management/wakeup frame + * definitions we will probably never need to know about. + */ -enum ChipCmdBits { - CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, }; - -/* Interrupt register bits, using my own meaningful names. */ -enum IntrStatusBits { - PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000, - RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10, - TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01, -}; -enum TxStatusBits { - TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000, - TxOutOfWindow=0x20000000, TxAborted=0x40000000, - TxCarrierLost=0x80000000, -}; -enum RxStatusBits { - RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000, - RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004, - RxBadAlign=0x0002, RxStatusOK=0x0001, -}; - -enum MediaStatusBits { - MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08, - MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01, -}; - -enum MIIBMCRBits { - BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000, - BMCRRestartNWay=0x0200, BMCRDuplex=0x0100, -}; - -enum CSCRBits { - CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800, - CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0, - CSCR_LinkDownCmd=0x0f3c0, -}; - -/* Bits in RxConfig. */ -enum rx_mode_bits { - RxCfgWrap=0x80, - AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08, - AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01, -}; +#define RTL_STS_RXMULTICAST BIT(15) +#define RTL_STS_RXPHYSICAL BIT(14) +#define RTL_STS_RXBROADCAST BIT(13) +#define RTL_STS_RXBADSYMBOL BIT(5) +#define RTL_STS_RXRUNT BIT(4) +#define RTL_STS_RXTOOLONG BIT(3) +#define RTL_STS_RXCRCERR BIT(2) +#define RTL_STS_RXBADALIGN BIT(1) +#define RTL_STS_RXSTATUSOK BIT(0) static int ioaddr; static unsigned int cur_rx,cur_tx; @@ -251,7 +270,7 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis) ioaddr = dev->iobase; /* Bring the chip out of low-power mode. */ - outb(0x00, ioaddr + Config1); + outb(0x00, ioaddr + RTL_REG_CONFIG1); addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6; for (i = 0; i < 3; i++) @@ -259,7 +278,7 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis) rtl_reset(dev); - if (inb(ioaddr + MediaStatus) & MSRLinkFail) { + if (inb(ioaddr + RTL_REG_MEDIASTATUS) & RTL_REG_MEDIASTATUS_MSRLINKFAIL) { printf("Cable not connected or other link failure\n"); return -1 ; } @@ -286,15 +305,15 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis) #define eeprom_delay() inl(ee_addr) /* The EEPROM commands include the alway-set leading bit. */ -#define EE_WRITE_CMD (5) -#define EE_READ_CMD (6) -#define EE_ERASE_CMD (7) +#define EE_WRITE_CMD 5 +#define EE_READ_CMD 6 +#define EE_ERASE_CMD 7 static int read_eeprom(int location, int addr_len) { int i; unsigned int retval = 0; - long ee_addr = ioaddr + Cfg9346; + long ee_addr = ioaddr + RTL_REG_CFG9346; int read_cmd = location | (EE_READ_CMD << addr_len); outb(EE_ENB & ~EE_CS, ee_addr); @@ -335,41 +354,46 @@ static void set_rx_mode(struct eth_device *dev) { unsigned int mc_filter[2]; int rx_mode; /* !IFF_PROMISC */ - rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; + rx_mode = RTL_REG_RXCONFIG_ACCEPTBROADCAST | + RTL_REG_RXCONFIG_ACCEPTMULTICAST | + RTL_REG_RXCONFIG_ACCEPTMYPHYS; mc_filter[1] = mc_filter[0] = 0xffffffff; - outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig); + outl(rtl8139_rx_config | rx_mode, ioaddr + RTL_REG_RXCONFIG); - outl(mc_filter[0], ioaddr + MAR0 + 0); - outl(mc_filter[1], ioaddr + MAR0 + 4); + outl(mc_filter[0], ioaddr + RTL_REG_MAR0 + 0); + outl(mc_filter[1], ioaddr + RTL_REG_MAR0 + 4); } static void rtl_reset(struct eth_device *dev) { int i; - outb(CmdReset, ioaddr + ChipCmd); + outb(RTL_REG_CHIPCMD_CMDRESET, ioaddr + RTL_REG_CHIPCMD); cur_rx = 0; cur_tx = 0; /* Give the chip 10ms to finish the reset. */ for (i=0; i<100; ++i){ - if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break; + if ((inb(ioaddr + RTL_REG_CHIPCMD) & + RTL_REG_CHIPCMD_CMDRESET) == 0) + break; udelay (100); /* wait 100us */ } for (i = 0; i < ETH_ALEN; i++) - outb(dev->enetaddr[i], ioaddr + MAC0 + i); + outb(dev->enetaddr[i], ioaddr + RTL_REG_MAC0 + i); /* Must enable Tx/Rx before setting transfer thresholds! */ - outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd); + outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB, + ioaddr + RTL_REG_CHIPCMD); outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8), - ioaddr + RxConfig); /* accept no frames yet! */ - outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig); + ioaddr + RTL_REG_RXCONFIG); /* accept no frames yet! */ + outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + RTL_REG_TXCONFIG); - /* The Linux driver changes Config1 here to use a different LED pattern + /* The Linux driver changes RTL_REG_CONFIG1 here to use a different LED pattern * for half duplex or full/autodetect duplex (for full/autodetect, the * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses * TX/RX, Link100, Link10). This is messy, because it doesn't match @@ -380,24 +404,25 @@ static void rtl_reset(struct eth_device *dev) debug_cond(DEBUG_RX, "rx ring address is %lX\n",(unsigned long)rx_ring); flush_cache((unsigned long)rx_ring, RX_BUF_LEN); - outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf); + outl(phys_to_bus((int)rx_ring), ioaddr + RTL_REG_RXBUF); - /* If we add multicast support, the MAR0 register would have to be + /* If we add multicast support, the RTL_REG_MAR0 register would have to be * initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */ - outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd); + outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB, + ioaddr + RTL_REG_CHIPCMD); - outl(rtl8139_rx_config, ioaddr + RxConfig); + outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG); /* Start the chip's Tx and Rx process. */ - outl(0, ioaddr + RxMissed); + outl(0, ioaddr + RTL_REG_RXMISSED); /* set_rx_mode */ set_rx_mode(dev); /* Disable all known interrupts by setting the interrupt mask. */ - outw(0, ioaddr + IntrMask); + outw(0, ioaddr + RTL_REG_INTRMASK); } static int rtl_transmit(struct eth_device *dev, void *packet, int length) @@ -420,23 +445,32 @@ static int rtl_transmit(struct eth_device *dev, void *packet, int length) } flush_cache((unsigned long)tx_buffer, length); - outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4); + outl(phys_to_bus((int)tx_buffer), ioaddr + RTL_REG_TXADDR0 + cur_tx*4); outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len, - ioaddr + TxStatus0 + cur_tx*4); + ioaddr + RTL_REG_TXSTATUS0 + cur_tx*4); do { - status = inw(ioaddr + IntrStatus); - /* Only acknlowledge interrupt sources we can properly handle - * here - the RxOverflow/RxFIFOOver MUST be handled in the - * rtl_poll() function. */ - outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus); - if ((status & (TxOK | TxErr | PCIErr)) != 0) break; + status = inw(ioaddr + RTL_REG_INTRSTATUS); + /* + * Only acknlowledge interrupt sources we can properly + * handle here - the RTL_REG_INTRSTATUS_RXOVERFLOW/ + * RTL_REG_INTRSTATUS_RXFIFOOVER MUST be handled in the + * rtl_poll() function. + */ + outw(status & (RTL_REG_INTRSTATUS_TXOK | + RTL_REG_INTRSTATUS_TXERR | + RTL_REG_INTRSTATUS_PCIERR), + ioaddr + RTL_REG_INTRSTATUS); + if ((status & (RTL_REG_INTRSTATUS_TXOK | + RTL_REG_INTRSTATUS_TXERR | + RTL_REG_INTRSTATUS_PCIERR)) != 0) + break; udelay(10); } while (i++ < RTL_TIMEOUT); - txstatus = inl(ioaddr + TxStatus0 + cur_tx*4); + txstatus = inl(ioaddr + RTL_REG_TXSTATUS0 + cur_tx*4); - if (status & TxOK) { + if (status & RTL_REG_INTRSTATUS_TXOK) { cur_tx = (cur_tx + 1) % NUM_TX_DESC; debug_cond(DEBUG_TX, @@ -465,13 +499,16 @@ static int rtl_poll(struct eth_device *dev) ioaddr = dev->iobase; - if (inb(ioaddr + ChipCmd) & RxBufEmpty) { + if (inb(ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY) { return 0; } - status = inw(ioaddr + IntrStatus); + status = inw(ioaddr + RTL_REG_INTRSTATUS); /* See below for the rest of the interrupt acknowledges. */ - outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus); + outw(status & ~(RTL_REG_INTRSTATUS_RXFIFOOVER | + RTL_REG_INTRSTATUS_RXOVERFLOW | + RTL_REG_INTRSTATUS_RXOK), + ioaddr + RTL_REG_INTRSTATUS); debug_cond(DEBUG_RX, "rtl_poll: int %hX ", status); @@ -481,7 +518,9 @@ static int rtl_poll(struct eth_device *dev) rx_size = rx_status >> 16; rx_status &= 0xffff; - if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) || + if ((rx_status & (RTL_STS_RXBADSYMBOL | RTL_STS_RXRUNT | + RTL_STS_RXTOOLONG | RTL_STS_RXCRCERR | + RTL_STS_RXBADALIGN)) || (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) { printf("rx error %hX\n", rx_status); rtl_reset(dev); /* this clears all interrupts still pending */ @@ -507,11 +546,13 @@ static int rtl_poll(struct eth_device *dev) flush_cache((unsigned long)rx_ring, RX_BUF_LEN); cur_rx = (cur_rx + rx_size + 4 + 3) & ~3; - outw(cur_rx - 16, ioaddr + RxBufPtr); + outw(cur_rx - 16, ioaddr + RTL_REG_RXBUFPTR); /* See RTL8139 Programming Guide V0.1 for the official handling of * Rx overflow situations. The document itself contains basically no * usable information, except for a few exception handling rules. */ - outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus); + outw(status & (RTL_REG_INTRSTATUS_RXFIFOOVER | + RTL_REG_INTRSTATUS_RXOVERFLOW | + RTL_REG_INTRSTATUS_RXOK), ioaddr + RTL_REG_INTRSTATUS); return length; } @@ -522,11 +563,11 @@ static void rtl_disable(struct eth_device *dev) ioaddr = dev->iobase; /* reset the chip */ - outb(CmdReset, ioaddr + ChipCmd); + outb(RTL_REG_CHIPCMD_CMDRESET, ioaddr + RTL_REG_CHIPCMD); /* Give the chip 10ms to finish the reset. */ for (i=0; i<100; ++i){ - if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break; + if ((inb(ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_CMDRESET) == 0) break; udelay (100); /* wait 100us */ } } From f80f4e4d729252eb6124e1afb5dde9f74c35c994 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 12 Apr 2020 21:20:31 +0200 Subject: [PATCH 072/237] net: rtl8139: Rework eeprom_delay() macro The macro assumes ee_addr variable to be present when it's being used. Rework the macro into a function instead and pass it an argument specifying the register base address, to make it future proof for DM conversion. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/rtl8139.c | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index 9898f20c391..ff014ade88b 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -73,6 +73,7 @@ #include #include +#include #include #include #include @@ -297,18 +298,20 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis) #define EE_DATA_READ 0x01 /* EEPROM chip data out. */ #define EE_ENB (0x80 | EE_CS) -/* - Delay between EEPROM clock transitions. - No extra delay is needed with 33MHz PCI, but 66MHz may change this. -*/ - -#define eeprom_delay() inl(ee_addr) - /* The EEPROM commands include the alway-set leading bit. */ #define EE_WRITE_CMD 5 #define EE_READ_CMD 6 #define EE_ERASE_CMD 7 +static void rtl8139_eeprom_delay(uintptr_t regbase) +{ + /* + * Delay between EEPROM clock transitions. + * No extra delay is needed with 33MHz PCI, but 66MHz may change this. + */ + inl(regbase + RTL_REG_CFG9346); +} + static int read_eeprom(int location, int addr_len) { int i; @@ -318,30 +321,30 @@ static int read_eeprom(int location, int addr_len) outb(EE_ENB & ~EE_CS, ee_addr); outb(EE_ENB, ee_addr); - eeprom_delay(); + rtl8139_eeprom_delay(ioaddr); /* Shift the read command bits out. */ for (i = 4 + addr_len; i >= 0; i--) { int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; outb(EE_ENB | dataval, ee_addr); - eeprom_delay(); + rtl8139_eeprom_delay(ioaddr); outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); - eeprom_delay(); + rtl8139_eeprom_delay(ioaddr); } outb(EE_ENB, ee_addr); - eeprom_delay(); + rtl8139_eeprom_delay(ioaddr); for (i = 16; i > 0; i--) { outb(EE_ENB | EE_SHIFT_CLK, ee_addr); - eeprom_delay(); + rtl8139_eeprom_delay(ioaddr); retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0); outb(EE_ENB, ee_addr); - eeprom_delay(); + rtl8139_eeprom_delay(ioaddr); } /* Terminate the EEPROM access. */ outb(~EE_CS, ee_addr); - eeprom_delay(); + rtl8139_eeprom_delay(ioaddr); return retval; } From 17dc95e5277cdbad1281b6b5605b1eef74729463 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 12 Apr 2020 21:28:30 +0200 Subject: [PATCH 073/237] net: rtl8139: Minor cleanup of read_eeprom() Rename the function to rtl8139_read_eeprom() to keep the naming consistent, keep the variables sorted in reverse xmas tree. No functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/rtl8139.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index ff014ade88b..90e9f1272c3 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -199,7 +199,7 @@ static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4))); static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4))); static int rtl8139_probe(struct eth_device *dev, bd_t *bis); -static int read_eeprom(int location, int addr_len); +static int rtl8139_read_eeprom(unsigned int location, unsigned int addr_len); static void rtl_reset(struct eth_device *dev); static int rtl_transmit(struct eth_device *dev, void *packet, int length); static int rtl_poll(struct eth_device *dev); @@ -273,9 +273,9 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis) /* Bring the chip out of low-power mode. */ outb(0x00, ioaddr + RTL_REG_CONFIG1); - addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6; + addr_len = rtl8139_read_eeprom(0,8) == 0x8129 ? 8 : 6; for (i = 0; i < 3; i++) - *ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len)); + *ap++ = le16_to_cpu (rtl8139_read_eeprom(i + 7, addr_len)); rtl_reset(dev); @@ -312,12 +312,13 @@ static void rtl8139_eeprom_delay(uintptr_t regbase) inl(regbase + RTL_REG_CFG9346); } -static int read_eeprom(int location, int addr_len) +static int rtl8139_read_eeprom(unsigned int location, unsigned int addr_len) { - int i; + unsigned int read_cmd = location | (EE_READ_CMD << addr_len); + uintptr_t ee_addr = ioaddr + RTL_REG_CFG9346; unsigned int retval = 0; - long ee_addr = ioaddr + RTL_REG_CFG9346; - int read_cmd = location | (EE_READ_CMD << addr_len); + u8 dataval; + int i; outb(EE_ENB & ~EE_CS, ee_addr); outb(EE_ENB, ee_addr); @@ -325,19 +326,21 @@ static int read_eeprom(int location, int addr_len) /* Shift the read command bits out. */ for (i = 4 + addr_len; i >= 0; i--) { - int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + dataval = (read_cmd & BIT(i)) ? EE_DATA_WRITE : 0; outb(EE_ENB | dataval, ee_addr); rtl8139_eeprom_delay(ioaddr); outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); rtl8139_eeprom_delay(ioaddr); } + outb(EE_ENB, ee_addr); rtl8139_eeprom_delay(ioaddr); for (i = 16; i > 0; i--) { outb(EE_ENB | EE_SHIFT_CLK, ee_addr); rtl8139_eeprom_delay(ioaddr); - retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0); + retval <<= 1; + retval |= inb(ee_addr) & EE_DATA_READ; outb(EE_ENB, ee_addr); rtl8139_eeprom_delay(ioaddr); } @@ -345,6 +348,7 @@ static int read_eeprom(int location, int addr_len) /* Terminate the EEPROM access. */ outb(~EE_CS, ee_addr); rtl8139_eeprom_delay(ioaddr); + return retval; } From 198e6b571b58de54803a92743970c8f5dea77782 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 12 Apr 2020 21:30:38 +0200 Subject: [PATCH 074/237] net: rtl8139: Consistently use rtl8139_rx_config This string of macros is exactly the same thing as rtl8139_rx_config, so just use rtl8139_rx_config. No functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/rtl8139.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index 90e9f1272c3..7a2829a1633 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -396,8 +396,8 @@ static void rtl_reset(struct eth_device *dev) /* Must enable Tx/Rx before setting transfer thresholds! */ outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB, ioaddr + RTL_REG_CHIPCMD); - outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8), - ioaddr + RTL_REG_RXCONFIG); /* accept no frames yet! */ + /* accept no frames yet! */ + outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG); outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + RTL_REG_TXCONFIG); /* The Linux driver changes RTL_REG_CONFIG1 here to use a different LED pattern From 89f3facffb8b35f45d405716dce63f6bc944a082 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 12 Apr 2020 21:35:12 +0200 Subject: [PATCH 075/237] net: rtl8139: Minor cleanup of set_rx_mode() Rename the function to rtl8139_set_rx_mode(), use unsigned variables where applicable and inline mc_filter[] values. No functional chanage. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/rtl8139.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index 7a2829a1633..4dfb709fa9a 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -357,19 +357,17 @@ static const unsigned int rtl8139_rx_config = (RX_FIFO_THRESH << 13) | (RX_DMA_BURST << 8); -static void set_rx_mode(struct eth_device *dev) { - unsigned int mc_filter[2]; - int rx_mode; +static void rtl8139_set_rx_mode(struct eth_device *dev) +{ /* !IFF_PROMISC */ - rx_mode = RTL_REG_RXCONFIG_ACCEPTBROADCAST | - RTL_REG_RXCONFIG_ACCEPTMULTICAST | - RTL_REG_RXCONFIG_ACCEPTMYPHYS; - mc_filter[1] = mc_filter[0] = 0xffffffff; + unsigned int rx_mode = RTL_REG_RXCONFIG_ACCEPTBROADCAST | + RTL_REG_RXCONFIG_ACCEPTMULTICAST | + RTL_REG_RXCONFIG_ACCEPTMYPHYS; outl(rtl8139_rx_config | rx_mode, ioaddr + RTL_REG_RXCONFIG); - outl(mc_filter[0], ioaddr + RTL_REG_MAR0 + 0); - outl(mc_filter[1], ioaddr + RTL_REG_MAR0 + 4); + outl(0xffffffff, ioaddr + RTL_REG_MAR0 + 0); + outl(0xffffffff, ioaddr + RTL_REG_MAR0 + 4); } static void rtl_reset(struct eth_device *dev) @@ -425,8 +423,7 @@ static void rtl_reset(struct eth_device *dev) /* Start the chip's Tx and Rx process. */ outl(0, ioaddr + RTL_REG_RXMISSED); - /* set_rx_mode */ - set_rx_mode(dev); + rtl8139_set_rx_mode(dev); /* Disable all known interrupts by setting the interrupt mask. */ outw(0, ioaddr + RTL_REG_INTRMASK); From c7a3e35d768ddc6b6d3a9a0e061bba0741deaa52 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 12 Apr 2020 21:41:56 +0200 Subject: [PATCH 076/237] net: rtl8139: Minor cleanup of rtl_reset() Rename the function to rtl8139_reset(), clean up the reset polling and various line-over-80 problems. No functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/rtl8139.c | 57 ++++++++++++++++++++++++------------------- 1 file changed, 32 insertions(+), 25 deletions(-) diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index 4dfb709fa9a..d9d8aae7a94 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -200,7 +200,7 @@ static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4))); static int rtl8139_probe(struct eth_device *dev, bd_t *bis); static int rtl8139_read_eeprom(unsigned int location, unsigned int addr_len); -static void rtl_reset(struct eth_device *dev); +static void rtl8139_reset(struct eth_device *dev); static int rtl_transmit(struct eth_device *dev, void *packet, int length); static int rtl_poll(struct eth_device *dev); static void rtl_disable(struct eth_device *dev); @@ -277,7 +277,7 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis) for (i = 0; i < 3; i++) *ap++ = le16_to_cpu (rtl8139_read_eeprom(i + 7, addr_len)); - rtl_reset(dev); + rtl8139_reset(dev); if (inb(ioaddr + RTL_REG_MEDIASTATUS) & RTL_REG_MEDIASTATUS_MSRLINKFAIL) { printf("Cable not connected or other link failure\n"); @@ -370,8 +370,9 @@ static void rtl8139_set_rx_mode(struct eth_device *dev) outl(0xffffffff, ioaddr + RTL_REG_MAR0 + 4); } -static void rtl_reset(struct eth_device *dev) +static void rtl8139_reset(struct eth_device *dev) { + u8 reg; int i; outb(RTL_REG_CHIPCMD_CMDRESET, ioaddr + RTL_REG_CHIPCMD); @@ -380,11 +381,12 @@ static void rtl_reset(struct eth_device *dev) cur_tx = 0; /* Give the chip 10ms to finish the reset. */ - for (i=0; i<100; ++i){ - if ((inb(ioaddr + RTL_REG_CHIPCMD) & - RTL_REG_CHIPCMD_CMDRESET) == 0) + for (i = 0; i < 100; i++) { + reg = inb(ioaddr + RTL_REG_CHIPCMD); + if (!(reg & RTL_REG_CHIPCMD_CMDRESET)) break; - udelay (100); /* wait 100us */ + + udelay(100); } @@ -393,30 +395,35 @@ static void rtl_reset(struct eth_device *dev) /* Must enable Tx/Rx before setting transfer thresholds! */ outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB, - ioaddr + RTL_REG_CHIPCMD); + ioaddr + RTL_REG_CHIPCMD); + /* accept no frames yet! */ outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG); - outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + RTL_REG_TXCONFIG); + outl((TX_DMA_BURST << 8) | 0x03000000, ioaddr + RTL_REG_TXCONFIG); - /* The Linux driver changes RTL_REG_CONFIG1 here to use a different LED pattern - * for half duplex or full/autodetect duplex (for full/autodetect, the - * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses - * TX/RX, Link100, Link10). This is messy, because it doesn't match - * the inscription on the mounting bracket. It should not be changed - * from the configuration EEPROM default, because the card manufacturer - * should have set that to match the card. */ + /* + * The Linux driver changes RTL_REG_CONFIG1 here to use a different + * LED pattern for half duplex or full/autodetect duplex (for + * full/autodetect, the outputs are TX/RX, Link10/100, FULL, while + * for half duplex it uses TX/RX, Link100, Link10). This is messy, + * because it doesn't match the inscription on the mounting bracket. + * It should not be changed from the configuration EEPROM default, + * because the card manufacturer should have set that to match the + * card. + */ + debug_cond(DEBUG_RX, "rx ring address is %p\n", rx_ring); - debug_cond(DEBUG_RX, - "rx ring address is %lX\n",(unsigned long)rx_ring); flush_cache((unsigned long)rx_ring, RX_BUF_LEN); outl(phys_to_bus((int)rx_ring), ioaddr + RTL_REG_RXBUF); - /* If we add multicast support, the RTL_REG_MAR0 register would have to be - * initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot - * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */ - + /* + * If we add multicast support, the RTL_REG_MAR0 register would have + * to be initialized to 0xffffffffffffffff (two 32 bit accesses). + * Etherboot only needs broadcast (for ARP/RARP/BOOTP/DHCP) and + * unicast. + */ outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB, - ioaddr + RTL_REG_CHIPCMD); + ioaddr + RTL_REG_CHIPCMD); outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG); @@ -488,7 +495,7 @@ static int rtl_transmit(struct eth_device *dev, void *packet, int length) "tx timeout/error (%d usecs), status %hX txstatus %lX\n", 10*i, status, txstatus); - rtl_reset(dev); + rtl8139_reset(dev); return 0; } @@ -527,7 +534,7 @@ static int rtl_poll(struct eth_device *dev) RTL_STS_RXBADALIGN)) || (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) { printf("rx error %hX\n", rx_status); - rtl_reset(dev); /* this clears all interrupts still pending */ + rtl8139_reset(dev); /* this clears all interrupts still pending */ return 0; } From 67fdbc06be27728e41aa9682d6aaf5618d959765 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 12 Apr 2020 22:40:45 +0200 Subject: [PATCH 077/237] net: rtl8139: Minor cleanup of rtl_transmit() Rename the function to rtl8139_send(), clean up the TX polling, the TX OK condition at the end, overuse of typecasts, and various line-over-80 problems. No functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/rtl8139.c | 64 +++++++++++++++++++++---------------------- 1 file changed, 31 insertions(+), 33 deletions(-) diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index d9d8aae7a94..cb1166ead2d 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -201,7 +201,7 @@ static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4))); static int rtl8139_probe(struct eth_device *dev, bd_t *bis); static int rtl8139_read_eeprom(unsigned int location, unsigned int addr_len); static void rtl8139_reset(struct eth_device *dev); -static int rtl_transmit(struct eth_device *dev, void *packet, int length); +static int rtl8139_send(struct eth_device *dev, void *packet, int length); static int rtl_poll(struct eth_device *dev); static void rtl_disable(struct eth_device *dev); static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, int join) @@ -246,7 +246,7 @@ int rtl8139_initialize(bd_t *bis) dev->iobase = (int)bus_to_phys(iobase); dev->init = rtl8139_probe; dev->halt = rtl_disable; - dev->send = rtl_transmit; + dev->send = rtl8139_send; dev->recv = rtl_poll; dev->mcast = rtl_bcast_addr; @@ -436,29 +436,31 @@ static void rtl8139_reset(struct eth_device *dev) outw(0, ioaddr + RTL_REG_INTRMASK); } -static int rtl_transmit(struct eth_device *dev, void *packet, int length) +static int rtl8139_send(struct eth_device *dev, void *packet, int length) { - unsigned int status; - unsigned long txstatus; unsigned int len = length; + unsigned long txstatus; + unsigned int status; int i = 0; ioaddr = dev->iobase; - memcpy((char *)tx_buffer, (char *)packet, (int)length); + memcpy(tx_buffer, packet, length); debug_cond(DEBUG_TX, "sending %d bytes\n", len); - /* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4 - * bytes are sent automatically for the FCS, totalling to 64 bytes). */ - while (len < ETH_ZLEN) { + /* + * Note: RTL8139 doesn't auto-pad, send minimum payload (another 4 + * bytes are sent automatically for the FCS, totalling to 64 bytes). + */ + while (len < ETH_ZLEN) tx_buffer[len++] = '\0'; - } flush_cache((unsigned long)tx_buffer, length); - outl(phys_to_bus((int)tx_buffer), ioaddr + RTL_REG_TXADDR0 + cur_tx*4); - outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len, - ioaddr + RTL_REG_TXSTATUS0 + cur_tx*4); + outl(phys_to_bus((unsigned long)tx_buffer), + ioaddr + RTL_REG_TXADDR0 + cur_tx * 4); + outl(((TX_FIFO_THRESH << 11) & 0x003f0000) | len, + ioaddr + RTL_REG_TXSTATUS0 + cur_tx * 4); do { status = inw(ioaddr + RTL_REG_INTRSTATUS); @@ -468,37 +470,33 @@ static int rtl_transmit(struct eth_device *dev, void *packet, int length) * RTL_REG_INTRSTATUS_RXFIFOOVER MUST be handled in the * rtl_poll() function. */ - outw(status & (RTL_REG_INTRSTATUS_TXOK | - RTL_REG_INTRSTATUS_TXERR | - RTL_REG_INTRSTATUS_PCIERR), - ioaddr + RTL_REG_INTRSTATUS); - if ((status & (RTL_REG_INTRSTATUS_TXOK | - RTL_REG_INTRSTATUS_TXERR | - RTL_REG_INTRSTATUS_PCIERR)) != 0) + status &= RTL_REG_INTRSTATUS_TXOK | RTL_REG_INTRSTATUS_TXERR | + RTL_REG_INTRSTATUS_PCIERR; + outw(status, ioaddr + RTL_REG_INTRSTATUS); + if (status) break; + udelay(10); } while (i++ < RTL_TIMEOUT); - txstatus = inl(ioaddr + RTL_REG_TXSTATUS0 + cur_tx*4); - - if (status & RTL_REG_INTRSTATUS_TXOK) { - cur_tx = (cur_tx + 1) % NUM_TX_DESC; + txstatus = inl(ioaddr + RTL_REG_TXSTATUS0 + cur_tx * 4); + if (!(status & RTL_REG_INTRSTATUS_TXOK)) { debug_cond(DEBUG_TX, - "tx done, status %hX txstatus %lX\n", - status, txstatus); - - return length; - } else { - - debug_cond(DEBUG_TX, - "tx timeout/error (%d usecs), status %hX txstatus %lX\n", - 10*i, status, txstatus); + "tx timeout/error (%d usecs), status %hX txstatus %lX\n", + 10 * i, status, txstatus); rtl8139_reset(dev); return 0; } + + cur_tx = (cur_tx + 1) % NUM_TX_DESC; + + debug_cond(DEBUG_TX, "tx done, status %hX txstatus %lX\n", + status, txstatus); + + return length; } static int rtl_poll(struct eth_device *dev) From 468fd955626b650ebb7975d061d415682c91f041 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 12 Apr 2020 22:43:16 +0200 Subject: [PATCH 078/237] net: rtl8139: Minor cleanup of rtl_poll() Rename the function to rtl8139_recv(), clean up various checkpatch errors, line-over-80 conditions, and malformed comments. No functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/rtl8139.c | 63 ++++++++++++++++++++++--------------------- 1 file changed, 33 insertions(+), 30 deletions(-) diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index cb1166ead2d..d942ccf6273 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -44,7 +44,7 @@ which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My interpretation of this "reserved" is that Etherboot may do whatever it likes, as long as its environment is kept intact (like the BIOS - variables). Hopefully fixed rtl_poll() once and for all. The symptoms + variables). Hopefully fixed rtl8139_recv() once and for all. The symptoms were that if Etherboot was left at the boot menu for several minutes, the first eth_poll failed. Seems like I am the only person who does this. First of all I fixed the debugging code and then set out for a long bug @@ -65,7 +65,7 @@ corruption because of exceeding 32K during runtime. 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de) - rtl_poll was quite broken: it used the RxOK interrupt flag instead + rtl8139_recv was quite broken: it used the RxOK interrupt flag instead of the RxBufferEmpty flag which often resulted in very bad transmission performace - below 1kBytes/s. @@ -202,7 +202,7 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis); static int rtl8139_read_eeprom(unsigned int location, unsigned int addr_len); static void rtl8139_reset(struct eth_device *dev); static int rtl8139_send(struct eth_device *dev, void *packet, int length); -static int rtl_poll(struct eth_device *dev); +static int rtl8139_recv(struct eth_device *dev); static void rtl_disable(struct eth_device *dev); static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, int join) { @@ -247,7 +247,7 @@ int rtl8139_initialize(bd_t *bis) dev->init = rtl8139_probe; dev->halt = rtl_disable; dev->send = rtl8139_send; - dev->recv = rtl_poll; + dev->recv = rtl8139_recv; dev->mcast = rtl_bcast_addr; eth_register (dev); @@ -468,7 +468,7 @@ static int rtl8139_send(struct eth_device *dev, void *packet, int length) * Only acknlowledge interrupt sources we can properly * handle here - the RTL_REG_INTRSTATUS_RXOVERFLOW/ * RTL_REG_INTRSTATUS_RXFIFOOVER MUST be handled in the - * rtl_poll() function. + * rtl8139_recv() function. */ status &= RTL_REG_INTRSTATUS_TXOK | RTL_REG_INTRSTATUS_TXERR | RTL_REG_INTRSTATUS_PCIERR; @@ -499,27 +499,26 @@ static int rtl8139_send(struct eth_device *dev, void *packet, int length) return length; } -static int rtl_poll(struct eth_device *dev) +static int rtl8139_recv(struct eth_device *dev) { - unsigned int status; - unsigned int ring_offs; + const unsigned int rxstat = RTL_REG_INTRSTATUS_RXFIFOOVER | + RTL_REG_INTRSTATUS_RXOVERFLOW | + RTL_REG_INTRSTATUS_RXOK; unsigned int rx_size, rx_status; - int length=0; + unsigned int ring_offs; + unsigned int status; + int length = 0; ioaddr = dev->iobase; - if (inb(ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY) { + if (inb(ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY) return 0; - } status = inw(ioaddr + RTL_REG_INTRSTATUS); /* See below for the rest of the interrupt acknowledges. */ - outw(status & ~(RTL_REG_INTRSTATUS_RXFIFOOVER | - RTL_REG_INTRSTATUS_RXOVERFLOW | - RTL_REG_INTRSTATUS_RXOK), - ioaddr + RTL_REG_INTRSTATUS); + outw(status & ~rxstat, ioaddr + RTL_REG_INTRSTATUS); - debug_cond(DEBUG_RX, "rtl_poll: int %hX ", status); + debug_cond(DEBUG_RX, "%s: int %hX ", __func__, status); ring_offs = cur_rx % RX_BUF_LEN; /* ring_offs is guaranteed being 4-byte aligned */ @@ -530,38 +529,42 @@ static int rtl_poll(struct eth_device *dev) if ((rx_status & (RTL_STS_RXBADSYMBOL | RTL_STS_RXRUNT | RTL_STS_RXTOOLONG | RTL_STS_RXCRCERR | RTL_STS_RXBADALIGN)) || - (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) { + (rx_size < ETH_ZLEN) || + (rx_size > ETH_FRAME_LEN + 4)) { printf("rx error %hX\n", rx_status); - rtl8139_reset(dev); /* this clears all interrupts still pending */ + /* this clears all interrupts still pending */ + rtl8139_reset(dev); return 0; } /* Received a good packet */ length = rx_size - 4; /* no one cares about the FCS */ - if (ring_offs+4+rx_size-4 > RX_BUF_LEN) { - int semi_count = RX_BUF_LEN - ring_offs - 4; + if (ring_offs + 4 + rx_size - 4 > RX_BUF_LEN) { unsigned char rxdata[RX_BUF_LEN]; + int semi_count = RX_BUF_LEN - ring_offs - 4; memcpy(rxdata, rx_ring + ring_offs + 4, semi_count); - memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count); + memcpy(&rxdata[semi_count], rx_ring, + rx_size - 4 - semi_count); net_process_received_packet(rxdata, length); debug_cond(DEBUG_RX, "rx packet %d+%d bytes", - semi_count, rx_size-4-semi_count); + semi_count, rx_size - 4 - semi_count); } else { net_process_received_packet(rx_ring + ring_offs + 4, length); - debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size-4); + debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size - 4); } flush_cache((unsigned long)rx_ring, RX_BUF_LEN); - cur_rx = (cur_rx + rx_size + 4 + 3) & ~3; + cur_rx = ROUND(cur_rx + rx_size + 4, 4); outw(cur_rx - 16, ioaddr + RTL_REG_RXBUFPTR); - /* See RTL8139 Programming Guide V0.1 for the official handling of - * Rx overflow situations. The document itself contains basically no - * usable information, except for a few exception handling rules. */ - outw(status & (RTL_REG_INTRSTATUS_RXFIFOOVER | - RTL_REG_INTRSTATUS_RXOVERFLOW | - RTL_REG_INTRSTATUS_RXOK), ioaddr + RTL_REG_INTRSTATUS); + /* + * See RTL8139 Programming Guide V0.1 for the official handling of + * Rx overflow situations. The document itself contains basically + * no usable information, except for a few exception handling rules. + */ + outw(status & rxstat, ioaddr + RTL_REG_INTRSTATUS); + return length; } From 661479ffc1a0b7ea159dae1ca34d61d009896870 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 12 Apr 2020 22:55:40 +0200 Subject: [PATCH 079/237] net: rtl8139: Minor cleanup of rtl_disable() Rename the function to rtl8139_stop(), clean up checkpatch errors in the stop polling function. No functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/rtl8139.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index d942ccf6273..6aed7bd8957 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -203,7 +203,7 @@ static int rtl8139_read_eeprom(unsigned int location, unsigned int addr_len); static void rtl8139_reset(struct eth_device *dev); static int rtl8139_send(struct eth_device *dev, void *packet, int length); static int rtl8139_recv(struct eth_device *dev); -static void rtl_disable(struct eth_device *dev); +static void rtl8139_stop(struct eth_device *dev); static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, int join) { return (0); @@ -245,7 +245,7 @@ int rtl8139_initialize(bd_t *bis) dev->priv = (void *) devno; dev->iobase = (int)bus_to_phys(iobase); dev->init = rtl8139_probe; - dev->halt = rtl_disable; + dev->halt = rtl8139_stop; dev->send = rtl8139_send; dev->recv = rtl8139_recv; dev->mcast = rtl_bcast_addr; @@ -568,8 +568,9 @@ static int rtl8139_recv(struct eth_device *dev) return length; } -static void rtl_disable(struct eth_device *dev) +static void rtl8139_stop(struct eth_device *dev) { + u8 reg; int i; ioaddr = dev->iobase; @@ -578,8 +579,10 @@ static void rtl_disable(struct eth_device *dev) outb(RTL_REG_CHIPCMD_CMDRESET, ioaddr + RTL_REG_CHIPCMD); /* Give the chip 10ms to finish the reset. */ - for (i=0; i<100; ++i){ - if ((inb(ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_CMDRESET) == 0) break; + for (i = 0; i < 100; i++) { + reg = inb(ioaddr + RTL_REG_CHIPCMD); + if (!(reg & RTL_REG_CHIPCMD_CMDRESET)) + break; udelay (100); /* wait 100us */ } } From 38b306db2334a6565b326874eb4ff536e28654ba Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 12 Apr 2020 22:58:27 +0200 Subject: [PATCH 080/237] net: rtl8139: Factor out hardware reset This hardware reset and reset-wait implementation was twice in the driver, factor it out into a separate function. This really should use wait_for_bit() eventually and return -ETIMEDOUT, but thus far, handling of any of this is missing from the driver. This must be added later. Thus far, no functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/rtl8139.c | 28 +++++++++++----------------- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index 6aed7bd8957..68ef9eea250 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -370,16 +370,13 @@ static void rtl8139_set_rx_mode(struct eth_device *dev) outl(0xffffffff, ioaddr + RTL_REG_MAR0 + 4); } -static void rtl8139_reset(struct eth_device *dev) +static void rtl8139_hw_reset(struct eth_device *dev) { u8 reg; int i; outb(RTL_REG_CHIPCMD_CMDRESET, ioaddr + RTL_REG_CHIPCMD); - cur_rx = 0; - cur_tx = 0; - /* Give the chip 10ms to finish the reset. */ for (i = 0; i < 100; i++) { reg = inb(ioaddr + RTL_REG_CHIPCMD); @@ -388,7 +385,16 @@ static void rtl8139_reset(struct eth_device *dev) udelay(100); } +} +static void rtl8139_reset(struct eth_device *dev) +{ + int i; + + cur_rx = 0; + cur_tx = 0; + + rtl8139_hw_reset(dev); for (i = 0; i < ETH_ALEN; i++) outb(dev->enetaddr[i], ioaddr + RTL_REG_MAC0 + i); @@ -570,19 +576,7 @@ static int rtl8139_recv(struct eth_device *dev) static void rtl8139_stop(struct eth_device *dev) { - u8 reg; - int i; - ioaddr = dev->iobase; - /* reset the chip */ - outb(RTL_REG_CHIPCMD_CMDRESET, ioaddr + RTL_REG_CHIPCMD); - - /* Give the chip 10ms to finish the reset. */ - for (i = 0; i < 100; i++) { - reg = inb(ioaddr + RTL_REG_CHIPCMD); - if (!(reg & RTL_REG_CHIPCMD_CMDRESET)) - break; - udelay (100); /* wait 100us */ - } + rtl8139_hw_reset(dev); } From 0e5a4117a58b8d47b502d7e5536ca6b36d568806 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 12 Apr 2020 23:01:45 +0200 Subject: [PATCH 081/237] net: rtl8139: Finish cleanup Finish the checkpatch cleanup of the driver, fix the remaining issues in probe and init function and in global variables, rename the probe function to rtl8139_init(), no functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/rtl8139.c | 173 +++++++++++++++++++++--------------------- 1 file changed, 87 insertions(+), 86 deletions(-) diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index 68ef9eea250..b901e3a79b7 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -8,68 +8,67 @@ */ /* rtl8139.c - etherboot driver for the Realtek 8139 chipset - - ported from the linux driver written by Donald Becker - by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999 - - This software may be used and distributed according to the terms - of the GNU Public License, incorporated herein by reference. - - changes to the original driver: - - removed support for interrupts, switching to polling mode (yuck!) - - removed support for the 8129 chip (external MII) - -*/ + * + * ported from the linux driver written by Donald Becker + * by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999 + * + * This software may be used and distributed according to the terms + * of the GNU Public License, incorporated herein by reference. + * + * changes to the original driver: + * - removed support for interrupts, switching to polling mode (yuck!) + * - removed support for the 8129 chip (external MII) + */ /*********************************************************************/ /* Revision History */ /*********************************************************************/ /* - 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap) - Put in virt_to_bus calls to allow Etherboot relocation. - - 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap) - Following email from Hyun-Joon Cha, added a disable routine, otherwise - NIC remains live and can crash the kernel later. - - 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub) - Shuffled things around, removed the leftovers from the 8129 support - that was in the Linux driver and added a bit more 8139 definitions. - Moved the 8K receive buffer to a fixed, available address outside the - 0x98000-0x9ffff range. This is a bit of a hack, but currently the only - way to make room for the Etherboot features that need substantial amounts - of code like the ANSI console support. Currently the buffer is just below - 0x10000, so this even conforms to the tagged boot image specification, - which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My - interpretation of this "reserved" is that Etherboot may do whatever it - likes, as long as its environment is kept intact (like the BIOS - variables). Hopefully fixed rtl8139_recv() once and for all. The symptoms - were that if Etherboot was left at the boot menu for several minutes, the - first eth_poll failed. Seems like I am the only person who does this. - First of all I fixed the debugging code and then set out for a long bug - hunting session. It took me about a week full time work - poking around - various places in the driver, reading Don Becker's and Jeff Garzik's Linux - driver and even the FreeBSD driver (what a piece of crap!) - and - eventually spotted the nasty thing: the transmit routine was acknowledging - each and every interrupt pending, including the RxOverrun and RxFIFIOver - interrupts. This confused the RTL8139 thoroughly. It destroyed the - Rx ring contents by dumping the 2K FIFO contents right where we wanted to - get the next packet. Oh well, what fun. - - 18 Jan 2000 mdc@thinguin.org (Marty Connor) - Drastically simplified error handling. Basically, if any error - in transmission or reception occurs, the card is reset. - Also, pointed all transmit descriptors to the same buffer to - save buffer space. This should decrease driver size and avoid - corruption because of exceeding 32K during runtime. - - 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de) - rtl8139_recv was quite broken: it used the RxOK interrupt flag instead - of the RxBufferEmpty flag which often resulted in very bad - transmission performace - below 1kBytes/s. - -*/ + * 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap) + * Put in virt_to_bus calls to allow Etherboot relocation. + * + * 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap) + * Following email from Hyun-Joon Cha, added a disable routine, otherwise + * NIC remains live and can crash the kernel later. + * + * 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub) + * Shuffled things around, removed the leftovers from the 8129 support + * that was in the Linux driver and added a bit more 8139 definitions. + * Moved the 8K receive buffer to a fixed, available address outside the + * 0x98000-0x9ffff range. This is a bit of a hack, but currently the only + * way to make room for the Etherboot features that need substantial amounts + * of code like the ANSI console support. Currently the buffer is just below + * 0x10000, so this even conforms to the tagged boot image specification, + * which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My + * interpretation of this "reserved" is that Etherboot may do whatever it + * likes, as long as its environment is kept intact (like the BIOS + * variables). Hopefully fixed rtl8139_recv() once and for all. The symptoms + * were that if Etherboot was left at the boot menu for several minutes, the + * first eth_poll failed. Seems like I am the only person who does this. + * First of all I fixed the debugging code and then set out for a long bug + * hunting session. It took me about a week full time work - poking around + * various places in the driver, reading Don Becker's and Jeff Garzik's Linux + * driver and even the FreeBSD driver (what a piece of crap!) - and + * eventually spotted the nasty thing: the transmit routine was acknowledging + * each and every interrupt pending, including the RxOverrun and RxFIFIOver + * interrupts. This confused the RTL8139 thoroughly. It destroyed the + * Rx ring contents by dumping the 2K FIFO contents right where we wanted to + * get the next packet. Oh well, what fun. + * + * 18 Jan 2000 mdc@thinguin.org (Marty Connor) + * Drastically simplified error handling. Basically, if any error + * in transmission or reception occurs, the card is reset. + * Also, pointed all transmit descriptors to the same buffer to + * save buffer space. This should decrease driver size and avoid + * corruption because of exceeding 32K during runtime. + * + * 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de) + * rtl8139_recv was quite broken: it used the RxOK interrupt flag instead + * of the RxBufferEmpty flag which often resulted in very bad + * transmission performace - below 1kBytes/s. + * + */ #include #include @@ -82,8 +81,8 @@ #define RTL_TIMEOUT 100000 -/* PCI Tuning Parameters - Threshold is bytes transferred to chip before transmission starts. */ +/* PCI Tuning Parameters */ +/* Threshold is bytes transferred to chip before transmission starts. */ #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ #define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */ #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */ @@ -192,13 +191,13 @@ #define RTL_STS_RXSTATUSOK BIT(0) static int ioaddr; -static unsigned int cur_rx,cur_tx; +static unsigned int cur_rx, cur_tx; /* The RTL8139 can only transmit from a contiguous, aligned memory block. */ -static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4))); -static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4))); +static unsigned char tx_buffer[TX_BUF_SIZE] __aligned(4); +static unsigned char rx_ring[RX_BUF_LEN + 16] __aligned(4); -static int rtl8139_probe(struct eth_device *dev, bd_t *bis); +static int rtl8139_init(struct eth_device *dev, bd_t *bis); static int rtl8139_read_eeprom(unsigned int location, unsigned int addr_len); static void rtl8139_reset(struct eth_device *dev); static int rtl8139_send(struct eth_device *dev, void *packet, int length); @@ -206,82 +205,84 @@ static int rtl8139_recv(struct eth_device *dev); static void rtl8139_stop(struct eth_device *dev); static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, int join) { - return (0); + return 0; } static struct pci_device_id supported[] = { - {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139}, - {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139}, - {} + { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139 }, + { PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139 }, + { } }; int rtl8139_initialize(bd_t *bis) { - pci_dev_t devno; - int card_number = 0; struct eth_device *dev; + int card_number = 0; + pci_dev_t devno; + int idx = 0; u32 iobase; - int idx=0; - while(1){ + while (1) { /* Find RTL8139 */ - if ((devno = pci_find_devices(supported, idx++)) < 0) + devno = pci_find_devices(supported, idx++); + if (devno < 0) break; pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); iobase &= ~0xf; - debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase); + debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase); - dev = (struct eth_device *)malloc(sizeof *dev); + dev = (struct eth_device *)malloc(sizeof(*dev)); if (!dev) { printf("Can not allocate memory of rtl8139\n"); break; } memset(dev, 0, sizeof(*dev)); - sprintf (dev->name, "RTL8139#%d", card_number); + sprintf(dev->name, "RTL8139#%d", card_number); - dev->priv = (void *) devno; + dev->priv = (void *)devno; dev->iobase = (int)bus_to_phys(iobase); - dev->init = rtl8139_probe; + dev->init = rtl8139_init; dev->halt = rtl8139_stop; dev->send = rtl8139_send; dev->recv = rtl8139_recv; dev->mcast = rtl_bcast_addr; - eth_register (dev); + eth_register(dev); card_number++; - pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20); + pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20); - udelay (10 * 1000); + udelay(10 * 1000); } return card_number; } -static int rtl8139_probe(struct eth_device *dev, bd_t *bis) +static int rtl8139_init(struct eth_device *dev, bd_t *bis) { - int i; - int addr_len; unsigned short *ap = (unsigned short *)dev->enetaddr; + int addr_len, i; + u8 reg; ioaddr = dev->iobase; /* Bring the chip out of low-power mode. */ outb(0x00, ioaddr + RTL_REG_CONFIG1); - addr_len = rtl8139_read_eeprom(0,8) == 0x8129 ? 8 : 6; + addr_len = rtl8139_read_eeprom(0, 8) == 0x8129 ? 8 : 6; for (i = 0; i < 3; i++) - *ap++ = le16_to_cpu (rtl8139_read_eeprom(i + 7, addr_len)); + *ap++ = le16_to_cpu(rtl8139_read_eeprom(i + 7, addr_len)); rtl8139_reset(dev); - if (inb(ioaddr + RTL_REG_MEDIASTATUS) & RTL_REG_MEDIASTATUS_MSRLINKFAIL) { + reg = inb(ioaddr + RTL_REG_MEDIASTATUS); + if (reg & RTL_REG_MEDIASTATUS_MSRLINKFAIL) { printf("Cable not connected or other link failure\n"); - return -1 ; + return -1; } return 0; From 6ee6caaf035063dc376eeb3385f7f08f87549b1e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 12 Apr 2020 23:12:11 +0200 Subject: [PATCH 082/237] net: rtl8139: Move functions around Just move functions around in preparation for easy DM conversion, rename rtl_bcast_addr() to rtl8139_bcast_addr(), no functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/rtl8139.c | 179 ++++++++++++++++++++---------------------- 1 file changed, 87 insertions(+), 92 deletions(-) diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index b901e3a79b7..66591d03cec 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -190,104 +190,13 @@ #define RTL_STS_RXBADALIGN BIT(1) #define RTL_STS_RXSTATUSOK BIT(0) -static int ioaddr; static unsigned int cur_rx, cur_tx; +static int ioaddr; /* The RTL8139 can only transmit from a contiguous, aligned memory block. */ static unsigned char tx_buffer[TX_BUF_SIZE] __aligned(4); static unsigned char rx_ring[RX_BUF_LEN + 16] __aligned(4); -static int rtl8139_init(struct eth_device *dev, bd_t *bis); -static int rtl8139_read_eeprom(unsigned int location, unsigned int addr_len); -static void rtl8139_reset(struct eth_device *dev); -static int rtl8139_send(struct eth_device *dev, void *packet, int length); -static int rtl8139_recv(struct eth_device *dev); -static void rtl8139_stop(struct eth_device *dev); -static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, int join) -{ - return 0; -} - -static struct pci_device_id supported[] = { - { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139 }, - { PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139 }, - { } -}; - -int rtl8139_initialize(bd_t *bis) -{ - struct eth_device *dev; - int card_number = 0; - pci_dev_t devno; - int idx = 0; - u32 iobase; - - while (1) { - /* Find RTL8139 */ - devno = pci_find_devices(supported, idx++); - if (devno < 0) - break; - - pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); - iobase &= ~0xf; - - debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase); - - dev = (struct eth_device *)malloc(sizeof(*dev)); - if (!dev) { - printf("Can not allocate memory of rtl8139\n"); - break; - } - memset(dev, 0, sizeof(*dev)); - - sprintf(dev->name, "RTL8139#%d", card_number); - - dev->priv = (void *)devno; - dev->iobase = (int)bus_to_phys(iobase); - dev->init = rtl8139_init; - dev->halt = rtl8139_stop; - dev->send = rtl8139_send; - dev->recv = rtl8139_recv; - dev->mcast = rtl_bcast_addr; - - eth_register(dev); - - card_number++; - - pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20); - - udelay(10 * 1000); - } - - return card_number; -} - -static int rtl8139_init(struct eth_device *dev, bd_t *bis) -{ - unsigned short *ap = (unsigned short *)dev->enetaddr; - int addr_len, i; - u8 reg; - - ioaddr = dev->iobase; - - /* Bring the chip out of low-power mode. */ - outb(0x00, ioaddr + RTL_REG_CONFIG1); - - addr_len = rtl8139_read_eeprom(0, 8) == 0x8129 ? 8 : 6; - for (i = 0; i < 3; i++) - *ap++ = le16_to_cpu(rtl8139_read_eeprom(i + 7, addr_len)); - - rtl8139_reset(dev); - - reg = inb(ioaddr + RTL_REG_MEDIASTATUS); - if (reg & RTL_REG_MEDIASTATUS_MSRLINKFAIL) { - printf("Cable not connected or other link failure\n"); - return -1; - } - - return 0; -} - /* Serial EEPROM section. */ /* EEPROM_Ctrl bits. */ @@ -575,9 +484,95 @@ static int rtl8139_recv(struct eth_device *dev) return length; } +static int rtl8139_init(struct eth_device *dev, bd_t *bis) +{ + unsigned short *ap = (unsigned short *)dev->enetaddr; + int addr_len, i; + u8 reg; + + ioaddr = dev->iobase; + + /* Bring the chip out of low-power mode. */ + outb(0x00, ioaddr + RTL_REG_CONFIG1); + + addr_len = rtl8139_read_eeprom(0, 8) == 0x8129 ? 8 : 6; + for (i = 0; i < 3; i++) + *ap++ = le16_to_cpu(rtl8139_read_eeprom(i + 7, addr_len)); + + rtl8139_reset(dev); + + reg = inb(ioaddr + RTL_REG_MEDIASTATUS); + if (reg & RTL_REG_MEDIASTATUS_MSRLINKFAIL) { + printf("Cable not connected or other link failure\n"); + return -1; + } + + return 0; +} + static void rtl8139_stop(struct eth_device *dev) { ioaddr = dev->iobase; rtl8139_hw_reset(dev); } + +static int rtl8139_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, + int join) +{ + return 0; +} + +static struct pci_device_id supported[] = { + { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139 }, + { PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139 }, + { } +}; + +int rtl8139_initialize(bd_t *bis) +{ + struct eth_device *dev; + int card_number = 0; + pci_dev_t devno; + int idx = 0; + u32 iobase; + + while (1) { + /* Find RTL8139 */ + devno = pci_find_devices(supported, idx++); + if (devno < 0) + break; + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); + iobase &= ~0xf; + + debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase); + + dev = (struct eth_device *)malloc(sizeof(*dev)); + if (!dev) { + printf("Can not allocate memory of rtl8139\n"); + break; + } + memset(dev, 0, sizeof(*dev)); + + sprintf(dev->name, "RTL8139#%d", card_number); + + dev->priv = (void *)devno; + dev->iobase = (int)bus_to_phys(iobase); + dev->init = rtl8139_init; + dev->halt = rtl8139_stop; + dev->send = rtl8139_send; + dev->recv = rtl8139_recv; + dev->mcast = rtl8139_bcast_addr; + + eth_register(dev); + + card_number++; + + pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20); + + udelay(10 * 1000); + } + + return card_number; +} From e7ab86d9b2f24c92552be62b0447abab4f8644a2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 12 Apr 2020 23:49:25 +0200 Subject: [PATCH 083/237] net: rtl8139: Fill in SPDX tag The rtl8139 driver is derived from Etherboot driver, which is in turn derived from Linux 8139too driver added in Linux 2.2.18pre14. An undocumented change in Linux 2.4.10.2 added a new field to the driver, MODULE_LICENSE("GPL"); . According to current Linux kernel licensing rules, Documentation/process/license-rules.rst, quote: "GPL" Module is licensed under GPL version 2. This does not express any distinction between GPL-2.0-only or GPL-2.0-or-later. The exact license information can only be determined via the license information in the corresponding source files. And since the code does not contain any "future" clause, the tag is therefore GPL-2.0 only. Signed-off-by: Marek Vasut Cc: Joe Hershberger --- drivers/net/rtl8139.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index 66591d03cec..1f083972917 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * rtl8139.c : U-Boot driver for the RealTek RTL8139 * @@ -12,9 +13,6 @@ * ported from the linux driver written by Donald Becker * by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999 * - * This software may be used and distributed according to the terms - * of the GNU Public License, incorporated herein by reference. - * * changes to the original driver: * - removed support for interrupts, switching to polling mode (yuck!) * - removed support for the 8129 chip (external MII) From 9c211e3b055ce809ac81ea4f849594ffb6f77df4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 15 Mar 2020 00:08:31 +0100 Subject: [PATCH 084/237] net: smc911x: Remove pkt_data_{push,pull} These functions are never used and are likely a pre-DM remnant from times long past, just remove them. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Masahiro Yamada --- drivers/net/smc911x.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 257b0385c2a..24b4eaeb3fd 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -13,11 +13,6 @@ #include "smc911x.h" -u32 pkt_data_pull(struct eth_device *dev, u32 addr) \ - __attribute__ ((weak, alias ("smc911x_reg_read"))); -void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) \ - __attribute__ ((weak, alias ("smc911x_reg_write"))); - static void smc911x_handle_mac_address(struct eth_device *dev) { unsigned long addrh, addrl; @@ -157,7 +152,7 @@ static int smc911x_send(struct eth_device *dev, void *packet, int length) tmplen = (length + 3) / 4; while (tmplen--) - pkt_data_push(dev, TX_DATA_FIFO, *data++); + smc911x_reg_write(dev, TX_DATA_FIFO, *data++); /* wait for transmission */ while (!((smc911x_reg_read(dev, TX_FIFO_INF) & @@ -203,7 +198,7 @@ static int smc911x_rx(struct eth_device *dev) tmplen = (pktlen + 3) / 4; while (tmplen--) - *data++ = pkt_data_pull(dev, RX_DATA_FIFO); + *data++ = smc911x_reg_read(dev, RX_DATA_FIFO); if (status & RX_STS_ES) printf(DRIVERNAME From 882d5f6983ff23b6f09899bb43d6dfd90ed7492f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 15 Mar 2020 15:14:18 +0100 Subject: [PATCH 085/237] net: smc911x: Replace malloc()+memset() with calloc() Replace combination of malloc()+memset() with calloc() as the behavior is exactly the same and the amount of code is reduced. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Masahiro Yamada --- drivers/net/smc911x.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 24b4eaeb3fd..2c72e3469d5 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -242,11 +242,9 @@ int smc911x_initialize(u8 dev_num, int base_addr) unsigned long addrl, addrh; struct eth_device *dev; - dev = malloc(sizeof(*dev)); - if (!dev) { - return -1; - } - memset(dev, 0, sizeof(*dev)); + dev = calloc(1, sizeof(*dev)); + if (!dev) + return -ENOMEM; dev->iobase = base_addr; From 49af0cb5a61c821d416ef069c6950d82523db585 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 15 Mar 2020 15:40:15 +0100 Subject: [PATCH 086/237] net: smc911x: Rename smc911x_rx() to smc911x_recv() Rename the function to keep the naming scheme consistent, no functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Masahiro Yamada --- drivers/net/smc911x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 2c72e3469d5..6da6c895469 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -184,7 +184,7 @@ static void smc911x_halt(struct eth_device *dev) smc911x_handle_mac_address(dev); } -static int smc911x_rx(struct eth_device *dev) +static int smc911x_recv(struct eth_device *dev) { u32 *data = (u32 *)net_rx_packets[0]; u32 pktlen, tmplen; @@ -269,7 +269,7 @@ int smc911x_initialize(u8 dev_num, int base_addr) dev->init = smc911x_init; dev->halt = smc911x_halt; dev->send = smc911x_send; - dev->recv = smc911x_rx; + dev->recv = smc911x_recv; sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num); eth_register(dev); From 6f6cf0083f466c49c97c175b0169a0cd31c35d63 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 15 Mar 2020 15:43:20 +0100 Subject: [PATCH 087/237] net: smc911x: Invert the logic in smc911x_miiphy_{read,write}() Invert the logic in the aforementioned functions to reduce indent, no functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Masahiro Yamada --- drivers/net/smc911x.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 6da6c895469..ceb4f812152 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -216,24 +216,29 @@ static int smc911x_recv(struct eth_device *dev) static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad, int reg) { - u16 val = 0; struct eth_device *dev = eth_get_dev_by_name(bus->name); - if (dev) { - int retval = smc911x_eth_phy_read(dev, phy, reg, &val); - if (retval < 0) - return retval; - return val; - } - return -ENODEV; + u16 val = 0; + int ret; + + if (!dev) + return -ENODEV; + + ret = smc911x_eth_phy_read(dev, phy, reg, &val); + if (ret < 0) + return ret; + + return val; } /* wrapper for smc911x_eth_phy_write */ static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad, int reg, u16 val) { struct eth_device *dev = eth_get_dev_by_name(bus->name); - if (dev) - return smc911x_eth_phy_write(dev, phy, reg, val); - return -ENODEV; + + if (!dev) + return -ENODEV; + + return smc911x_eth_phy_write(dev, phy, reg, val); } #endif From 9741795408d2fb907256899cd9403dd57b917358 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 15 Mar 2020 15:57:14 +0100 Subject: [PATCH 088/237] net: smc911x: Fix potential memleak() in init fail path Fix memleak in the init fail path, where if allocation or registration of MDIO bus fails, then ethernet interface is not unregistered and the private data are not freed, yet the probe function reports a failure. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Masahiro Yamada --- drivers/net/smc911x.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index ceb4f812152..4459da5945d 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -282,15 +282,23 @@ int smc911x_initialize(u8 dev_num, int base_addr) #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) int retval; struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) + if (!mdiodev) { + eth_unregister(dev); + free(dev); return -ENOMEM; + } + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); mdiodev->read = smc911x_miiphy_read; mdiodev->write = smc911x_miiphy_write; retval = mdio_register(mdiodev); - if (retval < 0) + if (retval < 0) { + mdio_free(mdiodev); + eth_unregister(dev); + free(dev); return retval; + } #endif return 1; From f51a2f84969a1c88fb96414835a3b04883f3d8eb Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 21 Mar 2020 17:25:41 +0100 Subject: [PATCH 089/237] net: smc911x: Pull MII registration into separate function Pull the MII interface registration into separate function to avoid the ifdeffery in smc911x_initialize(). Moreover, adjust the fail path such that we use goto labels. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Masahiro Yamada --- drivers/net/smc911x.c | 64 +++++++++++++++++++++++++++---------------- 1 file changed, 40 insertions(+), 24 deletions(-) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 4459da5945d..65c25f3bfd3 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -240,12 +240,39 @@ static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad, return smc911x_eth_phy_write(dev, phy, reg, val); } + +static int smc911x_initialize_mii(struct eth_device *dev) +{ + struct mii_dev *mdiodev = mdio_alloc(); + int ret; + + if (!mdiodev) + return -ENOMEM; + + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = smc911x_miiphy_read; + mdiodev->write = smc911x_miiphy_write; + + ret = mdio_register(mdiodev); + if (ret < 0) { + mdio_free(mdiodev); + return ret; + } + + return 0; +} +#else +static int smc911x_initialize_mii(struct eth_device *dev) +{ + return 0; +} #endif int smc911x_initialize(u8 dev_num, int base_addr) { unsigned long addrl, addrh; struct eth_device *dev; + int ret; dev = calloc(1, sizeof(*dev)); if (!dev) @@ -254,9 +281,10 @@ int smc911x_initialize(u8 dev_num, int base_addr) dev->iobase = base_addr; /* Try to detect chip. Will fail if not present. */ - if (smc911x_detect_chip(dev)) { - free(dev); - return 0; + ret = smc911x_detect_chip(dev); + if (ret) { + ret = 0; /* Card not detected is not an error */ + goto err_detect; } addrh = smc911x_get_mac_csr(dev, ADDRH); @@ -279,27 +307,15 @@ int smc911x_initialize(u8 dev_num, int base_addr) eth_register(dev); -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) { - eth_unregister(dev); - free(dev); - return -ENOMEM; - } - - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = smc911x_miiphy_read; - mdiodev->write = smc911x_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) { - mdio_free(mdiodev); - eth_unregister(dev); - free(dev); - return retval; - } -#endif + ret = smc911x_initialize_mii(dev); + if (ret) + goto err_mii; return 1; + +err_mii: + eth_unregister(dev); +err_detect: + free(dev); + return ret; } From eb46efa381d6dedb03af77d74b896ff40f1591b8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 15 Mar 2020 15:03:07 +0100 Subject: [PATCH 090/237] net: smc911x: Inline all functions from header file Inline all the functions from the header file, as they are not used outside of the driver or the standalone EEPROM example. Note that this does introduce considerable amount of duplication in the standalone EEPROM example, however that one has to be rewritten anyway, roughly such that the SMC911x driver would expose DM EEPROM interface and the standalone example would use that. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Masahiro Yamada --- drivers/net/smc911x.c | 157 ++++++++++++++++++++++++++- drivers/net/smc911x.h | 157 --------------------------- examples/standalone/smc911x_eeprom.c | 156 ++++++++++++++++++++++++++ 3 files changed, 312 insertions(+), 158 deletions(-) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 65c25f3bfd3..ff285f14b4b 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -10,9 +10,165 @@ #include #include #include +#include #include "smc911x.h" +struct chip_id { + u16 id; + char *name; +}; + +static const struct chip_id chip_ids[] = { + { CHIP_89218, "LAN89218" }, + { CHIP_9115, "LAN9115" }, + { CHIP_9116, "LAN9116" }, + { CHIP_9117, "LAN9117" }, + { CHIP_9118, "LAN9118" }, + { CHIP_9211, "LAN9211" }, + { CHIP_9215, "LAN9215" }, + { CHIP_9216, "LAN9216" }, + { CHIP_9217, "LAN9217" }, + { CHIP_9218, "LAN9218" }, + { CHIP_9220, "LAN9220" }, + { CHIP_9221, "LAN9221" }, + { 0, NULL }, +}; + +#define DRIVERNAME "smc911x" + +#if defined (CONFIG_SMC911X_32_BIT) && \ + defined (CONFIG_SMC911X_16_BIT) +#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \ + CONFIG_SMC911X_16_BIT shall be set" +#endif + +#if defined (CONFIG_SMC911X_32_BIT) +static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset) +{ + return *(volatile u32*)(dev->iobase + offset); +} +u32 smc911x_reg_read(struct eth_device *dev, u32 offset) + __attribute__((weak, alias("__smc911x_reg_read"))); + +static inline void __smc911x_reg_write(struct eth_device *dev, + u32 offset, u32 val) +{ + *(volatile u32*)(dev->iobase + offset) = val; +} +void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val) + __attribute__((weak, alias("__smc911x_reg_write"))); +#elif defined (CONFIG_SMC911X_16_BIT) +static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset) +{ + volatile u16 *addr_16 = (u16 *)(dev->iobase + offset); + return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16)); +} +static inline void smc911x_reg_write(struct eth_device *dev, + u32 offset, u32 val) +{ + *(volatile u16 *)(dev->iobase + offset) = (u16)val; + *(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16); +} +#else +#error "SMC911X: undefined bus width" +#endif /* CONFIG_SMC911X_16_BIT */ + +static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg) +{ + while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + ; + smc911x_reg_write(dev, MAC_CSR_CMD, + MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg); + while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + ; + + return smc911x_reg_read(dev, MAC_CSR_DATA); +} + +static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data) +{ + while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + ; + smc911x_reg_write(dev, MAC_CSR_DATA, data); + smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg); + while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + ; +} + +static int smc911x_detect_chip(struct eth_device *dev) +{ + unsigned long val, i; + + val = smc911x_reg_read(dev, BYTE_TEST); + if (val == 0xffffffff) { + /* Special case -- no chip present */ + return -1; + } else if (val != 0x87654321) { + printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val); + return -1; + } + + val = smc911x_reg_read(dev, ID_REV) >> 16; + for (i = 0; chip_ids[i].id != 0; i++) { + if (chip_ids[i].id == val) break; + } + if (!chip_ids[i].id) { + printf(DRIVERNAME ": Unknown chip ID %04lx\n", val); + return -1; + } + + dev->priv = (void *)&chip_ids[i]; + + return 0; +} + +static void smc911x_reset(struct eth_device *dev) +{ + int timeout; + + /* + * Take out of PM setting first + * Device is already wake up if PMT_CTRL_READY bit is set + */ + if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) { + /* Write to the bytetest will take out of powerdown */ + smc911x_reg_write(dev, BYTE_TEST, 0x0); + + timeout = 10; + + while (timeout-- && + !(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY)) + udelay(10); + if (timeout < 0) { + printf(DRIVERNAME + ": timeout waiting for PM restore\n"); + return; + } + } + + /* Disable interrupts */ + smc911x_reg_write(dev, INT_EN, 0); + + smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST); + + timeout = 1000; + while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY) + udelay(10); + + if (timeout < 0) { + printf(DRIVERNAME ": reset timeout\n"); + return; + } + + /* Reset the FIFO level and flow control settings */ + smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN); + smc911x_reg_write(dev, AFC_CFG, 0x0050287F); + + /* Set to LED outputs */ + smc911x_reg_write(dev, GPIO_CFG, 0x70070000); +} + static void smc911x_handle_mac_address(struct eth_device *dev) { unsigned long addrh, addrl; @@ -117,7 +273,6 @@ static void smc911x_enable(struct eth_device *dev) smc911x_set_mac_csr(dev, MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN | MAC_CR_HBDIS); - } static int smc911x_init(struct eth_device *dev, bd_t * bd) diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h index 3145fbde2bd..ce66900f4cf 100644 --- a/drivers/net/smc911x.h +++ b/drivers/net/smc911x.h @@ -8,47 +8,6 @@ #ifndef _SMC911X_H_ #define _SMC911X_H_ -#include - -#define DRIVERNAME "smc911x" - -#if defined (CONFIG_SMC911X_32_BIT) && \ - defined (CONFIG_SMC911X_16_BIT) -#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \ - CONFIG_SMC911X_16_BIT shall be set" -#endif - -#if defined (CONFIG_SMC911X_32_BIT) -static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset) -{ - return *(volatile u32*)(dev->iobase + offset); -} -u32 smc911x_reg_read(struct eth_device *dev, u32 offset) - __attribute__((weak, alias("__smc911x_reg_read"))); - -static inline void __smc911x_reg_write(struct eth_device *dev, - u32 offset, u32 val) -{ - *(volatile u32*)(dev->iobase + offset) = val; -} -void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val) - __attribute__((weak, alias("__smc911x_reg_write"))); -#elif defined (CONFIG_SMC911X_16_BIT) -static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset) -{ - volatile u16 *addr_16 = (u16 *)(dev->iobase + offset); - return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16)); -} -static inline void smc911x_reg_write(struct eth_device *dev, - u32 offset, u32 val) -{ - *(volatile u16 *)(dev->iobase + offset) = (u16)val; - *(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16); -} -#else -#error "SMC911X: undefined bus width" -#endif /* CONFIG_SMC911X_16_BIT */ - /* Below are the register offsets and bit definitions * of the Lan911x memory space */ @@ -380,120 +339,4 @@ static inline void smc911x_reg_write(struct eth_device *dev, #define CHIP_9220 0x9220 #define CHIP_9221 0x9221 -struct chip_id { - u16 id; - char *name; -}; - -static const struct chip_id chip_ids[] = { - { CHIP_89218, "LAN89218" }, - { CHIP_9115, "LAN9115" }, - { CHIP_9116, "LAN9116" }, - { CHIP_9117, "LAN9117" }, - { CHIP_9118, "LAN9118" }, - { CHIP_9211, "LAN9211" }, - { CHIP_9215, "LAN9215" }, - { CHIP_9216, "LAN9216" }, - { CHIP_9217, "LAN9217" }, - { CHIP_9218, "LAN9218" }, - { CHIP_9220, "LAN9220" }, - { CHIP_9221, "LAN9221" }, - { 0, NULL }, -}; - -static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg) -{ - while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) - ; - smc911x_reg_write(dev, MAC_CSR_CMD, - MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg); - while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) - ; - - return smc911x_reg_read(dev, MAC_CSR_DATA); -} - -static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data) -{ - while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) - ; - smc911x_reg_write(dev, MAC_CSR_DATA, data); - smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg); - while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) - ; -} - -static int smc911x_detect_chip(struct eth_device *dev) -{ - unsigned long val, i; - - val = smc911x_reg_read(dev, BYTE_TEST); - if (val == 0xffffffff) { - /* Special case -- no chip present */ - return -1; - } else if (val != 0x87654321) { - printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val); - return -1; - } - - val = smc911x_reg_read(dev, ID_REV) >> 16; - for (i = 0; chip_ids[i].id != 0; i++) { - if (chip_ids[i].id == val) break; - } - if (!chip_ids[i].id) { - printf(DRIVERNAME ": Unknown chip ID %04lx\n", val); - return -1; - } - - dev->priv = (void *)&chip_ids[i]; - - return 0; -} - -static void smc911x_reset(struct eth_device *dev) -{ - int timeout; - - /* - * Take out of PM setting first - * Device is already wake up if PMT_CTRL_READY bit is set - */ - if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) { - /* Write to the bytetest will take out of powerdown */ - smc911x_reg_write(dev, BYTE_TEST, 0x0); - - timeout = 10; - - while (timeout-- && - !(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY)) - udelay(10); - if (timeout < 0) { - printf(DRIVERNAME - ": timeout waiting for PM restore\n"); - return; - } - } - - /* Disable interrupts */ - smc911x_reg_write(dev, INT_EN, 0); - - smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST); - - timeout = 1000; - while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY) - udelay(10); - - if (timeout < 0) { - printf(DRIVERNAME ": reset timeout\n"); - return; - } - - /* Reset the FIFO level and flow control settings */ - smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN); - smc911x_reg_write(dev, AFC_CFG, 0x0050287F); - - /* Set to LED outputs */ - smc911x_reg_write(dev, GPIO_CFG, 0x70070000); -} - #endif diff --git a/examples/standalone/smc911x_eeprom.c b/examples/standalone/smc911x_eeprom.c index 2c05ed902d0..19ad9e6297c 100644 --- a/examples/standalone/smc911x_eeprom.c +++ b/examples/standalone/smc911x_eeprom.c @@ -18,8 +18,164 @@ #include #include #include +#include #include "../drivers/net/smc911x.h" +#define DRIVERNAME "smc911x" + +#if defined (CONFIG_SMC911X_32_BIT) && \ + defined (CONFIG_SMC911X_16_BIT) +#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \ + CONFIG_SMC911X_16_BIT shall be set" +#endif + +struct chip_id { + u16 id; + char *name; +}; + +static const struct chip_id chip_ids[] = { + { CHIP_89218, "LAN89218" }, + { CHIP_9115, "LAN9115" }, + { CHIP_9116, "LAN9116" }, + { CHIP_9117, "LAN9117" }, + { CHIP_9118, "LAN9118" }, + { CHIP_9211, "LAN9211" }, + { CHIP_9215, "LAN9215" }, + { CHIP_9216, "LAN9216" }, + { CHIP_9217, "LAN9217" }, + { CHIP_9218, "LAN9218" }, + { CHIP_9220, "LAN9220" }, + { CHIP_9221, "LAN9221" }, + { 0, NULL }, +}; + +#if defined (CONFIG_SMC911X_32_BIT) +static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset) +{ + return *(volatile u32*)(dev->iobase + offset); +} +u32 smc911x_reg_read(struct eth_device *dev, u32 offset) + __attribute__((weak, alias("__smc911x_reg_read"))); + +static inline void __smc911x_reg_write(struct eth_device *dev, + u32 offset, u32 val) +{ + *(volatile u32*)(dev->iobase + offset) = val; +} +void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val) + __attribute__((weak, alias("__smc911x_reg_write"))); +#elif defined (CONFIG_SMC911X_16_BIT) +static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset) +{ + volatile u16 *addr_16 = (u16 *)(dev->iobase + offset); + return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16)); +} +static inline void smc911x_reg_write(struct eth_device *dev, + u32 offset, u32 val) +{ + *(volatile u16 *)(dev->iobase + offset) = (u16)val; + *(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16); +} +#else +#error "SMC911X: undefined bus width" +#endif /* CONFIG_SMC911X_16_BIT */ + +static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg) +{ + while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + ; + smc911x_reg_write(dev, MAC_CSR_CMD, + MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg); + while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + ; + + return smc911x_reg_read(dev, MAC_CSR_DATA); +} + +static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data) +{ + while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + ; + smc911x_reg_write(dev, MAC_CSR_DATA, data); + smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg); + while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + ; +} + +static int smc911x_detect_chip(struct eth_device *dev) +{ + unsigned long val, i; + + val = smc911x_reg_read(dev, BYTE_TEST); + if (val == 0xffffffff) { + /* Special case -- no chip present */ + return -1; + } else if (val != 0x87654321) { + printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val); + return -1; + } + + val = smc911x_reg_read(dev, ID_REV) >> 16; + for (i = 0; chip_ids[i].id != 0; i++) { + if (chip_ids[i].id == val) break; + } + if (!chip_ids[i].id) { + printf(DRIVERNAME ": Unknown chip ID %04lx\n", val); + return -1; + } + + dev->priv = (void *)&chip_ids[i]; + + return 0; +} + +static void smc911x_reset(struct eth_device *dev) +{ + int timeout; + + /* + * Take out of PM setting first + * Device is already wake up if PMT_CTRL_READY bit is set + */ + if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) { + /* Write to the bytetest will take out of powerdown */ + smc911x_reg_write(dev, BYTE_TEST, 0x0); + + timeout = 10; + + while (timeout-- && + !(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY)) + udelay(10); + if (timeout < 0) { + printf(DRIVERNAME + ": timeout waiting for PM restore\n"); + return; + } + } + + /* Disable interrupts */ + smc911x_reg_write(dev, INT_EN, 0); + + smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST); + + timeout = 1000; + while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY) + udelay(10); + + if (timeout < 0) { + printf(DRIVERNAME ": reset timeout\n"); + return; + } + + /* Reset the FIFO level and flow control settings */ + smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN); + smc911x_reg_write(dev, AFC_CFG, 0x0050287F); + + /* Set to LED outputs */ + smc911x_reg_write(dev, GPIO_CFG, 0x70070000); +} + /** * smsc_ctrlc - detect press of CTRL+C (common ctrlc() isnt exported!?) */ From f0d73f5cd0ec0967fffcdf130a8c016262a216c4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 15 Mar 2020 14:38:59 +0100 Subject: [PATCH 091/237] net: smc911x: Drop weak alias from 32bit accessors These accessors are not overridden by any board, and even if they were, this is something which should be handled via DM now, so remove the weak alias option. Moreover, drop the inline keyword, as the compiler can decide better. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Masahiro Yamada --- drivers/net/smc911x.c | 14 ++++---------- examples/standalone/smc911x_eeprom.c | 16 +++++----------- 2 files changed, 9 insertions(+), 21 deletions(-) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index ff285f14b4b..effee5367ca 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -44,28 +44,22 @@ static const struct chip_id chip_ids[] = { #endif #if defined (CONFIG_SMC911X_32_BIT) -static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset) +static u32 smc911x_reg_read(struct eth_device *dev, u32 offset) { return *(volatile u32*)(dev->iobase + offset); } -u32 smc911x_reg_read(struct eth_device *dev, u32 offset) - __attribute__((weak, alias("__smc911x_reg_read"))); -static inline void __smc911x_reg_write(struct eth_device *dev, - u32 offset, u32 val) +static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val) { *(volatile u32*)(dev->iobase + offset) = val; } -void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val) - __attribute__((weak, alias("__smc911x_reg_write"))); #elif defined (CONFIG_SMC911X_16_BIT) -static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset) +static u32 smc911x_reg_read(struct eth_device *dev, u32 offset) { volatile u16 *addr_16 = (u16 *)(dev->iobase + offset); return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16)); } -static inline void smc911x_reg_write(struct eth_device *dev, - u32 offset, u32 val) +static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val) { *(volatile u16 *)(dev->iobase + offset) = (u16)val; *(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16); diff --git a/examples/standalone/smc911x_eeprom.c b/examples/standalone/smc911x_eeprom.c index 19ad9e6297c..270588bcf5e 100644 --- a/examples/standalone/smc911x_eeprom.c +++ b/examples/standalone/smc911x_eeprom.c @@ -51,28 +51,22 @@ static const struct chip_id chip_ids[] = { }; #if defined (CONFIG_SMC911X_32_BIT) -static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset) +static u32 smc911x_reg_read(struct eth_device *dev, u32 offset) { return *(volatile u32*)(dev->iobase + offset); } -u32 smc911x_reg_read(struct eth_device *dev, u32 offset) - __attribute__((weak, alias("__smc911x_reg_read"))); -static inline void __smc911x_reg_write(struct eth_device *dev, - u32 offset, u32 val) +static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val) { *(volatile u32*)(dev->iobase + offset) = val; } -void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val) - __attribute__((weak, alias("__smc911x_reg_write"))); #elif defined (CONFIG_SMC911X_16_BIT) -static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset) +static u32 smc911x_reg_read(struct eth_device *dev, u32 offset) { volatile u16 *addr_16 = (u16 *)(dev->iobase + offset); - return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16)); + return (*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16); } -static inline void smc911x_reg_write(struct eth_device *dev, - u32 offset, u32 val) +static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val) { *(volatile u16 *)(dev->iobase + offset) = (u16)val; *(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16); From ba267c781da73ab0df4a7a57c05ef21c19aee609 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 15 Mar 2020 14:42:23 +0100 Subject: [PATCH 092/237] net: smc911x: Convert IO accessors to {read,write}{w,l}() Convert the IO accessors to standard ones instead of using volatile void pointers, as those do not cover all the bus access details. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Masahiro Yamada --- drivers/net/smc911x.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index effee5367ca..364f8c5da8d 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include "smc911x.h" @@ -46,23 +47,23 @@ static const struct chip_id chip_ids[] = { #if defined (CONFIG_SMC911X_32_BIT) static u32 smc911x_reg_read(struct eth_device *dev, u32 offset) { - return *(volatile u32*)(dev->iobase + offset); + return readl(dev->iobase + offset); } static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val) { - *(volatile u32*)(dev->iobase + offset) = val; + writel(val, dev->iobase + offset); } #elif defined (CONFIG_SMC911X_16_BIT) static u32 smc911x_reg_read(struct eth_device *dev, u32 offset) { - volatile u16 *addr_16 = (u16 *)(dev->iobase + offset); - return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16)); + return (readw(dev->iobase + offset) & 0xffff) | + (readw(dev->iobase + offset + 2) << 16); } static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val) { - *(volatile u16 *)(dev->iobase + offset) = (u16)val; - *(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16); + writew(val & 0xffff, dev->iobase + offset); + writew(val >> 16, dev->iobase + offset + 2); } #else #error "SMC911X: undefined bus width" From 3dbab926031fe77d794670c05d6c7badcfa77291 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 15 Mar 2020 15:36:09 +0100 Subject: [PATCH 093/237] net: smc911x: Pass around driver private data Introduce a private data structure for this driver with embedded struct eth_device and pass it around. This prepares the driver to work with both DM and non-DM systems. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Masahiro Yamada --- drivers/net/smc911x.c | 232 ++++++++++++++++++++++-------------------- 1 file changed, 124 insertions(+), 108 deletions(-) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 364f8c5da8d..07066ce1083 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -20,6 +20,13 @@ struct chip_id { char *name; }; +struct smc911x_priv { + struct eth_device dev; + phys_addr_t iobase; + const struct chip_id *chipid; + unsigned char enetaddr[6]; +}; + static const struct chip_id chip_ids[] = { { CHIP_89218, "LAN89218" }, { CHIP_9115, "LAN9115" }, @@ -45,57 +52,57 @@ static const struct chip_id chip_ids[] = { #endif #if defined (CONFIG_SMC911X_32_BIT) -static u32 smc911x_reg_read(struct eth_device *dev, u32 offset) +static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset) { - return readl(dev->iobase + offset); + return readl(priv->iobase + offset); } -static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val) +static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val) { - writel(val, dev->iobase + offset); + writel(val, priv->iobase + offset); } #elif defined (CONFIG_SMC911X_16_BIT) -static u32 smc911x_reg_read(struct eth_device *dev, u32 offset) +static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset) { - return (readw(dev->iobase + offset) & 0xffff) | - (readw(dev->iobase + offset + 2) << 16); + return (readw(priv->iobase + offset) & 0xffff) | + (readw(priv->iobase + offset + 2) << 16); } -static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val) +static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val) { - writew(val & 0xffff, dev->iobase + offset); - writew(val >> 16, dev->iobase + offset + 2); + writew(val & 0xffff, priv->iobase + offset); + writew(val >> 16, priv->iobase + offset + 2); } #else #error "SMC911X: undefined bus width" #endif /* CONFIG_SMC911X_16_BIT */ -static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg) +static u32 smc911x_get_mac_csr(struct smc911x_priv *priv, u8 reg) { - while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ; - smc911x_reg_write(dev, MAC_CSR_CMD, + smc911x_reg_write(priv, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg); - while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ; - return smc911x_reg_read(dev, MAC_CSR_DATA); + return smc911x_reg_read(priv, MAC_CSR_DATA); } -static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data) +static void smc911x_set_mac_csr(struct smc911x_priv *priv, u8 reg, u32 data) { - while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ; - smc911x_reg_write(dev, MAC_CSR_DATA, data); - smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg); - while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + smc911x_reg_write(priv, MAC_CSR_DATA, data); + smc911x_reg_write(priv, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg); + while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ; } -static int smc911x_detect_chip(struct eth_device *dev) +static int smc911x_detect_chip(struct smc911x_priv *priv) { unsigned long val, i; - val = smc911x_reg_read(dev, BYTE_TEST); + val = smc911x_reg_read(priv, BYTE_TEST); if (val == 0xffffffff) { /* Special case -- no chip present */ return -1; @@ -104,7 +111,7 @@ static int smc911x_detect_chip(struct eth_device *dev) return -1; } - val = smc911x_reg_read(dev, ID_REV) >> 16; + val = smc911x_reg_read(priv, ID_REV) >> 16; for (i = 0; chip_ids[i].id != 0; i++) { if (chip_ids[i].id == val) break; } @@ -113,12 +120,12 @@ static int smc911x_detect_chip(struct eth_device *dev) return -1; } - dev->priv = (void *)&chip_ids[i]; + priv->chipid = &chip_ids[i]; return 0; } -static void smc911x_reset(struct eth_device *dev) +static void smc911x_reset(struct smc911x_priv *priv) { int timeout; @@ -126,14 +133,14 @@ static void smc911x_reset(struct eth_device *dev) * Take out of PM setting first * Device is already wake up if PMT_CTRL_READY bit is set */ - if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) { + if ((smc911x_reg_read(priv, PMT_CTRL) & PMT_CTRL_READY) == 0) { /* Write to the bytetest will take out of powerdown */ - smc911x_reg_write(dev, BYTE_TEST, 0x0); + smc911x_reg_write(priv, BYTE_TEST, 0x0); timeout = 10; while (timeout-- && - !(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY)) + !(smc911x_reg_read(priv, PMT_CTRL) & PMT_CTRL_READY)) udelay(10); if (timeout < 0) { printf(DRIVERNAME @@ -143,12 +150,12 @@ static void smc911x_reset(struct eth_device *dev) } /* Disable interrupts */ - smc911x_reg_write(dev, INT_EN, 0); + smc911x_reg_write(priv, INT_EN, 0); - smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST); + smc911x_reg_write(priv, HW_CFG, HW_CFG_SRST); timeout = 1000; - while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY) + while (timeout-- && smc911x_reg_read(priv, E2P_CMD) & E2P_CMD_EPC_BUSY) udelay(10); if (timeout < 0) { @@ -157,83 +164,83 @@ static void smc911x_reset(struct eth_device *dev) } /* Reset the FIFO level and flow control settings */ - smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN); - smc911x_reg_write(dev, AFC_CFG, 0x0050287F); + smc911x_set_mac_csr(priv, FLOW, FLOW_FCPT | FLOW_FCEN); + smc911x_reg_write(priv, AFC_CFG, 0x0050287F); /* Set to LED outputs */ - smc911x_reg_write(dev, GPIO_CFG, 0x70070000); + smc911x_reg_write(priv, GPIO_CFG, 0x70070000); } -static void smc911x_handle_mac_address(struct eth_device *dev) +static void smc911x_handle_mac_address(struct smc911x_priv *priv) { unsigned long addrh, addrl; - uchar *m = dev->enetaddr; + unsigned char *m = priv->enetaddr; addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24); addrh = m[4] | (m[5] << 8); - smc911x_set_mac_csr(dev, ADDRL, addrl); - smc911x_set_mac_csr(dev, ADDRH, addrh); + smc911x_set_mac_csr(priv, ADDRL, addrl); + smc911x_set_mac_csr(priv, ADDRH, addrh); printf(DRIVERNAME ": MAC %pM\n", m); } -static int smc911x_eth_phy_read(struct eth_device *dev, +static int smc911x_eth_phy_read(struct smc911x_priv *priv, u8 phy, u8 reg, u16 *val) { - while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) + while (smc911x_get_mac_csr(priv, MII_ACC) & MII_ACC_MII_BUSY) ; - smc911x_set_mac_csr(dev, MII_ACC, phy << 11 | reg << 6 | + smc911x_set_mac_csr(priv, MII_ACC, phy << 11 | reg << 6 | MII_ACC_MII_BUSY); - while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) + while (smc911x_get_mac_csr(priv, MII_ACC) & MII_ACC_MII_BUSY) ; - *val = smc911x_get_mac_csr(dev, MII_DATA); + *val = smc911x_get_mac_csr(priv, MII_DATA); return 0; } -static int smc911x_eth_phy_write(struct eth_device *dev, +static int smc911x_eth_phy_write(struct smc911x_priv *priv, u8 phy, u8 reg, u16 val) { - while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) + while (smc911x_get_mac_csr(priv, MII_ACC) & MII_ACC_MII_BUSY) ; - smc911x_set_mac_csr(dev, MII_DATA, val); - smc911x_set_mac_csr(dev, MII_ACC, + smc911x_set_mac_csr(priv, MII_DATA, val); + smc911x_set_mac_csr(priv, MII_ACC, phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE); - while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) + while (smc911x_get_mac_csr(priv, MII_ACC) & MII_ACC_MII_BUSY) ; return 0; } -static int smc911x_phy_reset(struct eth_device *dev) +static int smc911x_phy_reset(struct smc911x_priv *priv) { u32 reg; - reg = smc911x_reg_read(dev, PMT_CTRL); + reg = smc911x_reg_read(priv, PMT_CTRL); reg &= ~0xfffff030; reg |= PMT_CTRL_PHY_RST; - smc911x_reg_write(dev, PMT_CTRL, reg); + smc911x_reg_write(priv, PMT_CTRL, reg); mdelay(100); return 0; } -static void smc911x_phy_configure(struct eth_device *dev) +static void smc911x_phy_configure(struct smc911x_priv *priv) { int timeout; u16 status; - smc911x_phy_reset(dev); + smc911x_phy_reset(priv); - smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_RESET); + smc911x_eth_phy_write(priv, 1, MII_BMCR, BMCR_RESET); mdelay(1); - smc911x_eth_phy_write(dev, 1, MII_ADVERTISE, 0x01e1); - smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_ANENABLE | + smc911x_eth_phy_write(priv, 1, MII_ADVERTISE, 0x01e1); + smc911x_eth_phy_write(priv, 1, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); timeout = 5000; @@ -242,7 +249,7 @@ static void smc911x_phy_configure(struct eth_device *dev) if ((timeout--) == 0) goto err_out; - if (smc911x_eth_phy_read(dev, 1, MII_BMSR, &status) != 0) + if (smc911x_eth_phy_read(priv, 1, MII_BMSR, &status) != 0) goto err_out; } while (!(status & BMSR_LSTATUS)); @@ -254,64 +261,66 @@ err_out: printf(DRIVERNAME ": autonegotiation timed out\n"); } -static void smc911x_enable(struct eth_device *dev) +static void smc911x_enable(struct smc911x_priv *priv) { /* Enable TX */ - smc911x_reg_write(dev, HW_CFG, 8 << 16 | HW_CFG_SF); + smc911x_reg_write(priv, HW_CFG, 8 << 16 | HW_CFG_SF); - smc911x_reg_write(dev, GPT_CFG, GPT_CFG_TIMER_EN | 10000); + smc911x_reg_write(priv, GPT_CFG, GPT_CFG_TIMER_EN | 10000); - smc911x_reg_write(dev, TX_CFG, TX_CFG_TX_ON); + smc911x_reg_write(priv, TX_CFG, TX_CFG_TX_ON); /* no padding to start of packets */ - smc911x_reg_write(dev, RX_CFG, 0); + smc911x_reg_write(priv, RX_CFG, 0); - smc911x_set_mac_csr(dev, MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN | + smc911x_set_mac_csr(priv, MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN | MAC_CR_HBDIS); } static int smc911x_init(struct eth_device *dev, bd_t * bd) { - struct chip_id *id = dev->priv; + struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev); + const struct chip_id *id = priv->chipid; printf(DRIVERNAME ": detected %s controller\n", id->name); - smc911x_reset(dev); + smc911x_reset(priv); /* Configure the PHY, initialize the link state */ - smc911x_phy_configure(dev); + smc911x_phy_configure(priv); - smc911x_handle_mac_address(dev); + smc911x_handle_mac_address(priv); /* Turn on Tx + Rx */ - smc911x_enable(dev); + smc911x_enable(priv); return 0; } static int smc911x_send(struct eth_device *dev, void *packet, int length) { + struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev); u32 *data = (u32*)packet; u32 tmplen; u32 status; - smc911x_reg_write(dev, TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG | + smc911x_reg_write(priv, TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG | TX_CMD_A_INT_LAST_SEG | length); - smc911x_reg_write(dev, TX_DATA_FIFO, length); + smc911x_reg_write(priv, TX_DATA_FIFO, length); tmplen = (length + 3) / 4; while (tmplen--) - smc911x_reg_write(dev, TX_DATA_FIFO, *data++); + smc911x_reg_write(priv, TX_DATA_FIFO, *data++); /* wait for transmission */ - while (!((smc911x_reg_read(dev, TX_FIFO_INF) & + while (!((smc911x_reg_read(priv, TX_FIFO_INF) & TX_FIFO_INF_TSUSED) >> 16)); /* get status. Ignore 'no carrier' error, it has no meaning for * full duplex operation */ - status = smc911x_reg_read(dev, TX_STATUS_FIFO) & + status = smc911x_reg_read(priv, TX_STATUS_FIFO) & (TX_STS_LOC | TX_STS_LATE_COLL | TX_STS_MANY_COLL | TX_STS_MANY_DEFER | TX_STS_UNDERRUN); @@ -330,25 +339,28 @@ static int smc911x_send(struct eth_device *dev, void *packet, int length) static void smc911x_halt(struct eth_device *dev) { - smc911x_reset(dev); - smc911x_handle_mac_address(dev); + struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev); + + smc911x_reset(priv); + smc911x_handle_mac_address(priv); } static int smc911x_recv(struct eth_device *dev) { + struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev); u32 *data = (u32 *)net_rx_packets[0]; u32 pktlen, tmplen; u32 status; - if ((smc911x_reg_read(dev, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) { - status = smc911x_reg_read(dev, RX_STATUS_FIFO); + if ((smc911x_reg_read(priv, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) { + status = smc911x_reg_read(priv, RX_STATUS_FIFO); pktlen = (status & RX_STS_PKT_LEN) >> 16; - smc911x_reg_write(dev, RX_CFG, 0); + smc911x_reg_write(priv, RX_CFG, 0); tmplen = (pktlen + 3) / 4; while (tmplen--) - *data++ = smc911x_reg_read(dev, RX_DATA_FIFO); + *data++ = smc911x_reg_read(priv, RX_DATA_FIFO); if (status & RX_STS_ES) printf(DRIVERNAME @@ -367,31 +379,34 @@ static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad, int reg) { struct eth_device *dev = eth_get_dev_by_name(bus->name); + struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev); u16 val = 0; int ret; - if (!dev) + if (!dev || !priv) return -ENODEV; - ret = smc911x_eth_phy_read(dev, phy, reg, &val); + ret = smc911x_eth_phy_read(priv, phy, reg, &val); if (ret < 0) return ret; return val; } + /* wrapper for smc911x_eth_phy_write */ static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad, int reg, u16 val) { struct eth_device *dev = eth_get_dev_by_name(bus->name); + struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev); - if (!dev) + if (!dev || !priv) return -ENODEV; - return smc911x_eth_phy_write(dev, phy, reg, val); + return smc911x_eth_phy_write(priv, phy, reg, val); } -static int smc911x_initialize_mii(struct eth_device *dev) +static int smc911x_initialize_mii(struct smc911x_priv *priv) { struct mii_dev *mdiodev = mdio_alloc(); int ret; @@ -399,7 +414,7 @@ static int smc911x_initialize_mii(struct eth_device *dev) if (!mdiodev) return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + strncpy(mdiodev->name, priv->dev.name, MDIO_NAME_LEN); mdiodev->read = smc911x_miiphy_read; mdiodev->write = smc911x_miiphy_write; @@ -412,7 +427,7 @@ static int smc911x_initialize_mii(struct eth_device *dev) return 0; } #else -static int smc911x_initialize_mii(struct eth_device *dev) +static int smc911x_initialize_mii(struct smc911x_priv *priv) { return 0; } @@ -421,51 +436,52 @@ static int smc911x_initialize_mii(struct eth_device *dev) int smc911x_initialize(u8 dev_num, int base_addr) { unsigned long addrl, addrh; - struct eth_device *dev; + struct smc911x_priv *priv; int ret; - dev = calloc(1, sizeof(*dev)); - if (!dev) + priv = calloc(1, sizeof(*priv)); + if (!priv) return -ENOMEM; - dev->iobase = base_addr; + priv->iobase = base_addr; + priv->dev.iobase = base_addr; /* Try to detect chip. Will fail if not present. */ - ret = smc911x_detect_chip(dev); + ret = smc911x_detect_chip(priv); if (ret) { ret = 0; /* Card not detected is not an error */ goto err_detect; } - addrh = smc911x_get_mac_csr(dev, ADDRH); - addrl = smc911x_get_mac_csr(dev, ADDRL); + addrh = smc911x_get_mac_csr(priv, ADDRH); + addrl = smc911x_get_mac_csr(priv, ADDRL); if (!(addrl == 0xffffffff && addrh == 0x0000ffff)) { /* address is obtained from optional eeprom */ - dev->enetaddr[0] = addrl; - dev->enetaddr[1] = addrl >> 8; - dev->enetaddr[2] = addrl >> 16; - dev->enetaddr[3] = addrl >> 24; - dev->enetaddr[4] = addrh; - dev->enetaddr[5] = addrh >> 8; + priv->enetaddr[0] = addrl; + priv->enetaddr[1] = addrl >> 8; + priv->enetaddr[2] = addrl >> 16; + priv->enetaddr[3] = addrl >> 24; + priv->enetaddr[4] = addrh; + priv->enetaddr[5] = addrh >> 8; } - dev->init = smc911x_init; - dev->halt = smc911x_halt; - dev->send = smc911x_send; - dev->recv = smc911x_recv; - sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num); + priv->dev.init = smc911x_init; + priv->dev.halt = smc911x_halt; + priv->dev.send = smc911x_send; + priv->dev.recv = smc911x_recv; + sprintf(priv->dev.name, "%s-%hu", DRIVERNAME, dev_num); - eth_register(dev); + eth_register(&priv->dev); - ret = smc911x_initialize_mii(dev); + ret = smc911x_initialize_mii(priv); if (ret) goto err_mii; return 1; err_mii: - eth_unregister(dev); + eth_unregister(&priv->dev); err_detect: - free(dev); + free(priv); return ret; } From b11c8bbfafa998e90fe93ab4e9b08c1a4959bd65 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 15 Mar 2020 17:02:05 +0100 Subject: [PATCH 094/237] net: smc911x: Clean up the status handling in smc911x_recv() Invert the status handling logic in smc911x_recv(), to make the function easier to read, no functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Masahiro Yamada --- drivers/net/smc911x.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 07066ce1083..2d1a9e0f5a9 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -352,23 +352,25 @@ static int smc911x_recv(struct eth_device *dev) u32 pktlen, tmplen; u32 status; - if ((smc911x_reg_read(priv, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) { - status = smc911x_reg_read(priv, RX_STATUS_FIFO); - pktlen = (status & RX_STS_PKT_LEN) >> 16; + status = smc911x_reg_read(priv, RX_FIFO_INF); + if (!(status & RX_FIFO_INF_RXSUSED)) + return 0; - smc911x_reg_write(priv, RX_CFG, 0); + status = smc911x_reg_read(priv, RX_STATUS_FIFO); + pktlen = (status & RX_STS_PKT_LEN) >> 16; - tmplen = (pktlen + 3) / 4; - while (tmplen--) - *data++ = smc911x_reg_read(priv, RX_DATA_FIFO); + smc911x_reg_write(priv, RX_CFG, 0); - if (status & RX_STS_ES) - printf(DRIVERNAME - ": dropped bad packet. Status: 0x%08x\n", - status); - else - net_process_received_packet(net_rx_packets[0], pktlen); - } + tmplen = (pktlen + 3) / 4; + while (tmplen--) + *data++ = smc911x_reg_read(priv, RX_DATA_FIFO); + + if (status & RX_STS_ES) + printf(DRIVERNAME + ": dropped bad packet. Status: 0x%08x\n", + status); + else + net_process_received_packet(net_rx_packets[0], pktlen); return 0; } From 8eb4fef11b5420020518486ef0305aada0a02467 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 15 Mar 2020 17:25:27 +0100 Subject: [PATCH 095/237] net: smc911x: Split non-DM specific bits from common code Split network handling functions into non-DM specific parts and common code in preparation for conversion to DM. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Masahiro Yamada Acked-by: Joe Hershberger --- drivers/net/smc911x.c | 57 ++++++++++++++++++++++++++++++++----------- 1 file changed, 43 insertions(+), 14 deletions(-) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 2d1a9e0f5a9..95f955f6d8a 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -277,9 +277,8 @@ static void smc911x_enable(struct smc911x_priv *priv) MAC_CR_HBDIS); } -static int smc911x_init(struct eth_device *dev, bd_t * bd) +static int smc911x_init_common(struct smc911x_priv *priv) { - struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev); const struct chip_id *id = priv->chipid; printf(DRIVERNAME ": detected %s controller\n", id->name); @@ -297,9 +296,9 @@ static int smc911x_init(struct eth_device *dev, bd_t * bd) return 0; } -static int smc911x_send(struct eth_device *dev, void *packet, int length) +static int smc911x_send_common(struct smc911x_priv *priv, + void *packet, int length) { - struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev); u32 *data = (u32*)packet; u32 tmplen; u32 status; @@ -337,18 +336,14 @@ static int smc911x_send(struct eth_device *dev, void *packet, int length) return -1; } -static void smc911x_halt(struct eth_device *dev) +static void smc911x_halt_common(struct smc911x_priv *priv) { - struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev); - smc911x_reset(priv); smc911x_handle_mac_address(priv); } -static int smc911x_recv(struct eth_device *dev) +static int smc911x_recv_common(struct smc911x_priv *priv, u32 *data) { - struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev); - u32 *data = (u32 *)net_rx_packets[0]; u32 pktlen, tmplen; u32 status; @@ -365,14 +360,14 @@ static int smc911x_recv(struct eth_device *dev) while (tmplen--) *data++ = smc911x_reg_read(priv, RX_DATA_FIFO); - if (status & RX_STS_ES) + if (status & RX_STS_ES) { printf(DRIVERNAME ": dropped bad packet. Status: 0x%08x\n", status); - else - net_process_received_packet(net_rx_packets[0], pktlen); + return 0; + } - return 0; + return pktlen; } #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) @@ -435,6 +430,40 @@ static int smc911x_initialize_mii(struct smc911x_priv *priv) } #endif +static int smc911x_init(struct eth_device *dev, bd_t *bd) +{ + struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev); + + return smc911x_init_common(priv); +} + +static void smc911x_halt(struct eth_device *dev) +{ + struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev); + + smc911x_halt_common(priv); +} + +static int smc911x_send(struct eth_device *dev, void *packet, int length) +{ + struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev); + + return smc911x_send_common(priv, packet, length); +} + +static int smc911x_recv(struct eth_device *dev) +{ + struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev); + u32 *data = (u32 *)net_rx_packets[0]; + int ret; + + ret = smc911x_recv_common(priv, data); + if (ret) + net_process_received_packet(net_rx_packets[0], ret); + + return ret; +} + int smc911x_initialize(u8 dev_num, int base_addr) { unsigned long addrl, addrh; From 8148693b988fb36463dbc12cef4b7947acae9846 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 15 Mar 2020 17:39:01 +0100 Subject: [PATCH 096/237] net: smc911x: Add DM support Add support for U-Boot DM and DT probing. Furthermore, build the SMC911x standalone EEPROM example only for the non-DM case, as it is not converted yet. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Masahiro Yamada --- drivers/net/Kconfig | 2 + drivers/net/smc911x.c | 115 +++++++++++++++++++++++++++++++++++ examples/standalone/Makefile | 5 +- 3 files changed, 121 insertions(+), 1 deletion(-) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index bc518f218da..a2587a29e16 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -388,11 +388,13 @@ config SMC911X if SMC911X +if !DM_ETH config SMC911X_BASE hex "SMC911X Base Address" help Define this to hold the physical address of the device (I/O space) +endif #DM_ETH choice prompt "SMC911X bus width" diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 95f955f6d8a..45ecd6a2633 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -21,7 +21,9 @@ struct chip_id { }; struct smc911x_priv { +#ifndef CONFIG_DM_ETH struct eth_device dev; +#endif phys_addr_t iobase; const struct chip_id *chipid; unsigned char enetaddr[6]; @@ -370,6 +372,8 @@ static int smc911x_recv_common(struct smc911x_priv *priv, u32 *data) return pktlen; } +#ifndef CONFIG_DM_ETH + #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) /* wrapper for smc911x_eth_phy_read */ static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad, @@ -494,6 +498,7 @@ int smc911x_initialize(u8 dev_num, int base_addr) priv->enetaddr[3] = addrl >> 24; priv->enetaddr[4] = addrh; priv->enetaddr[5] = addrh >> 8; + memcpy(priv->dev.enetaddr, priv->enetaddr, 6); } priv->dev.init = smc911x_init; @@ -516,3 +521,113 @@ err_detect: free(priv); return ret; } + +#else /* ifdef CONFIG_DM_ETH */ + +static int smc911x_start(struct udevice *dev) +{ + struct eth_pdata *plat = dev_get_platdata(dev); + struct smc911x_priv *priv = dev_get_priv(dev); + + memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr)); + + return smc911x_init_common(priv); +} + +static void smc911x_stop(struct udevice *dev) +{ + struct smc911x_priv *priv = dev_get_priv(dev); + + smc911x_halt_common(priv); +} + +static int smc911x_send(struct udevice *dev, void *packet, int length) +{ + struct smc911x_priv *priv = dev_get_priv(dev); + int ret; + + ret = smc911x_send_common(priv, packet, length); + + return ret ? 0 : -ETIMEDOUT; +} + +static int smc911x_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct smc911x_priv *priv = dev_get_priv(dev); + u32 *data = (u32 *)net_rx_packets[0]; + int ret; + + ret = smc911x_recv_common(priv, data); + if (ret) + *packetp = (void *)data; + + return ret ? ret : -EAGAIN; +} + +static int smc911x_bind(struct udevice *dev) +{ + return device_set_name(dev, dev->name); +} + +static int smc911x_probe(struct udevice *dev) +{ + struct smc911x_priv *priv = dev_get_priv(dev); + unsigned long addrh, addrl; + int ret; + + /* Try to detect chip. Will fail if not present. */ + ret = smc911x_detect_chip(priv); + if (ret) + return ret; + + addrh = smc911x_get_mac_csr(priv, ADDRH); + addrl = smc911x_get_mac_csr(priv, ADDRL); + if (!(addrl == 0xffffffff && addrh == 0x0000ffff)) { + /* address is obtained from optional eeprom */ + priv->enetaddr[0] = addrl; + priv->enetaddr[1] = addrl >> 8; + priv->enetaddr[2] = addrl >> 16; + priv->enetaddr[3] = addrl >> 24; + priv->enetaddr[4] = addrh; + priv->enetaddr[5] = addrh >> 8; + } + + return 0; +} + +static int smc911x_ofdata_to_platdata(struct udevice *dev) +{ + struct smc911x_priv *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + + pdata->iobase = devfdt_get_addr(dev); + priv->iobase = pdata->iobase; + + return 0; +} + +static const struct eth_ops smc911x_ops = { + .start = smc911x_start, + .send = smc911x_send, + .recv = smc911x_recv, + .stop = smc911x_stop, +}; + +static const struct udevice_id smc911x_ids[] = { + { .compatible = "smsc,lan9115" }, + { } +}; + +U_BOOT_DRIVER(smc911x) = { + .name = "eth_smc911x", + .id = UCLASS_ETH, + .of_match = smc911x_ids, + .bind = smc911x_bind, + .ofdata_to_platdata = smc911x_ofdata_to_platdata, + .probe = smc911x_probe, + .ops = &smc911x_ops, + .priv_auto_alloc_size = sizeof(struct smc911x_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; +#endif diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index 779e2528b77..4a34813804f 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -5,10 +5,13 @@ extra-y := hello_world extra-$(CONFIG_SMC91111) += smc91111_eeprom -extra-$(CONFIG_SMC911X) += smc911x_eeprom extra-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2 extra-$(CONFIG_PPC) += sched +ifndef CONFIG_DM_ETH +extra-$(CONFIG_SMC911X) += smc911x_eeprom +endif + # # Some versions of make do not handle trailing white spaces properly; # leading to build failures. The problem was found with GNU Make 3.80. From e7882f65f02eca5a7d35871ba0355462bbf7362e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 10 Apr 2020 20:54:49 +0200 Subject: [PATCH 097/237] tiny-printf: Support %i The most basic printf("%i", value) formating string was missing, add it for the sake of convenience. Signed-off-by: Marek Vasut Cc: Simon Glass Cc: Stefan Roese --- lib/tiny-printf.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c index 1138c7012ae..8fc7e48d994 100644 --- a/lib/tiny-printf.c +++ b/lib/tiny-printf.c @@ -242,6 +242,7 @@ static int _vprintf(struct printf_info *info, const char *fmt, va_list va) goto abort; case 'u': case 'd': + case 'i': div = 1000000000; if (islong) { num = va_arg(va, unsigned long); @@ -251,7 +252,7 @@ static int _vprintf(struct printf_info *info, const char *fmt, va_list va) num = va_arg(va, unsigned int); } - if (ch == 'd') { + if (ch != 'u') { if (islong && (long)num < 0) { num = -(long)num; out(info, '-'); From f8dc7f2f18d324343737c72e27b6bd0ee8ff728e Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 10 Apr 2020 16:02:02 +0200 Subject: [PATCH 098/237] configs: migrate CONFIG_SYS_ARM_CACHE_* in Kconfig Move CONFIG_SYS_ARM_CACHE_WRITETHROUGH and CONFIG_SYS_ARM_CACHE_WRITEALLOC into Kconfig done by moveconfig.py. Kconfig uses a choice between the 3 values supported in U-Boot, including the new configuration CONFIG_SYS_ARM_CACHE_WRITEBACK (the default configuration). The patch also avoids to select simultaneously 2 configurations. Signed-off-by: Patrick Delaunay --- arch/arm/Kconfig | 28 +++++++++++++++++++++ arch/arm/include/asm/iproc-common/configs.h | 1 - include/configs/grpeach.h | 1 - include/configs/pxa-common.h | 2 -- scripts/config_whitelist.txt | 1 - 5 files changed, 28 insertions(+), 5 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8e67e1c5873..8b6c6a2965c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -340,6 +340,34 @@ config SYS_CACHELINE_SIZE default 64 if SYS_CACHE_SHIFT_6 default 32 if SYS_CACHE_SHIFT_5 +choice + prompt "Select the ARM data write cache policy" + default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \ + TARGET_BCMNSP || CPU_PXA || RZA1 + default SYS_ARM_CACHE_WRITEBACK + +config SYS_ARM_CACHE_WRITEBACK + bool "Write-back (WB)" + help + A write updates the cache only and marks the cache line as dirty. + External memory is updated only when the line is evicted or explicitly + cleaned. + +config SYS_ARM_CACHE_WRITETHROUGH + bool "Write-through (WT)" + help + A write updates both the cache and the external memory system. + This does not mark the cache line as dirty. + +config SYS_ARM_CACHE_WRITEALLOC + bool "Write allocation (WA)" + help + A cache line is allocated on a write miss. This means that executing a + store instruction on the processor might cause a burst read to occur. + There is a linefill to obtain the data for the cache line, before the + write is performed. +endchoice + config ARCH_CPU_INIT bool "Enable ARCH_CPU_INIT" help diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h index 96c4f54f4a4..4733c0793c3 100644 --- a/arch/arm/include/asm/iproc-common/configs.h +++ b/arch/arm/include/asm/iproc-common/configs.h @@ -10,7 +10,6 @@ /* Architecture, CPU, chip, etc */ #define CONFIG_IPROC -#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH /* Memory Info */ #define CONFIG_SYS_SDRAM_BASE 0x61000000 diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index f1ea729eb38..001e9d385ba 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -16,7 +16,6 @@ /* Miscellaneous */ #define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH #define CONFIG_CMDLINE_TAG /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ diff --git a/include/configs/pxa-common.h b/include/configs/pxa-common.h index e25800a0958..2632d48cc9c 100644 --- a/include/configs/pxa-common.h +++ b/include/configs/pxa-common.h @@ -8,8 +8,6 @@ #ifndef __CONFIG_PXA_COMMON_H__ #define __CONFIG_PXA_COMMON_H__ -#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH - /* * KGDB */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 12a6698958e..7a5da9d822a 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1770,7 +1770,6 @@ CONFIG_SYS_AMASK4 CONFIG_SYS_AMASK5 CONFIG_SYS_AMASK6 CONFIG_SYS_AMASK7 -CONFIG_SYS_ARM_CACHE_WRITETHROUGH CONFIG_SYS_AT91_CPU_NAME CONFIG_SYS_AT91_MAIN_CLOCK CONFIG_SYS_AT91_PLLA From c8ec1e3ff505a6ce44ec36e77d0579f5d01ed6b8 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 24 Apr 2020 20:20:15 +0200 Subject: [PATCH 099/237] arm: caches: protect dram_bank_mmu_setup access to bi_dram Add protection in dram_bank_mmu_setup() to avoid access to bd->bi_dram before relocation. This patch allow to use the generic weak function dram_bank_mmu_setup to activate the MMU and the data cache in SPL or in U-Boot before relocation, when bd->bi_dram is not yet initialized. In this cases, the MMU must be initialized explicitly with mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay --- arch/arm/lib/cache-cp15.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index f8d20960da9..54509f11c30 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -91,6 +91,10 @@ __weak void dram_bank_mmu_setup(int bank) bd_t *bd = gd->bd; int i; + /* bd->bi_dram is available only after relocation */ + if ((gd->flags & GD_FLG_RELOC) == 0) + return; + debug("%s: bank: %d\n", __func__, bank); for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) + From 2e8d68e241b35d383a057b014287a756624a32bc Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 24 Apr 2020 20:20:16 +0200 Subject: [PATCH 100/237] arm: caches: add DCACHE_DEFAULT_OPTION Add the new flags DCACHE_DEFAULT_OPTION to define the default option to use according the compilation flags CONFIG_SYS_ARM_CACHE_*. This new compilation flag allows to simplify dram_bank_mmu_setup() and can be used as third parameter (option=dcache option to select) of mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay --- arch/arm/include/asm/system.h | 8 ++++++++ arch/arm/lib/cache-cp15.c | 11 ++--------- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 81ccead1127..a3147fde146 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -485,6 +485,14 @@ enum dcache_option { }; #endif +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK +#endif + /* Size of an MMU section */ enum { #ifdef CONFIG_ARMV7_LPAE diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 54509f11c30..d15144188bf 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -99,15 +99,8 @@ __weak void dram_bank_mmu_setup(int bank) for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) + (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT); - i++) { -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) - set_section_dcache(i, DCACHE_WRITETHROUGH); -#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) - set_section_dcache(i, DCACHE_WRITEALLOC); -#else - set_section_dcache(i, DCACHE_WRITEBACK); -#endif - } + i++) + set_section_dcache(i, DCACHE_DEFAULT_OPTION); } /* to activate the MMU we need to set up virtual memory: use 1M areas */ From 54be09cd8f6e66f59144f9e5861b0252ed441d89 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 24 Apr 2020 20:20:17 +0200 Subject: [PATCH 101/237] arm: caches: manage phys_addr_t overflow in mmu_set_region_dcache_behaviour Solved the overflow on phys_addr_t type for start + size in mmu_set_region_dcache_behaviour() function. This overflow is avoided by dividing start and end by 2 before addition, and we only expecting that start and size are even. This patch doesn't change the current function behavior if the parameters (start or size) are not aligned on MMU_SECTION_SIZE. For example, this overflow occurs on ARM32 with: start = 0xC0000000 and size = 0x40000000 then start + size = 0x100000000 and end = 0x0. For information the function behavior change with risk of regression, if we just shift start and size before the addition. Example with 2MB section size: MMU_SECTION_SIZE 0x200000 and MMU_SECTION_SHIFT = 21 with start = 0x1000000, size = 0x1000000, - with the proposed patch, start = 0 and end = 0x1 as previously - with the more simple patch: end = (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT) the value of end change: start >> 21 = 0, size >> 21 = 0 and end = 0x0 !!! Signed-off-by: Patrick Delaunay --- arch/arm/lib/cache-cp15.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index d15144188bf..f803d6fb8ce 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -61,8 +61,11 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, unsigned long startpt, stoppt; unsigned long upto, end; - end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; + /* div by 2 before start + size to avoid phys_addr_t overflow */ + end = ALIGN((start / 2) + (size / 2), MMU_SECTION_SIZE / 2) + >> (MMU_SECTION_SHIFT - 1); start = start >> MMU_SECTION_SHIFT; + #ifdef CONFIG_ARMV7_LPAE debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size, option); From b8a42e0fcb94b335e0661ff4d2366ee3edf7f883 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Fri, 1 May 2020 15:24:50 +0200 Subject: [PATCH 102/237] rtc: pcf2127: don't add/subtract 1 to tm_mon As noted in rtc_def.h, the tm_mon field in struct rtc_time is 1-12, unlike in struct tm where it is 0-11. Currently, running "date" prints the wrong Date: 2020-04-01 (Friday) Time: 13:05:30 and setting the RTC via the date command is also broken. Signed-off-by: Rasmus Villemoes --- drivers/rtc/pcf2127.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/rtc/pcf2127.c b/drivers/rtc/pcf2127.c index f6953505a5a..b34ed63bf05 100644 --- a/drivers/rtc/pcf2127.c +++ b/drivers/rtc/pcf2127.c @@ -56,7 +56,7 @@ static int pcf2127_rtc_set(struct udevice *dev, const struct rtc_time *tm) buf[i++] = tm->tm_wday & 0x07; /* month, 1 - 12 */ - buf[i++] = bin2bcd(tm->tm_mon + 1); + buf[i++] = bin2bcd(tm->tm_mon); /* year */ buf[i++] = bin2bcd(tm->tm_year % 100); @@ -83,7 +83,7 @@ static int pcf2127_rtc_get(struct udevice *dev, struct rtc_time *tm) tm->tm_min = bcd2bin(buf[PCF2127_REG_MN] & 0x7F); tm->tm_hour = bcd2bin(buf[PCF2127_REG_HR] & 0x3F); tm->tm_mday = bcd2bin(buf[PCF2127_REG_DM] & 0x3F); - tm->tm_mon = bcd2bin(buf[PCF2127_REG_MO] & 0x1F) - 1; + tm->tm_mon = bcd2bin(buf[PCF2127_REG_MO] & 0x1F); tm->tm_year = bcd2bin(buf[PCF2127_REG_YR]) + 1900; if (tm->tm_year < 1970) tm->tm_year += 100; /* assume we are in 1970...2069 */ From 932b8f8c29811fd0560c4df1221156fa498edfc5 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Fri, 24 Apr 2020 23:31:20 +0200 Subject: [PATCH 103/237] doc: describe the analysis of crash dumps Provide an overview of the analysis of U-Boot crash dumps. Signed-off-by: Heinrich Schuchardt Acked-by: Ilias Apalodimas --- doc/develop/crash_dumps.rst | 122 ++++++++++++++++++++++++++++++++++++ doc/develop/index.rst | 10 +++ doc/index.rst | 11 ++++ 3 files changed, 143 insertions(+) create mode 100644 doc/develop/crash_dumps.rst create mode 100644 doc/develop/index.rst diff --git a/doc/develop/crash_dumps.rst b/doc/develop/crash_dumps.rst new file mode 100644 index 00000000000..18696372fc7 --- /dev/null +++ b/doc/develop/crash_dumps.rst @@ -0,0 +1,122 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (c) 2020 Heinrich Schuchardt + +Analyzing crash dumps +===================== + +When the CPU detects an instruction that it cannot execute it raises an +interrupt. U-Boot than writes a crash dump. This chapter describes how such +dump can be analyzed. + +Creating a crash dump voluntarily +--------------------------------- + +For describing the analysis of a crash dump we need an example. U-Boot comes +with a command 'exception' that comes in handy here. The command is enabled +by:: + + CONFIG_CMD_EXCEPTION=y + +The example output below was recorded when running qemu\_arm64\_defconfig on +QEMU:: + + => exception undefined + "Synchronous Abort" handler, esr 0x02000000 + elr: 00000000000101fc lr : 00000000000214ec (reloc) + elr: 000000007ff291fc lr : 000000007ff3a4ec + x0 : 000000007ffbd7f8 x1 : 0000000000000000 + x2 : 0000000000000001 x3 : 000000007eedce18 + x4 : 000000007ff291fc x5 : 000000007eedce50 + x6 : 0000000000000064 x7 : 000000007eedce10 + x8 : 0000000000000000 x9 : 0000000000000004 + x10: 6db6db6db6db6db7 x11: 000000000000000d + x12: 0000000000000006 x13: 000000000001869f + x14: 000000007edd7dc0 x15: 0000000000000002 + x16: 000000007ff291fc x17: 0000000000000000 + x18: 000000007eed8dc0 x19: 0000000000000000 + x20: 000000007ffbd7f8 x21: 0000000000000000 + x22: 000000007eedce10 x23: 0000000000000002 + x24: 000000007ffd4c80 x25: 0000000000000000 + x26: 0000000000000000 x27: 0000000000000000 + x28: 000000007eedce70 x29: 000000007edd7b40 + + Code: b00003c0 912ad000 940029d6 17ffff52 (e7f7defb) + Resetting CPU ... + + resetting ... + +The first line provides us with the type of interrupt that occurred. +(On ARMv8 a synchronous abort is an exception where the return address stored +in the ESR register indicates the instruction that caused the exception.) + +The second line provides the contents of the elr and the lr register after +subtracting the relocation offset. - U-Boot relocates itself after being +loaded. - The relocation offset can also be displayed using the bdinfo command. + +After the contents of the registers we get a line indicating the machine +code of the instructions preceding the crash and in parentheses the instruction +leading to the dump. + +Analyzing the code location +--------------------------- + +We can convert the instructions in the line starting with 'Code:' into mnemonics +using the objdump command. To make things easier scripts/decodecode is +supplied:: + + $echo 'Code: b00003c0 912ad000 940029d6 17ffff52 (e7f7defb)' | \ + CROSS_COMPILE=aarch64-linux-gnu- ARCH=arm64 scripts/decodecode + Code: b00003c0 912ad000 940029d6 17ffff52 (e7f7defb) + All code + ======== + 0: b00003c0 adrp x0, 0x79000 + 4: 912ad000 add x0, x0, #0xab4 + 8: 940029d6 bl 0xa760 + c: 17ffff52 b 0xfffffffffffffd54 + 10:* e7f7defb .inst 0xe7f7defb ; undefined <-- trapping instruction + + Code starting with the faulting instruction + =========================================== + 0: e7f7defb .inst 0xe7f7defb ; undefined + +Now lets use the locations provided by the elr and lr registers after +subtracting the relocation offset to find out where in the code the crash +occurred and from where it was invoked. + +File u-boot.map contains the memory layout of the U-Boot binary. Here we find +these lines:: + + .text.do_undefined + 0x00000000000101fc 0xc cmd/built-in.o + .text.exception_complete + 0x0000000000010208 0x90 cmd/built-in.o + ... + .text.cmd_process + 0x00000000000213b8 0x164 common/built-in.o + 0x00000000000213b8 cmd_process + .text.cmd_process_error + 0x000000000002151c 0x40 common/built-in.o + 0x000000000002151c cmd_process_error + +So the error occurred at the start of function do\_undefined() and this +function was invoked from somewhere inside function cmd\_process(). + +If we want to dive deeper, we can disassemble the U-Boot binary:: + + $ aarch64-linux-gnu-objdump -S -D u-boot | less + + 00000000000101fc : + { + /* + * 0xe7f...f. is undefined in ARM mode + * 0xde.. is undefined in Thumb mode + */ + asm volatile (".word 0xe7f7defb\n"); + 101fc: e7f7defb .inst 0xe7f7defb ; undefined + return CMD_RET_FAILURE; + } + 10200: 52800020 mov w0, #0x1 // #1 + 10204: d65f03c0 ret + +This example is based on the ARMv8 architecture but the same procedures can be +used on other architectures as well. diff --git a/doc/develop/index.rst b/doc/develop/index.rst new file mode 100644 index 00000000000..072db63b5cb --- /dev/null +++ b/doc/develop/index.rst @@ -0,0 +1,10 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Develop U-Boot +============== + + +.. toctree:: + :maxdepth: 2 + + crash_dumps diff --git a/doc/index.rst b/doc/index.rst index cd98be6cc5f..fd9f10f28e4 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -26,6 +26,17 @@ trying to get it to work optimally on a given system. build/index +Developer-oriented documentation +-------------------------------- + +The following manuals are written for *developers* of the U-Boot - those who +want to contribute to U-Boot. + +.. toctree:: + :maxdepth: 2 + + develop/index + Unified Extensible Firmware (UEFI) ---------------------------------- From 6609d123ce48ca5d46bb1c8e285fe009acf491ca Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Sun, 26 Apr 2020 01:17:44 +0200 Subject: [PATCH 104/237] timer MediaTek use upstream compatible The timers compatible string in upstream is called mt6577-timer. Add this compatible to the driver. Signed-off-by: Matthias Brugger --- drivers/timer/mtk_timer.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/timer/mtk_timer.c b/drivers/timer/mtk_timer.c index b5e76bd3586..e99135e5bec 100644 --- a/drivers/timer/mtk_timer.c +++ b/drivers/timer/mtk_timer.c @@ -71,6 +71,7 @@ static const struct timer_ops mtk_timer_ops = { static const struct udevice_id mtk_timer_ids[] = { { .compatible = "mediatek,timer" }, + { .compatible = "mediatek,mt6577-timer" }, { } }; From 2ef35fcb34b97fefc693f638be2ad18be3298d08 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Sun, 26 Apr 2020 01:17:45 +0200 Subject: [PATCH 105/237] watchdog MediaTek add upstream compatible The upstream compatible is called mt6589-wdt. Add this compatible to the driver. Signed-off-by: Matthias Brugger --- drivers/watchdog/mtk_wdt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index 669a32320d4..b3c597e1d03 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -143,6 +143,7 @@ static const struct wdt_ops mtk_wdt_ops = { static const struct udevice_id mtk_wdt_ids[] = { { .compatible = "mediatek,wdt"}, + { .compatible = "mediatek,mt6589-wdt"}, {} }; From 37f2755a00c1b3223780d88c7a82e2f6af26a18e Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Sun, 26 Apr 2020 01:17:46 +0200 Subject: [PATCH 106/237] arm: enable distro boot for bananapi-r2 This patch enables distro boot for the bananapi-r2, based on a MediaTek mt7623n. Signed-off-by: Matthias Brugger --- configs/mt7623n_bpir2_defconfig | 3 ++- include/configs/mt7623.h | 24 ++++++++++++++++++++---- 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig index 07ddade76a4..fe28f37b9eb 100644 --- a/configs/mt7623n_bpir2_defconfig +++ b/configs/mt7623n_bpir2_defconfig @@ -7,6 +7,7 @@ CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x100000 CONFIG_TARGET_MT7623=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=3 @@ -56,4 +57,4 @@ CONFIG_TIMER=y CONFIG_MTK_TIMER=y CONFIG_WDT_MTK=y CONFIG_LZMA=y -# CONFIG_EFI_LOADER is not set +CONFIG_EFI_LOADER=y diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h index faab0913fc9..fe436cca389 100644 --- a/include/configs/mt7623.h +++ b/include/configs/mt7623.h @@ -45,11 +45,13 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* This is needed for kernel booting */ -#define FDT_HIGH "fdt_high=0xac000000\0" +#define FDT_HIGH "0xac000000" -/* Extra environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - FDT_HIGH +#define ENV_MEM_LAYOUT_SETTINGS \ + "fdt_high=" FDT_HIGH "\0" \ + "kernel_addr_r=0x84000000\0" \ + "fdt_addr_r=" FDT_HIGH "\0" \ + "fdtfile=mt7623n-bananapi-bpi-r2.dtb" "\0" /* Ethernet */ #define CONFIG_IPADDR 192.168.1.1 @@ -57,4 +59,18 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 +#ifdef CONFIG_DISTRO_DEFAULTS + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) + +#include + +/* Extra environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV + +#endif /* ifdef CONFIG_DISTRO_DEFAULTS*/ + #endif From fc21a88f801c41a535397a359b3b5bdc3ef8e79f Mon Sep 17 00:00:00 2001 From: Sven Roederer Date: Mon, 27 Apr 2020 02:08:38 +0200 Subject: [PATCH 107/237] tools/mkimage: fix handling long filenames The cmdline for calling the dtc was cut-off when using long filenames (e.g. 245 bytes) for output-file and datafile of "-f" parameter. For FIT-images cmd[MKIMAGE_MAX_DTC_CMDLINE_LEN] is declared (hardcoded 512 bytes), and contains some static values, the path of a tmpfile and a datafile. tmpfile is max MKIMAGE_MAX_TMPFILE_LEN (256) and datafile might be also this size. Having two very long pathname results in a truncation os the executed shell command, as the truncated datafile path will not be found. Redefine MKIMAGE_MAX_DTC_CMDLINE_LEN to "2 * MKIMAGE_MAX_TMPFILE_LEN + 35 for the parameters. This likely applies to the "-d" parameter, too. Signed-off-by: Sven Roederer --- tools/mkimage.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/mkimage.h b/tools/mkimage.h index 0254af59fbe..5b096a545b7 100644 --- a/tools/mkimage.h +++ b/tools/mkimage.h @@ -42,6 +42,6 @@ static inline ulong map_to_sysmem(void *ptr) #define MKIMAGE_TMPFILE_SUFFIX ".tmp" #define MKIMAGE_MAX_TMPFILE_LEN 256 #define MKIMAGE_DEFAULT_DTC_OPTIONS "-I dts -O dtb -p 500" -#define MKIMAGE_MAX_DTC_CMDLINE_LEN 512 +#define MKIMAGE_MAX_DTC_CMDLINE_LEN 2 * MKIMAGE_MAX_TMPFILE_LEN + 35 #endif /* _MKIIMAGE_H_ */ From ea5d3731b843b14f1c48d0d0f2c7d2877ecbf673 Mon Sep 17 00:00:00 2001 From: Sven Roederer Date: Mon, 27 Apr 2020 02:08:39 +0200 Subject: [PATCH 108/237] tools/fit-image: print a warning when cmd-line for dtc might be truncated Signed-off-by: Sven Roederer --- tools/fit_image.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tools/fit_image.c b/tools/fit_image.c index 4aeabbcfe97..88ff093d05b 100644 --- a/tools/fit_image.c +++ b/tools/fit_image.c @@ -17,6 +17,7 @@ #include "fit_common.h" #include "mkimage.h" #include +#include #include #include #include @@ -744,6 +745,9 @@ static int fit_handle_file(struct image_tool_params *params) snprintf(cmd, sizeof(cmd), "cp \"%s\" \"%s\"", params->imagefile, tmpfile); } + if (strlen(cmd) >= MKIMAGE_MAX_DTC_CMDLINE_LEN - 1) { + fprintf(stderr, "WARNING: command-line for FIT creation might be truncated and will probably fail.\n"); + } if (*cmd && system(cmd) == -1) { fprintf (stderr, "%s: system(%s) failed: %s\n", From b142d0ac1946701f4d592869c2d81e42afe2e294 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 28 Apr 2020 21:40:13 +0200 Subject: [PATCH 109/237] cmd/gpt: avoid NULL check before free() free() checks if its argument is NULL. Do not duplicate this in the calling code. Signed-off-by: Heinrich Schuchardt Reviewed-by: Tom Rini --- cmd/gpt.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/cmd/gpt.c b/cmd/gpt.c index b94f0051cdd..b8d11c167df 100644 --- a/cmd/gpt.c +++ b/cmd/gpt.c @@ -772,11 +772,9 @@ static int do_rename_gpt_parts(struct blk_desc *dev_desc, char *subcomm, out: del_gpt_info(); #ifdef CONFIG_RANDOM_UUID - if (str_disk_guid) - free(str_disk_guid); + free(str_disk_guid); #endif - if (new_partitions) - free(new_partitions); + free(new_partitions); free(partitions_list); return ret; } From 4fb0f55fd294aca02407ef1def74a22612fa041b Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 28 Apr 2020 21:50:02 +0200 Subject: [PATCH 110/237] fs: ext4: avoid NULL check before free() free() checks if its argument is NULL. Don't duplicate this in the calling code. Signed-off-by: Heinrich Schuchardt --- fs/ext4/ext4_journal.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/fs/ext4/ext4_journal.c b/fs/ext4/ext4_journal.c index f8524e5a99a..0ceb73d9c91 100644 --- a/fs/ext4/ext4_journal.c +++ b/fs/ext4/ext4_journal.c @@ -107,22 +107,18 @@ void ext4fs_free_journal(void) for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) { if (dirty_block_ptr[i]->blknr == -1) break; - if (dirty_block_ptr[i]->buf) - free(dirty_block_ptr[i]->buf); + free(dirty_block_ptr[i]->buf); } for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) { if (journal_ptr[i]->blknr == -1) break; - if (journal_ptr[i]->buf) - free(journal_ptr[i]->buf); + free(journal_ptr[i]->buf); } for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) { - if (journal_ptr[i]) - free(journal_ptr[i]); - if (dirty_block_ptr[i]) - free(dirty_block_ptr[i]); + free(journal_ptr[i]); + free(dirty_block_ptr[i]); } gindex = 0; gd_index = 0; @@ -272,8 +268,7 @@ void ext4fs_free_revoke_blks(void) struct revoke_blk_list *next_node = NULL; while (tmp_node != NULL) { - if (tmp_node->content) - free(tmp_node->content); + free(tmp_node->content); tmp_node = tmp_node->next; } From f4070e6f6c680034d67f13b878f0da55b3b51f92 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 28 Apr 2020 21:56:10 +0200 Subject: [PATCH 111/237] hush: avoid NULL check before free() free() checks if its argument is NULL. Don't duplicate this in the calling code. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- common/cli_hush.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/common/cli_hush.c b/common/cli_hush.c index cf1e273485c..a62af07cc54 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -1849,8 +1849,7 @@ static int run_list_real(struct pipe *pi) continue; } else { /* insert new value from list for variable */ - if (pi->progs->argv[0]) - free(pi->progs->argv[0]); + free(pi->progs->argv[0]); pi->progs->argv[0] = *list++; #ifndef __U_BOOT__ pi->progs->glob_result.gl_pathv[0] = From eb7690e81f527ae36ecc05e567848606ccebde01 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Wed, 29 Apr 2020 15:26:16 +0200 Subject: [PATCH 112/237] test/py: vboot: add a test to check fit signature on fit with padding The pytest vboot does all his tests on fit without padding. We add the same tests on fit with padding. Reviewed-by: Simon Glass Signed-off-by: Philippe Reynes --- test/py/tests/test_vboot.py | 52 +++++++++++++++++++++++-------------- 1 file changed, 33 insertions(+), 19 deletions(-) diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py index e67f2b3d0f6..6b998cfd70e 100644 --- a/test/py/tests/test_vboot.py +++ b/test/py/tests/test_vboot.py @@ -30,11 +30,16 @@ import u_boot_utils as util import vboot_forge TESTDATA = [ - ['sha1', '', False], - ['sha1', '-pss', False], - ['sha256', '', False], - ['sha256', '-pss', False], - ['sha256', '-pss', True], + ['sha1', '', None, False], + ['sha1', '', '-E -p 0x10000', False], + ['sha1', '-pss', None, False], + ['sha1', '-pss', '-E -p 0x10000', False], + ['sha256', '', None, False], + ['sha256', '', '-E -p 0x10000', False], + ['sha256', '-pss', None, False], + ['sha256', '-pss', '-E -p 0x10000', False], + ['sha256', '-pss', None, True], + ['sha256', '-pss', '-E -p 0x10000', True], ] @pytest.mark.boardspec('sandbox') @@ -43,8 +48,8 @@ TESTDATA = [ @pytest.mark.requiredtool('fdtget') @pytest.mark.requiredtool('fdtput') @pytest.mark.requiredtool('openssl') -@pytest.mark.parametrize("sha_algo,padding,required", TESTDATA) -def test_vboot(u_boot_console, sha_algo, padding, required): +@pytest.mark.parametrize("sha_algo,padding,sign_options,required", TESTDATA) +def test_vboot(u_boot_console, sha_algo, padding, sign_options, required): """Test verified boot signing with mkimage and verification with 'bootm'. This works using sandbox only as it needs to update the device tree used @@ -104,7 +109,7 @@ def test_vboot(u_boot_console, sha_algo, padding, required): util.run_and_log(cons, [mkimage, '-D', dtc_args, '-f', '%s%s' % (datadir, its), fit]) - def sign_fit(sha_algo): + def sign_fit(sha_algo, options): """Sign the FIT Signs the FIT and writes the signature into it. It also writes the @@ -113,10 +118,13 @@ def test_vboot(u_boot_console, sha_algo, padding, required): Args: sha_algo: Either 'sha1' or 'sha256', to select the algorithm to use. + options: Options to provide to mkimage. """ + args = [mkimage, '-F', '-k', tmpdir, '-K', dtb, '-r', fit] + if options: + args += options.split(' ') cons.log.action('%s: Sign images' % sha_algo) - util.run_and_log(cons, [mkimage, '-F', '-k', tmpdir, '-K', dtb, - '-r', fit]) + util.run_and_log(cons, args) def replace_fit_totalsize(size): """Replace FIT header's totalsize with something greater. @@ -154,7 +162,7 @@ def test_vboot(u_boot_console, sha_algo, padding, required): util.run_and_log(cons, 'openssl req -batch -new -x509 -key %s%s.key ' '-out %s%s.crt' % (tmpdir, name, tmpdir, name)) - def test_with_algo(sha_algo, padding): + def test_with_algo(sha_algo, padding, sign_options): """Test verified boot with the given hash algorithm. This is the main part of the test code. The same procedure is followed @@ -163,6 +171,9 @@ def test_vboot(u_boot_console, sha_algo, padding, required): Args: sha_algo: Either 'sha1' or 'sha256', to select the algorithm to use. + padding: Either '' or '-pss', to select the padding to use for the + rsa signature algorithm. + sign_options: Options to mkimage when signing a fit image. """ # Compile our device tree files for kernel and U-Boot. These are # regenerated here since mkimage will modify them (by adding a @@ -176,7 +187,7 @@ def test_vboot(u_boot_console, sha_algo, padding, required): run_bootm(sha_algo, 'unsigned images', 'dev-', True) # Sign images with our dev keys - sign_fit(sha_algo) + sign_fit(sha_algo, sign_options) run_bootm(sha_algo, 'signed images', 'dev+', True) # Create a fresh .dtb without the public keys @@ -187,7 +198,7 @@ def test_vboot(u_boot_console, sha_algo, padding, required): run_bootm(sha_algo, 'unsigned config', '%s+ OK' % sha_algo, True) # Sign images with our dev keys - sign_fit(sha_algo) + sign_fit(sha_algo, sign_options) run_bootm(sha_algo, 'signed config', 'dev+', True) cons.log.action('%s: Check signed config on the host' % sha_algo) @@ -209,7 +220,7 @@ def test_vboot(u_boot_console, sha_algo, padding, required): # Create a new properly signed fit and replace header bytes make_fit('sign-configs-%s%s.its' % (sha_algo, padding)) - sign_fit(sha_algo) + sign_fit(sha_algo, sign_options) bcfg = u_boot_console.config.buildconfig max_size = int(bcfg.get('config_fit_signature_max_size', 0x10000000), 0) existing_size = replace_fit_totalsize(max_size + 1) @@ -240,7 +251,7 @@ def test_vboot(u_boot_console, sha_algo, padding, required): cons, [fit_check_sign, '-f', fit, '-k', dtb], 1, 'Failed to verify required signature') - def test_required_key(sha_algo, padding): + def test_required_key(sha_algo, padding, sign_options): """Test verified boot with the given hash algorithm. This function tests if U-Boot rejects an image when a required key isn't @@ -248,6 +259,9 @@ def test_vboot(u_boot_console, sha_algo, padding, required): Args: sha_algo: Either 'sha1' or 'sha256', to select the algorithm to use + padding: Either '' or '-pss', to select the padding to use for the + rsa signature algorithm. + sign_options: Options to mkimage when signing a fit image. """ # Compile our device tree files for kernel and U-Boot. These are # regenerated here since mkimage will modify them (by adding a @@ -260,12 +274,12 @@ def test_vboot(u_boot_console, sha_algo, padding, required): # Build the FIT with prod key (keys required) and sign it. This puts the # signature into sandbox-u-boot.dtb, marked 'required' make_fit('sign-configs-%s%s-prod.its' % (sha_algo, padding)) - sign_fit(sha_algo) + sign_fit(sha_algo, sign_options) # Build the FIT with dev key (keys NOT required). This adds the # signature into sandbox-u-boot.dtb, NOT marked 'required'. make_fit('sign-configs-%s%s.its' % (sha_algo, padding)) - sign_fit(sha_algo) + sign_fit(sha_algo, sign_options) # So now sandbox-u-boot.dtb two signatures, for the prod and dev keys. # Only the prod key is set as 'required'. But FIT we just built has @@ -297,9 +311,9 @@ def test_vboot(u_boot_console, sha_algo, padding, required): old_dtb = cons.config.dtb cons.config.dtb = dtb if required: - test_required_key(sha_algo, padding) + test_required_key(sha_algo, padding, sign_options) else: - test_with_algo(sha_algo, padding) + test_with_algo(sha_algo, padding, sign_options) finally: # Go back to the original U-Boot with the correct dtb. cons.config.dtb = old_dtb From c522949a29d44d728517cc2579ed719747da3e5d Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Wed, 29 Apr 2020 15:26:17 +0200 Subject: [PATCH 113/237] rsa: sig: fix config signature check for fit with padding The signature check on config node is broken on fit with padding. To compute the signature for config node, U-Boot compute the signature on all properties of requested node for this config, except for the property "data". But, when padding is used for binary in a fit, there isn't a property "data" but two properties: "data-offset" and "data-size". So to fix the check of signature, we also don't use the properties "data-offset" and "data-size" when checking the signature on config node. Reviewed-by: Simon Glass Signed-off-by: Philippe Reynes --- common/image-fit-sig.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/image-fit-sig.c b/common/image-fit-sig.c index 3e735785949..a3a0c61bcbf 100644 --- a/common/image-fit-sig.c +++ b/common/image-fit-sig.c @@ -249,7 +249,7 @@ static int fit_config_check_sig(const void *fit, int noffset, int required_keynode, int conf_noffset, char **err_msgp) { - char * const exc_prop[] = {"data"}; + char * const exc_prop[] = {"data", "data-size", "data-position"}; const char *prop, *end, *name; struct image_sign_info info; const uint32_t *strings; From 9297e366d6a847f7ac64f4ec7102b236d8ebe1f4 Mon Sep 17 00:00:00 2001 From: Marek Bykowski Date: Wed, 29 Apr 2020 18:23:07 +0200 Subject: [PATCH 114/237] malloc: dlmalloc: add an ability for the malloc to be re-init/init multiple times Malloc gets initialized with a call to mem_malloc_init() with the address the allocation starts to and its size. Currently it is not possible to move the malloc from one memory area to another as the malloc would eventually fail. This patch adds in the ability to re-init the malloc with the updated start address and the size. One of the use cases of this feature is SPL U-Boot running from within the static memory and calling to malloc init from within board_init_f(): arch/arm/cpu/armv8/start.S:reset vector arch/arm/cpu/armv8/start.S:main() arch/arm/lib/crt0_64.S:board_init_f() board//common/spl.c:board_init_f() board//common/spl.c:mem_malloc_init((ulong)CONFIG_SYS_SPL_MALLOC_START, CONFIG_SYS_SPL_MALLOC_SIZE); Shortly after the DDR (main) memory is init and ready we call to malloc init again but this time with the start address in the DDR memory and a much greater size for moving the allocation off the static to the DDR memory: board//common/spl.c:mem_malloc_init((ulong)CONFIG_SPL_MALLOC_OFFSET, CONFIG_SPL_MALLOC_SIZE); Where CONFIG_SYS_SPL_MALLOC_START and CONFIG_SPL_MALLOC_OFFSET are the start addresses of the malloc in the static and DDR memories respectively and CONFIG_SYS_SPL_MALLOC_SIZE=SZ_16K and CONFIG_SPL_MALLOC_SIZE=SZ_2M are the sizes of the mallocs in these memories. Note, now we have a much greater memory, enlarging from 16K to 2M, available for allocation. There is an alternative approach already existing in U-Boot with the use of an early (simplified) malloc and the proper (dlamalloc) malloc however necessitating managing the two mallocs whereas this approach proposes using a single dlmalloc. Signed-off-by: Marek Bykowski --- Kconfig | 14 ++++++++++++++ common/dlmalloc.c | 41 ++++++++++++++++++++++++++++++++++++++--- 2 files changed, 52 insertions(+), 3 deletions(-) diff --git a/Kconfig b/Kconfig index 9a5e6007538..15f1a75c61a 100644 --- a/Kconfig +++ b/Kconfig @@ -209,6 +209,20 @@ if EXPERT When disabling this, please check if malloc calls, maybe should be replaced by calloc - if one expects zeroed memory. +config SYS_MALLOC_DEFAULT_TO_INIT + bool "Default malloc to init while reserving the memory for it" + default n + help + It may happen that one needs to move the dynamic allocation + from one to another memory range, eg. when moving the malloc + from the limited static to a potentially large dynamic (DDR) + memory. + + If so then on top of setting the updated memory aside one + needs to bring the malloc init. + + If such a scenario is sought choose yes. + config TOOLS_DEBUG bool "Enable debug information for tools" help diff --git a/common/dlmalloc.c b/common/dlmalloc.c index db5ab55ed33..e8f07f14f93 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -280,6 +280,7 @@ nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | Unused space (may be 0 bytes long) . . . . | + nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ `foot:' | Size of chunk, in bytes | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ @@ -574,6 +575,10 @@ static void malloc_bin_reloc(void) static inline void malloc_bin_reloc(void) {} #endif +#ifdef CONFIG_SYS_MALLOC_DEFAULT_TO_INIT +static void malloc_init(void); +#endif + ulong mem_malloc_start = 0; ulong mem_malloc_end = 0; ulong mem_malloc_brk = 0; @@ -604,6 +609,10 @@ void mem_malloc_init(ulong start, ulong size) mem_malloc_end = start + size; mem_malloc_brk = start; +#ifdef CONFIG_SYS_MALLOC_DEFAULT_TO_INIT + malloc_init(); +#endif + debug("using memory %#lx-%#lx for malloc()\n", mem_malloc_start, mem_malloc_end); #ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT @@ -708,7 +717,36 @@ static unsigned int max_n_mmaps = 0; static unsigned long max_mmapped_mem = 0; #endif +#ifdef CONFIG_SYS_MALLOC_DEFAULT_TO_INIT +static void malloc_init(void) +{ + int i, j; + debug("bins (av_ array) are at %p\n", (void *)av_); + + av_[0] = NULL; av_[1] = NULL; + for (i = 2, j = 2; i < NAV * 2 + 2; i += 2, j++) { + av_[i] = bin_at(j - 2); + av_[i + 1] = bin_at(j - 2); + + /* Just print the first few bins so that + * we can see there are alright. + */ + if (i < 10) + debug("av_[%d]=%lx av_[%d]=%lx\n", + i, (ulong)av_[i], + i + 1, (ulong)av_[i + 1]); + } + + /* Init the static bookkeeping as well */ + sbrk_base = (char *)(-1); + max_sbrked_mem = 0; + max_total_mem = 0; +#ifdef DEBUG + memset((void *)¤t_mallinfo, 0, sizeof(struct mallinfo)); +#endif +} +#endif /* Debugging support @@ -1051,9 +1089,6 @@ static mchunkptr mremap_chunk(p, new_size) mchunkptr p; size_t new_size; #endif /* HAVE_MMAP */ - - - /* Extend the top-most chunk by obtaining memory from system. Main interface to sbrk (but see also malloc_trim). From 5cf9e3b237f24e66ff1a657e954ffe3dc92e09eb Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Mon, 20 Apr 2020 10:31:44 +0300 Subject: [PATCH 115/237] common/board_r: arm: Merge initr_enable_interrupts into interrupts_init initr_enable_interrupts() is an ARM-specific wrapper over enable_interrupts(), which is run during the common init sequence. It can be eliminated by moving the enable_interrupts() call to the end of interrupt_init() function, in arch/arm/lib/interrupts*.c. Signed-off-by: Ovidiu Panait Reviewed-by: Simon Glass --- arch/arm/lib/interrupts.c | 2 ++ arch/arm/lib/interrupts_64.c | 2 ++ arch/arm/lib/interrupts_m.c | 2 ++ common/board_r.c | 12 ------------ 4 files changed, 6 insertions(+), 12 deletions(-) diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c index 6dbf03b00cd..36299d6e543 100644 --- a/arch/arm/lib/interrupts.c +++ b/arch/arm/lib/interrupts.c @@ -34,6 +34,8 @@ int interrupt_init(void) */ IRQ_STACK_START_IN = gd->irq_sp + 8; + enable_interrupts(); + return 0; } diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c index dffdf57aa20..a2df7cf193c 100644 --- a/arch/arm/lib/interrupts_64.c +++ b/arch/arm/lib/interrupts_64.c @@ -13,6 +13,8 @@ DECLARE_GLOBAL_DATA_PTR; int interrupt_init(void) { + enable_interrupts(); + return 0; } diff --git a/arch/arm/lib/interrupts_m.c b/arch/arm/lib/interrupts_m.c index 1f6fdf2995d..2ae1c5ba76c 100644 --- a/arch/arm/lib/interrupts_m.c +++ b/arch/arm/lib/interrupts_m.c @@ -31,6 +31,8 @@ struct autosave_regs { int interrupt_init(void) { + enable_interrupts(); + return 0; } diff --git a/common/board_r.c b/common/board_r.c index 0bbeaa7594c..bdb0389e31a 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -518,15 +518,6 @@ static int initr_api(void) } #endif -/* enable exceptions */ -#ifdef CONFIG_ARM -static int initr_enable_interrupts(void) -{ - enable_interrupts(); - return 0; -} -#endif - #ifdef CONFIG_CMD_NET static int initr_ethaddr(void) { @@ -813,9 +804,6 @@ static init_fnc_t init_sequence_r[] = { initr_kgdb, #endif interrupt_init, -#ifdef CONFIG_ARM - initr_enable_interrupts, -#endif #if defined(CONFIG_MICROBLAZE) || defined(CONFIG_M68K) timer_init, /* initialize timer */ #endif From 5fb292f20f0d28bf916b4e480c9ab4a24713116c Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Mon, 20 Apr 2020 10:31:45 +0300 Subject: [PATCH 116/237] cmd/bedbug.c: Make bedbug_init have a return value Do this as a preparation for removing initr_bedbug wrapper from common/board_r.c. Signed-off-by: Ovidiu Panait Reviewed-by: Simon Glass --- cmd/bedbug.c | 4 ++-- include/bedbug/type.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/cmd/bedbug.c b/cmd/bedbug.c index 9fee5288301..d3e31212eab 100644 --- a/cmd/bedbug.c +++ b/cmd/bedbug.c @@ -44,10 +44,10 @@ int bedbug_puts (const char *str) * settings. * ====================================================================== */ -void bedbug_init (void) +int bedbug_init(void) { /* -------------------------------------------------- */ - return; + return 0; } /* bedbug_init */ diff --git a/include/bedbug/type.h b/include/bedbug/type.h index b7b447b1fe3..3754c7f2b2a 100644 --- a/include/bedbug/type.h +++ b/include/bedbug/type.h @@ -3,7 +3,7 @@ /* Supporting routines */ int bedbug_puts (const char *); -void bedbug_init (void); +int bedbug_init(void); void bedbug860_init (void); void do_bedbug_breakpoint (struct pt_regs *); void bedbug_main_loop (unsigned long, struct pt_regs *); From 1a4c077b751475cc3a6e77d2216990feccc068dd Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Mon, 20 Apr 2020 10:31:46 +0300 Subject: [PATCH 117/237] common/board_r: Drop initr_bedbug wrapper Drop initr_bedbug wrapper and call bedbug_init directly during the init sequence. Signed-off-by: Ovidiu Panait Reviewed-by: Simon Glass --- common/board_r.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/common/board_r.c b/common/board_r.c index bdb0389e31a..d9015cd0579 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -637,15 +637,6 @@ int initr_mem(void) } #endif -#ifdef CONFIG_CMD_BEDBUG -static int initr_bedbug(void) -{ - bedbug_init(); - - return 0; -} -#endif - static int run_main_loop(void) { #ifdef CONFIG_SANDBOX @@ -848,7 +839,7 @@ static init_fnc_t init_sequence_r[] = { #endif #ifdef CONFIG_CMD_BEDBUG INIT_FUNC_WATCHDOG_RESET - initr_bedbug, + bedbug_init, #endif #if defined(CONFIG_PRAM) initr_mem, From 36c2f020f2b633bdc6c75f4f836bbef900b8b78c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 1 May 2020 10:52:11 -0400 Subject: [PATCH 118/237] actions: Fix syntax for enabling SYS_RELOC_GD_ENV_ADDR The correct syntax is 'select SYS_...' and not 'select CONFIG_SYS...' Fixes: d5c819b885c2 ("actions: Move defconfig options to Kconfig") Signed-off-by: Tom Rini --- arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8b6c6a2965c..b494bcae954 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -909,7 +909,7 @@ config ARCH_OWL select CLK select CLK_OWL select OF_CONTROL - select CONFIG_SYS_RELOC_GD_ENV_ADDR + select SYS_RELOC_GD_ENV_ADDR imply CMD_DM config ARCH_QEMU From 14b7004532a41cbb2dc82cc1a5687e8e88e1ba0d Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Fri, 1 May 2020 22:06:17 +0200 Subject: [PATCH 119/237] .readthedocs.yml: fix type docs/ Out documentation directory is doc/ and not docs/. Signed-off-by: Heinrich Schuchardt --- .readthedocs.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.readthedocs.yml b/.readthedocs.yml index f3fb5ed51ba..44949ea239d 100644 --- a/.readthedocs.yml +++ b/.readthedocs.yml @@ -7,7 +7,7 @@ version: 2 # Build documentation in the docs/ directory with Sphinx sphinx: - configuration: docs/conf.py + configuration: doc/conf.py # Optionally build your docs in additional formats such as PDF and ePub formats: [] From 89b84b85e9c5d80e1b5eb5b52cc6596ba32135c7 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Sat, 2 May 2020 11:35:09 +0200 Subject: [PATCH 120/237] dm: core: Add function to get child count of ofnode or device This patch add function used to get the child count of a ofnode or a device Signed-off-by: Chunfeng Yun Signed-off-by: Frank Wunderlich Reviewed-by: Weijie Gao Reviewed-by: Simon Glass --- drivers/core/ofnode.c | 11 +++++++++++ drivers/core/read.c | 5 +++++ include/dm/ofnode.h | 8 ++++++++ include/dm/read.h | 13 +++++++++++++ 4 files changed, 37 insertions(+) diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 20871a68155..e3c42dae5c6 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -474,6 +474,17 @@ ofnode ofnode_get_chosen_node(const char *name) return ofnode_path(prop); } +int ofnode_get_child_count(ofnode parent) +{ + ofnode child; + int num = 0; + + ofnode_for_each_subnode(child, parent) + num++; + + return num; +} + static int decode_timing_property(ofnode node, const char *name, struct timing_entry *result) { diff --git a/drivers/core/read.c b/drivers/core/read.c index 47b8e034465..3d421f7a69c 100644 --- a/drivers/core/read.c +++ b/drivers/core/read.c @@ -352,3 +352,8 @@ fdt_addr_t dev_read_addr_pci(const struct udevice *dev) return addr; } + +int dev_get_child_count(const struct udevice *dev) +{ + return ofnode_get_child_count(dev_ofnode(dev)); +} diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 618fc10390e..a0d3df77868 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -879,6 +879,14 @@ ofnode ofnode_by_prop_value(ofnode from, const char *propname, ofnode_valid(node); \ node = ofnode_next_subnode(node)) +/** + * ofnode_get_child_count() - get the child count of a ofnode + * + * @node: valid node to get its child count + * @return the number of subnodes + */ +int ofnode_get_child_count(ofnode parent); + /** * ofnode_translate_address() - Translate a device-tree address * diff --git a/include/dm/read.h b/include/dm/read.h index 03c15b85506..b952551d555 100644 --- a/include/dm/read.h +++ b/include/dm/read.h @@ -669,6 +669,14 @@ u64 dev_translate_dma_address(const struct udevice *dev, */ int dev_read_alias_highest_id(const char *stem); +/** + * dev_get_child_count() - get the child count of a device + * + * @dev: device to use for interation (struct udevice *) + * @return the count of child subnode + */ +int dev_get_child_count(const struct udevice *dev); + #else /* CONFIG_DM_DEV_READ_INLINE is enabled */ static inline int dev_read_u32(const struct udevice *dev, @@ -978,6 +986,11 @@ static inline int dev_read_alias_highest_id(const char *stem) return fdtdec_get_alias_highest_id(gd->fdt_blob, stem); } +static inline int dev_get_child_count(const struct udevice *dev) +{ + return ofnode_get_child_count(dev_ofnode(dev)); +} + #endif /* CONFIG_DM_DEV_READ_INLINE */ /** From bf6ad91629d05c58c99d0cd763f865ae0670102a Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Sat, 2 May 2020 11:35:10 +0200 Subject: [PATCH 121/237] test: dm: add test item for ofnode_get_child_count() Add a test item for ofnode_get_child_count() Signed-off-by: Chunfeng Yun Signed-off-by: Frank Wunderlich Reviewed-by: Simon Glass Reviewed-by: Weijie Gao --- arch/sandbox/dts/test.dts | 18 ++++++++++++++++++ test/dm/ofnode.c | 21 +++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 4bccfbe6e1b..9c00e945010 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -218,6 +218,24 @@ compatible = "denx,u-boot-fdt-test1"; }; + i-test { + compatible = "mediatek,u-boot-fdt-test"; + #address-cells = <1>; + #size-cells = <0>; + + subnode@0 { + reg = <0>; + }; + + subnode@1 { + reg = <1>; + }; + + subnode@2 { + reg = <2>; + }; + }; + devres-test { compatible = "denx,u-boot-devres-test"; }; diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c index 1c49eaf38bf..07d5c7d7a65 100644 --- a/test/dm/ofnode.c +++ b/test/dm/ofnode.c @@ -113,3 +113,24 @@ static int dm_test_ofnode_read_chosen(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_ofnode_read_chosen, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +static int dm_test_ofnode_get_child_count(struct unit_test_state *uts) +{ + ofnode node, child_node; + u32 val; + + node = ofnode_path("/i-test"); + ut_assert(ofnode_valid(node)); + + val = ofnode_get_child_count(node); + ut_asserteq(3, val); + + child_node = ofnode_first_subnode(node); + ut_assert(ofnode_valid(child_node)); + val = ofnode_get_child_count(child_node); + ut_asserteq(0, val); + + return 0; +} +DM_TEST(dm_test_ofnode_get_child_count, + DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); From b13307b470f4fdfad42aa4c1adcaf1960837d0c4 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Sat, 2 May 2020 11:35:11 +0200 Subject: [PATCH 122/237] phy: Add API for a bulk of phys This patch adds a "bulk" API to the phy API in order to get/init/exit/power on/off a group of phys associated with a device. The bulk API will avoid adding a copy of the same code to manage a group of phys in drivers. Signed-off-by: Chunfeng Yun Signed-off-by: Frank Wunderlich Reviewed-by: Weijie Gao Reviewed-by: Jagan Teki --- drivers/phy/phy-uclass.c | 97 ++++++++++++++++++++++++++++++++++++++++ include/generic-phy.h | 92 +++++++++++++++++++++++++++++++++++++ 2 files changed, 189 insertions(+) diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c index e463b0b400e..6ab78448af3 100644 --- a/drivers/phy/phy-uclass.c +++ b/drivers/phy/phy-uclass.c @@ -6,6 +6,7 @@ #include #include +#include #include static inline struct phy_ops *phy_dev_ops(struct udevice *dev) @@ -167,6 +168,102 @@ int generic_phy_power_off(struct phy *phy) return ops->power_off ? ops->power_off(phy) : 0; } +int generic_phy_get_bulk(struct udevice *dev, struct phy_bulk *bulk) +{ + int i, ret, count; + + bulk->count = 0; + + /* Return if no phy declared */ + if (!dev_read_prop(dev, "phys", NULL)) + return 0; + + count = dev_count_phandle_with_args(dev, "phys", "#phy-cells"); + if (count < 1) + return count; + + bulk->phys = devm_kcalloc(dev, count, sizeof(struct phy), GFP_KERNEL); + if (!bulk->phys) + return -ENOMEM; + + for (i = 0; i < count; i++) { + ret = generic_phy_get_by_index(dev, i, &bulk->phys[i]); + if (ret) { + pr_err("Failed to get PHY%d for %s\n", i, dev->name); + return ret; + } + bulk->count++; + } + + return 0; +} + +int generic_phy_init_bulk(struct phy_bulk *bulk) +{ + struct phy *phys = bulk->phys; + int i, ret; + + for (i = 0; i < bulk->count; i++) { + ret = generic_phy_init(&phys[i]); + if (ret) { + pr_err("Can't init PHY%d\n", i); + goto phys_init_err; + } + } + + return 0; + +phys_init_err: + for (; i > 0; i--) + generic_phy_exit(&phys[i - 1]); + + return ret; +} + +int generic_phy_exit_bulk(struct phy_bulk *bulk) +{ + struct phy *phys = bulk->phys; + int i, ret = 0; + + for (i = 0; i < bulk->count; i++) + ret |= generic_phy_exit(&phys[i]); + + return ret; +} + +int generic_phy_power_on_bulk(struct phy_bulk *bulk) +{ + struct phy *phys = bulk->phys; + int i, ret; + + for (i = 0; i < bulk->count; i++) { + ret = generic_phy_power_on(&phys[i]); + if (ret) { + pr_err("Can't power on PHY%d\n", i); + goto phys_poweron_err; + } + } + + return 0; + +phys_poweron_err: + for (; i > 0; i--) + generic_phy_power_off(&phys[i - 1]); + + return ret; +} + +int generic_phy_power_off_bulk(struct phy_bulk *bulk) +{ + struct phy *phys = bulk->phys; + int i, ret = 0; + + for (i = 0; i < bulk->count; i++) + ret |= generic_phy_power_off(&phys[i]); + + return ret; +} + UCLASS_DRIVER(phy) = { .id = UCLASS_PHY, .name = "phy", diff --git a/include/generic-phy.h b/include/generic-phy.h index 73537025c2c..55629ae0b41 100644 --- a/include/generic-phy.h +++ b/include/generic-phy.h @@ -124,6 +124,23 @@ struct phy_ops { int (*power_off)(struct phy *phy); }; +/** + * struct phy_bulk - A handle to (allowing control of) a bulk of phys. + * + * Consumers provide storage for the phy bulk. The content of the structure is + * managed solely by the phy API. A phy bulk struct is initialized + * by "get"ing the phy bulk struct. + * The phy bulk struct is passed to all other bulk phy APIs to apply + * the API to all the phy in the bulk struct. + * + * @phys: An array of phy handles. + * @count: The number of phy handles in the phys array. + */ +struct phy_bulk { + struct phy *phys; + unsigned int count; +}; + #ifdef CONFIG_PHY /** @@ -250,6 +267,55 @@ int generic_phy_get_by_node(ofnode node, int index, struct phy *phy); int generic_phy_get_by_name(struct udevice *user, const char *phy_name, struct phy *phy); +/** + * generic_phy_get_bulk - Get all phys of a device. + * + * This looks up and gets all phys of the consumer device; each device is + * assumed to have n phys associated with it somehow, and this function finds + * and gets all of them in a separate structure. + * + * @dev: The consumer device. + * @bulk A pointer to a phy bulk struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int generic_phy_get_bulk(struct udevice *dev, struct phy_bulk *bulk); + +/** + * generic_phy_init_bulk() - Initialize all phys in a phy bulk struct. + * + * @bulk: A phy bulk struct that was previously successfully requested + * by generic_phy_get_bulk(). + * @return 0 if OK, or negative error code. + */ +int generic_phy_init_bulk(struct phy_bulk *bulk); + +/** + * generic_phy_exit_bulk() - de-initialize all phys in a phy bulk struct. + * + * @bulk: A phy bulk struct that was previously successfully requested + * by generic_phy_get_bulk(). + * @return 0 if OK, or negative error code. + */ +int generic_phy_exit_bulk(struct phy_bulk *bulk); + +/** + * generic_phy_power_on_bulk() - Power on all phys in a phy bulk struct. + * + * @bulk: A phy bulk struct that was previously successfully requested + * by generic_phy_get_bulk(). + * @return 0 if OK, or negative error code. + */ +int generic_phy_power_on_bulk(struct phy_bulk *bulk); + +/** + * generic_phy_power_off_bulk() - Power off all phys in a phy bulk struct. + * + * @bulk: A phy bulk struct that was previously successfully requested + * by generic_phy_get_bulk(). + * @return 0 if OK, or negative error code. + */ +int generic_phy_power_off_bulk(struct phy_bulk *bulk); + #else /* CONFIG_PHY */ static inline int generic_phy_init(struct phy *phy) @@ -289,6 +355,32 @@ static inline int generic_phy_get_by_name(struct udevice *user, const char *phy_ return 0; } +static inline int +generic_phy_get_bulk(struct udevice *dev, struct phy_bulk *bulk) +{ + return 0; +} + +static inline int generic_phy_init_bulk(struct phy_bulk *bulk) +{ + return 0; +} + +static inline int generic_phy_exit_bulk(struct phy_bulk *bulk) +{ + return 0; +} + +static inline int generic_phy_power_on_bulk(struct phy_bulk *bulk) +{ + return 0; +} + +static inline int generic_phy_power_off_bulk(struct phy_bulk *bulk) +{ + return 0; +} + #endif /* CONFIG_PHY */ /** From 00c82acfe9aadaa624699e4579dace583f944449 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Sat, 2 May 2020 11:35:12 +0200 Subject: [PATCH 123/237] test: dm: phy: add a test item for the phy_bulk API Add a test item for the phy_bulk API Signed-off-by: Chunfeng Yun Signed-off-by: Frank Wunderlich Reviewed-by: Weijie Gao Reviewed-by: Simon Glass Reviewed-by: Jagan Teki --- arch/sandbox/dts/test.dts | 11 +++++++++++ test/dm/phy.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 9c00e945010..15cd2330a38 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -159,12 +159,23 @@ broken; }; + phy_provider2: gen_phy@2 { + compatible = "sandbox,phy"; + #phy-cells = <0>; + }; + gen_phy_user: gen_phy_user { compatible = "simple-bus"; phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>; phy-names = "phy1", "phy2", "phy3"; }; + gen_phy_user1: gen_phy_user1 { + compatible = "simple-bus"; + phys = <&phy_provider0 0>, <&phy_provider2>; + phy-names = "phy1", "phy2"; + }; + some-bus { #address-cells = <1>; #size-cells = <0>; diff --git a/test/dm/phy.c b/test/dm/phy.c index 21d92194b97..92455d94aff 100644 --- a/test/dm/phy.c +++ b/test/dm/phy.c @@ -110,3 +110,36 @@ static int dm_test_phy_ops(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_phy_ops, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +static int dm_test_phy_bulk(struct unit_test_state *uts) +{ + struct phy_bulk phys; + struct udevice *parent; + + /* test normal operations */ + ut_assertok(uclass_get_device_by_name(UCLASS_SIMPLE_BUS, + "gen_phy_user1", &parent)); + + ut_assertok(generic_phy_get_bulk(parent, &phys)); + ut_asserteq(2, phys.count); + + ut_asserteq(0, generic_phy_init_bulk(&phys)); + ut_asserteq(0, generic_phy_power_on_bulk(&phys)); + ut_asserteq(0, generic_phy_power_off_bulk(&phys)); + ut_asserteq(0, generic_phy_exit_bulk(&phys)); + + /* has a known problem phy */ + ut_assertok(uclass_get_device_by_name(UCLASS_SIMPLE_BUS, + "gen_phy_user", &parent)); + + ut_assertok(generic_phy_get_bulk(parent, &phys)); + ut_asserteq(3, phys.count); + + ut_asserteq(0, generic_phy_init_bulk(&phys)); + ut_asserteq(-EIO, generic_phy_power_on_bulk(&phys)); + ut_asserteq(-EIO, generic_phy_power_off_bulk(&phys)); + ut_asserteq(0, generic_phy_exit_bulk(&phys)); + + return 0; +} +DM_TEST(dm_test_phy_bulk, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); From 6dfb8a8052ee024fd20150b558477ab5c3e6f0f9 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Sat, 2 May 2020 11:35:13 +0200 Subject: [PATCH 124/237] usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun Signed-off-by: Frank Wunderlich Reviewed-by: Weijie Gao --- drivers/usb/dwc3/core.c | 87 ++++++--------------------------- drivers/usb/dwc3/dwc3-generic.c | 7 ++- drivers/usb/host/xhci-dwc3.c | 7 ++- include/dwc3-uboot.h | 11 ++--- 4 files changed, 27 insertions(+), 85 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 4ec3f6df6a9..a8982bdc094 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -838,87 +838,32 @@ MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB) -int dwc3_setup_phy(struct udevice *dev, struct phy **array, int *num_phys) +int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys) { - int i, ret, count; - struct phy *usb_phys; + int ret; - /* Return if no phy declared */ - if (!dev_read_prop(dev, "phys", NULL)) - return 0; - count = dev_count_phandle_with_args(dev, "phys", "#phy-cells"); - if (count <= 0) - return count; + ret = generic_phy_get_bulk(dev, phys); + if (ret) + return ret; - usb_phys = devm_kcalloc(dev, count, sizeof(struct phy), - GFP_KERNEL); - if (!usb_phys) - return -ENOMEM; + ret = generic_phy_init_bulk(phys); + if (ret) + return ret; - for (i = 0; i < count; i++) { - ret = generic_phy_get_by_index(dev, i, &usb_phys[i]); - if (ret && ret != -ENOENT) { - pr_err("Failed to get USB PHY%d for %s\n", - i, dev->name); - return ret; - } - } - - for (i = 0; i < count; i++) { - ret = generic_phy_init(&usb_phys[i]); - if (ret) { - pr_err("Can't init USB PHY%d for %s\n", - i, dev->name); - goto phys_init_err; - } - } - - for (i = 0; i < count; i++) { - ret = generic_phy_power_on(&usb_phys[i]); - if (ret) { - pr_err("Can't power USB PHY%d for %s\n", - i, dev->name); - goto phys_poweron_err; - } - } - - *array = usb_phys; - *num_phys = count; - return 0; - -phys_poweron_err: - for (i = count - 1; i >= 0; i--) - generic_phy_power_off(&usb_phys[i]); - - for (i = 0; i < count; i++) - generic_phy_exit(&usb_phys[i]); - - return ret; - -phys_init_err: - for (; i >= 0; i--) - generic_phy_exit(&usb_phys[i]); + ret = generic_phy_power_on_bulk(phys); + if (ret) + generic_phy_exit_bulk(phys); return ret; } -int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, int num_phys) +int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys) { - int i, ret; + int ret; - for (i = 0; i < num_phys; i++) { - if (!generic_phy_valid(&usb_phys[i])) - continue; - - ret = generic_phy_power_off(&usb_phys[i]); - ret |= generic_phy_exit(&usb_phys[i]); - if (ret) { - pr_err("Can't shutdown USB PHY%d for %s\n", - i, dev->name); - } - } - - return 0; + ret = generic_phy_power_off_bulk(phys); + ret |= generic_phy_exit_bulk(phys); + return ret; } #endif diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index febcfc0f54c..eabd53a36dc 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -33,8 +33,7 @@ struct dwc3_generic_plat { struct dwc3_generic_priv { void *base; struct dwc3 dwc3; - struct phy *phys; - int num_phys; + struct phy_bulk phys; }; struct dwc3_generic_host_priv { @@ -56,7 +55,7 @@ static int dwc3_generic_probe(struct udevice *dev, dwc3_of_parse(dwc3); #endif - rc = dwc3_setup_phy(dev, &priv->phys, &priv->num_phys); + rc = dwc3_setup_phy(dev, &priv->phys); if (rc) return rc; @@ -79,7 +78,7 @@ static int dwc3_generic_remove(struct udevice *dev, struct dwc3 *dwc3 = &priv->dwc3; dwc3_remove(dwc3); - dwc3_shutdown_phy(dev, priv->phys, priv->num_phys); + dwc3_shutdown_phy(dev, &priv->phys); unmap_physmem(dwc3->regs, MAP_NOCACHE); return 0; diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index 9fcfa39d4b5..563db1a4260 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -19,8 +19,7 @@ #include struct xhci_dwc3_platdata { - struct phy *usb_phys; - int num_phys; + struct phy_bulk *usb_phys; }; void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) @@ -125,7 +124,7 @@ static int xhci_dwc3_probe(struct udevice *dev) hcor = (struct xhci_hcor *)((uintptr_t)hccr + HC_LENGTH(xhci_readl(&(hccr)->cr_capbase))); - ret = dwc3_setup_phy(dev, &plat->usb_phys, &plat->num_phys); + ret = dwc3_setup_phy(dev, plat->usb_phys); if (ret && (ret != -ENOTSUPP)) return ret; @@ -168,7 +167,7 @@ static int xhci_dwc3_remove(struct udevice *dev) { struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); - dwc3_shutdown_phy(dev, plat->usb_phys, plat->num_phys); + dwc3_shutdown_phy(dev, plat->usb_phys); return xhci_deregister(dev); } diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h index 3c9e204cf07..ce835fd1b2b 100644 --- a/include/dwc3-uboot.h +++ b/include/dwc3-uboot.h @@ -9,6 +9,7 @@ #ifndef __DWC3_UBOOT_H_ #define __DWC3_UBOOT_H_ +#include #include #include @@ -43,17 +44,15 @@ void dwc3_uboot_handle_interrupt(int index); struct phy; #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB) -int dwc3_setup_phy(struct udevice *dev, struct phy **array, int *num_phys); -int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, int num_phys); +int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys); +int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys); #else -static inline int dwc3_setup_phy(struct udevice *dev, struct phy **array, - int *num_phys) +static inline int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys) { return -ENOTSUPP; } -static inline int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, - int num_phys) +static inline int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys) { return -ENOTSUPP; } From cf67e451790aca04a969265495bb2a3ca1cbf47a Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Sat, 2 May 2020 11:35:14 +0200 Subject: [PATCH 125/237] usb: dwc2_udc_otg: use the phy bulk API to get phys Use the phy bulk API to get a group of phys Signed-off-by: Chunfeng Yun Signed-off-by: Frank Wunderlich Reviewed-by: Weijie Gao --- drivers/usb/gadget/dwc2_udc_otg.c | 93 ++++++------------------------- 1 file changed, 17 insertions(+), 76 deletions(-) diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c index b9c814cf73e..9f21af2923d 100644 --- a/drivers/usb/gadget/dwc2_udc_otg.c +++ b/drivers/usb/gadget/dwc2_udc_otg.c @@ -943,8 +943,7 @@ int usb_gadget_handle_interrupts(int index) struct dwc2_priv_data { struct clk_bulk clks; struct reset_ctl_bulk resets; - struct phy *phys; - int num_phys; + struct phy_bulk phys; struct udevice *usb33d_supply; }; @@ -953,87 +952,29 @@ int dm_usb_gadget_handle_interrupts(struct udevice *dev) return dwc2_udc_handle_interrupt(); } -int dwc2_phy_setup(struct udevice *dev, struct phy **array, int *num_phys) +static int dwc2_phy_setup(struct udevice *dev, struct phy_bulk *phys) { - int i, ret, count; - struct phy *usb_phys; + int ret; - /* Return if no phy declared */ - if (!dev_read_prop(dev, "phys", NULL)) - return 0; + ret = generic_phy_get_bulk(dev, phys); + if (ret) + return ret; - count = dev_count_phandle_with_args(dev, "phys", "#phy-cells"); - if (count <= 0) - return count; + ret = generic_phy_init_bulk(phys); + if (ret) + return ret; - usb_phys = devm_kcalloc(dev, count, sizeof(struct phy), - GFP_KERNEL); - if (!usb_phys) - return -ENOMEM; - - for (i = 0; i < count; i++) { - ret = generic_phy_get_by_index(dev, i, &usb_phys[i]); - if (ret && ret != -ENOENT) { - dev_err(dev, "Failed to get USB PHY%d for %s\n", - i, dev->name); - return ret; - } - } - - for (i = 0; i < count; i++) { - ret = generic_phy_init(&usb_phys[i]); - if (ret) { - dev_err(dev, "Can't init USB PHY%d for %s\n", - i, dev->name); - goto phys_init_err; - } - } - - for (i = 0; i < count; i++) { - ret = generic_phy_power_on(&usb_phys[i]); - if (ret) { - dev_err(dev, "Can't power USB PHY%d for %s\n", - i, dev->name); - goto phys_poweron_err; - } - } - - *array = usb_phys; - *num_phys = count; - - return 0; - -phys_poweron_err: - for (i = count - 1; i >= 0; i--) - generic_phy_power_off(&usb_phys[i]); - - for (i = 0; i < count; i++) - generic_phy_exit(&usb_phys[i]); - - return ret; - -phys_init_err: - for (; i >= 0; i--) - generic_phy_exit(&usb_phys[i]); + ret = generic_phy_power_on_bulk(phys); + if (ret) + generic_phy_exit_bulk(phys); return ret; } -void dwc2_phy_shutdown(struct udevice *dev, struct phy *usb_phys, int num_phys) +static void dwc2_phy_shutdown(struct udevice *dev, struct phy_bulk *phys) { - int i, ret; - - for (i = 0; i < num_phys; i++) { - if (!generic_phy_valid(&usb_phys[i])) - continue; - - ret = generic_phy_power_off(&usb_phys[i]); - ret |= generic_phy_exit(&usb_phys[i]); - if (ret) { - dev_err(dev, "Can't shutdown USB PHY%d for %s\n", - i, dev->name); - } - } + generic_phy_power_off_bulk(phys); + generic_phy_exit_bulk(phys); } static int dwc2_udc_otg_ofdata_to_platdata(struct udevice *dev) @@ -1158,7 +1099,7 @@ static int dwc2_udc_otg_probe(struct udevice *dev) if (ret) return ret; - ret = dwc2_phy_setup(dev, &priv->phys, &priv->num_phys); + ret = dwc2_phy_setup(dev, &priv->phys); if (ret) return ret; @@ -1208,7 +1149,7 @@ static int dwc2_udc_otg_remove(struct udevice *dev) clk_release_bulk(&priv->clks); - dwc2_phy_shutdown(dev, priv->phys, priv->num_phys); + dwc2_phy_shutdown(dev, &priv->phys); return dm_scan_fdt_dev(dev); } From ee6eabbedda47b4cff68861e34c21d992a4586e2 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Sat, 2 May 2020 11:35:15 +0200 Subject: [PATCH 126/237] phy: phy-mtk-tphy: add support USB phys Support USB2 and USB3 PHY with shared banks when support multi-phys Signed-off-by: Chunfeng Yun Signed-off-by: Frank Wunderlich Reviewed-by: Weijie Gao --- drivers/phy/phy-mtk-tphy.c | 227 +++++++++++++++++++++++++++++++++++-- 1 file changed, 218 insertions(+), 9 deletions(-) diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c index bd089b7a435..71bc706c6e9 100644 --- a/drivers/phy/phy-mtk-tphy.c +++ b/drivers/phy/phy-mtk-tphy.c @@ -20,11 +20,66 @@ /* version V1 sub-banks offset base address */ /* banks shared by multiple phys */ #define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */ +#define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */ #define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */ +/* u2 phy bank */ +#define SSUSB_SIFSLV_V1_U2PHY_COM 0x000 /* u3/pcie/sata phy banks */ #define SSUSB_SIFSLV_V1_U3PHYD 0x000 #define SSUSB_SIFSLV_V1_U3PHYA 0x200 +#define U3P_USBPHYACR0 0x000 +#define PA0_RG_U2PLL_FORCE_ON BIT(15) +#define PA0_RG_USB20_INTR_EN BIT(5) + +#define U3P_USBPHYACR5 0x014 +#define PA5_RG_U2_HSTX_SRCAL_EN BIT(15) +#define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12) +#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12) +#define PA5_RG_U2_HS_100U_U3_EN BIT(11) + +#define U3P_USBPHYACR6 0x018 +#define PA6_RG_U2_BC11_SW_EN BIT(23) +#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) +#define PA6_RG_U2_SQTH GENMASK(3, 0) +#define PA6_RG_U2_SQTH_VAL(x) (0xf & (x)) + +#define U3P_U2PHYACR4 0x020 +#define P2C_RG_USB20_GPIO_CTL BIT(9) +#define P2C_USB20_GPIO_MODE BIT(8) +#define P2C_U2_GPIO_CTR_MSK \ + (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE) + +#define U3P_U2PHYDTM0 0x068 +#define P2C_FORCE_UART_EN BIT(26) +#define P2C_FORCE_DATAIN BIT(23) +#define P2C_FORCE_DM_PULLDOWN BIT(21) +#define P2C_FORCE_DP_PULLDOWN BIT(20) +#define P2C_FORCE_XCVRSEL BIT(19) +#define P2C_FORCE_SUSPENDM BIT(18) +#define P2C_FORCE_TERMSEL BIT(17) +#define P2C_RG_DATAIN GENMASK(13, 10) +#define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10) +#define P2C_RG_DMPULLDOWN BIT(7) +#define P2C_RG_DPPULLDOWN BIT(6) +#define P2C_RG_XCVRSEL GENMASK(5, 4) +#define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4) +#define P2C_RG_SUSPENDM BIT(3) +#define P2C_RG_TERMSEL BIT(2) +#define P2C_DTM0_PART_MASK \ + (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \ + P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \ + P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \ + P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL) + +#define U3P_U2PHYDTM1 0x06C +#define P2C_RG_UART_EN BIT(16) +#define P2C_FORCE_IDDIG BIT(9) +#define P2C_RG_VBUSVALID BIT(5) +#define P2C_RG_SESSEND BIT(4) +#define P2C_RG_AVALID BIT(2) +#define P2C_RG_IDDIG BIT(1) + #define U3P_U3_CHIP_GPIO_CTLD 0x0c #define P3C_REG_IP_SW_RST BIT(31) #define P3C_MCU_BUS_CK_GATE_EN BIT(30) @@ -42,6 +97,14 @@ #define P3A_RG_CLKDRV_AMP GENMASK(31, 29) #define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29) +#define U3P_U3_PHYA_REG6 0x018 +#define P3A_RG_TX_EIDLE_CM GENMASK(31, 28) +#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28) + +#define U3P_U3_PHYA_REG9 0x024 +#define P3A_RG_RX_DAC_MUX GENMASK(5, 1) +#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1) + #define U3P_U3_PHYA_DA_REG0 0x100 #define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16) #define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16) @@ -77,6 +140,16 @@ #define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0) #define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x)) +#define U3P_U3_PHYD_LFPS1 0x00c +#define P3D_RG_FWAKE_TH GENMASK(21, 16) +#define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16) + +#define U3P_U3_PHYD_CDR1 0x05c +#define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24) +#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24) +#define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8) +#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8) + #define U3P_U3_PHYD_RXDET1 0x128 #define P3D_RG_RXDET_STB2_SET GENMASK(17, 9) #define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9) @@ -85,6 +158,16 @@ #define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0) #define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x)) +#define U3P_SPLLC_XTALCTL3 0x018 +#define XC3_RG_U3_XTAL_RX_PWD BIT(9) +#define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8) + +struct u2phy_banks { + void __iomem *misc; + void __iomem *fmreg; + void __iomem *com; +}; + struct u3phy_banks { void __iomem *spllc; void __iomem *chip; @@ -95,21 +178,127 @@ struct u3phy_banks { struct mtk_phy_instance { void __iomem *port_base; const struct device_node *np; - - struct u3phy_banks u3_banks; + union { + struct u2phy_banks u2_banks; + struct u3phy_banks u3_banks; + }; /* reference clock of anolog phy */ struct clk ref_clk; u32 index; - u8 type; + u32 type; }; struct mtk_tphy { + struct udevice *dev; void __iomem *sif_base; struct mtk_phy_instance **phys; int nphys; }; +static void u2_phy_instance_init(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u2phy_banks *u2_banks = &instance->u2_banks; + + /* switch to USB function, and enable usb pll */ + clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM0, + P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM, + P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0)); + + clrbits_le32(u2_banks->com + U3P_U2PHYDTM1, P2C_RG_UART_EN); + setbits_le32(u2_banks->com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN); + + /* disable switch 100uA current to SSUSB */ + clrbits_le32(u2_banks->com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN); + + clrbits_le32(u2_banks->com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK); + + /* DP/DM BC1.1 path Disable */ + clrsetbits_le32(u2_banks->com + U3P_USBPHYACR6, + PA6_RG_U2_BC11_SW_EN | PA6_RG_U2_SQTH, + PA6_RG_U2_SQTH_VAL(2)); + + /* set HS slew rate */ + clrsetbits_le32(u2_banks->com + U3P_USBPHYACR5, + PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4)); + + dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); +} + +static void u2_phy_instance_power_on(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u2phy_banks *u2_banks = &instance->u2_banks; + + clrbits_le32(u2_banks->com + U3P_U2PHYDTM0, + P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK); + + /* OTG Enable */ + setbits_le32(u2_banks->com + U3P_USBPHYACR6, + PA6_RG_U2_OTG_VBUSCMP_EN); + + clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1, + P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID); + + dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); +} + +static void u2_phy_instance_power_off(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u2phy_banks *u2_banks = &instance->u2_banks; + + clrbits_le32(u2_banks->com + U3P_U2PHYDTM0, + P2C_RG_XCVRSEL | P2C_RG_DATAIN); + + /* OTG Disable */ + clrbits_le32(u2_banks->com + U3P_USBPHYACR6, + PA6_RG_U2_OTG_VBUSCMP_EN); + + clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1, + P2C_RG_VBUSVALID | P2C_RG_AVALID, P2C_RG_SESSEND); + + dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); +} + +static void u3_phy_instance_init(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u3phy_banks *u3_banks = &instance->u3_banks; + + /* gating PCIe Analog XTAL clock */ + setbits_le32(u3_banks->spllc + U3P_SPLLC_XTALCTL3, + XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD); + + /* gating XSQ */ + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0, + P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2)); + + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG9, + P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4)); + + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG6, + P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe)); + + clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_CDR1, + P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1, + P3D_RG_CDR_BIR_LTD0_VAL(0xc) | + P3D_RG_CDR_BIR_LTD1_VAL(0x3)); + + clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_LFPS1, + P3D_RG_FWAKE_TH, P3D_RG_FWAKE_TH_VAL(0x34)); + + clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1, + P3D_RG_RXDET_STB2_SET, P3D_RG_RXDET_STB2_SET_VAL(0x10)); + + clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2, + P3D_RG_RXDET_STB2_SET_P3, + P3D_RG_RXDET_STB2_SET_P3_VAL(0x10)); + + dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); +} + static void pcie_phy_instance_init(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { @@ -187,9 +376,16 @@ static void pcie_phy_instance_power_off(struct mtk_tphy *tphy, static void phy_v1_banks_init(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { + struct u2phy_banks *u2_banks = &instance->u2_banks; struct u3phy_banks *u3_banks = &instance->u3_banks; switch (instance->type) { + case PHY_TYPE_USB2: + u2_banks->misc = NULL; + u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ; + u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM; + break; + case PHY_TYPE_USB3: case PHY_TYPE_PCIE: u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC; u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP; @@ -197,6 +393,7 @@ static void phy_v1_banks_init(struct mtk_tphy *tphy, u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; break; default: + dev_err(tphy->dev, "incompatible PHY type\n"); return; } } @@ -212,10 +409,17 @@ static int mtk_phy_init(struct phy *phy) return ret; switch (instance->type) { + case PHY_TYPE_USB2: + u2_phy_instance_init(tphy, instance); + break; + case PHY_TYPE_USB3: + u3_phy_instance_init(tphy, instance); + break; case PHY_TYPE_PCIE: pcie_phy_instance_init(tphy, instance); break; default: + dev_err(tphy->dev, "incompatible PHY type\n"); return -EINVAL; } @@ -227,7 +431,10 @@ static int mtk_phy_power_on(struct phy *phy) struct mtk_tphy *tphy = dev_get_priv(phy->dev); struct mtk_phy_instance *instance = tphy->phys[phy->id]; - pcie_phy_instance_power_on(tphy, instance); + if (instance->type == PHY_TYPE_USB2) + u2_phy_instance_power_on(tphy, instance); + else if (instance->type == PHY_TYPE_PCIE) + pcie_phy_instance_power_on(tphy, instance); return 0; } @@ -237,7 +444,10 @@ static int mtk_phy_power_off(struct phy *phy) struct mtk_tphy *tphy = dev_get_priv(phy->dev); struct mtk_phy_instance *instance = tphy->phys[phy->id]; - pcie_phy_instance_power_off(tphy, instance); + if (instance->type == PHY_TYPE_USB2) + u2_phy_instance_power_off(tphy, instance); + else if (instance->type == PHY_TYPE_PCIE) + pcie_phy_instance_power_off(tphy, instance); return 0; } @@ -285,8 +495,7 @@ static int mtk_phy_xlate(struct phy *phy, instance->type = args->args[1]; if (!(instance->type == PHY_TYPE_USB2 || instance->type == PHY_TYPE_USB3 || - instance->type == PHY_TYPE_PCIE || - instance->type == PHY_TYPE_SATA)) { + instance->type == PHY_TYPE_PCIE)) { dev_err(phy->dev, "unsupported device type\n"); return -EINVAL; } @@ -310,14 +519,14 @@ static int mtk_tphy_probe(struct udevice *dev) ofnode subnode; int index = 0; - dev_for_each_subnode(subnode, dev) - tphy->nphys++; + tphy->nphys = dev_get_child_count(dev); tphy->phys = devm_kcalloc(dev, tphy->nphys, sizeof(*tphy->phys), GFP_KERNEL); if (!tphy->phys) return -ENOMEM; + tphy->dev = dev; tphy->sif_base = dev_read_addr_ptr(dev); if (!tphy->sif_base) return -ENOENT; From d1ae8445adf7b84e948e9f09f728254922b7afa4 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Sat, 2 May 2020 11:35:16 +0200 Subject: [PATCH 127/237] phy: phy-mtk-tphy: add support new version The new version removes all shared banks between multi-phys Signed-off-by: Chunfeng Yun Signed-off-by: Frank Wunderlich Reviewed-by: Weijie Gao --- drivers/phy/phy-mtk-tphy.c | 68 +++++++++++++++++++++++++++++++++++--- 1 file changed, 63 insertions(+), 5 deletions(-) diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c index 71bc706c6e9..20167fe7cb9 100644 --- a/drivers/phy/phy-mtk-tphy.c +++ b/drivers/phy/phy-mtk-tphy.c @@ -28,6 +28,17 @@ #define SSUSB_SIFSLV_V1_U3PHYD 0x000 #define SSUSB_SIFSLV_V1_U3PHYA 0x200 +/* version V2 sub-banks offset base address */ +/* u2 phy banks */ +#define SSUSB_SIFSLV_V2_MISC 0x000 +#define SSUSB_SIFSLV_V2_U2FREQ 0x100 +#define SSUSB_SIFSLV_V2_U2PHY_COM 0x300 +/* u3/pcie/sata phy banks */ +#define SSUSB_SIFSLV_V2_SPLLC 0x000 +#define SSUSB_SIFSLV_V2_CHIP 0x100 +#define SSUSB_SIFSLV_V2_U3PHYD 0x200 +#define SSUSB_SIFSLV_V2_U3PHYA 0x400 + #define U3P_USBPHYACR0 0x000 #define PA0_RG_U2PLL_FORCE_ON BIT(15) #define PA0_RG_USB20_INTR_EN BIT(5) @@ -162,6 +173,11 @@ #define XC3_RG_U3_XTAL_RX_PWD BIT(9) #define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8) +enum mtk_phy_version { + MTK_TPHY_V1 = 1, + MTK_TPHY_V2, +}; + struct u2phy_banks { void __iomem *misc; void __iomem *fmreg; @@ -192,6 +208,7 @@ struct mtk_phy_instance { struct mtk_tphy { struct udevice *dev; void __iomem *sif_base; + enum mtk_phy_version version; struct mtk_phy_instance **phys; int nphys; }; @@ -304,6 +321,9 @@ static void pcie_phy_instance_init(struct mtk_tphy *tphy, { struct u3phy_banks *u3_banks = &instance->u3_banks; + if (tphy->version != MTK_TPHY_V1) + return; + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0, P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H, P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | @@ -398,6 +418,31 @@ static void phy_v1_banks_init(struct mtk_tphy *tphy, } } +static void phy_v2_banks_init(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u2phy_banks *u2_banks = &instance->u2_banks; + struct u3phy_banks *u3_banks = &instance->u3_banks; + + switch (instance->type) { + case PHY_TYPE_USB2: + u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; + u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; + u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; + break; + case PHY_TYPE_USB3: + case PHY_TYPE_PCIE: + u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; + u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; + u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; + u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA; + break; + default: + dev_err(tphy->dev, "incompatible PHY type\n"); + return; + } +} + static int mtk_phy_init(struct phy *phy) { struct mtk_tphy *tphy = dev_get_priv(phy->dev); @@ -500,7 +545,14 @@ static int mtk_phy_xlate(struct phy *phy, return -EINVAL; } - phy_v1_banks_init(tphy, instance); + if (tphy->version == MTK_TPHY_V1) { + phy_v1_banks_init(tphy, instance); + } else if (tphy->version == MTK_TPHY_V2) { + phy_v2_banks_init(tphy, instance); + } else { + dev_err(phy->dev, "phy version is not supported\n"); + return -EINVAL; + } return 0; } @@ -527,9 +579,14 @@ static int mtk_tphy_probe(struct udevice *dev) return -ENOMEM; tphy->dev = dev; - tphy->sif_base = dev_read_addr_ptr(dev); - if (!tphy->sif_base) - return -ENOENT; + tphy->version = dev_get_driver_data(dev); + + /* v1 has shared banks */ + if (tphy->version == MTK_TPHY_V1) { + tphy->sif_base = dev_read_addr_ptr(dev); + if (!tphy->sif_base) + return -ENOENT; + } dev_for_each_subnode(subnode, dev) { struct mtk_phy_instance *instance; @@ -560,7 +617,8 @@ static int mtk_tphy_probe(struct udevice *dev) } static const struct udevice_id mtk_tphy_id_table[] = { - { .compatible = "mediatek,generic-tphy-v1", }, + { .compatible = "mediatek,generic-tphy-v1", .data = MTK_TPHY_V1, }, + { .compatible = "mediatek,generic-tphy-v2", .data = MTK_TPHY_V2, }, { } }; From 4d4abbd783688f08da2e3e525d19917744d75a81 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Sat, 2 May 2020 11:35:17 +0200 Subject: [PATCH 128/237] phy: phy-mtk-tphy: add a new reference clock Usually the digital and analog phys use the same reference clock, but some platforms have two separate reference clocks for each of them, so add another optional clock to support them. In order to keep the clock names consistent with PHY IP's, change the da_ref for analog phy and ref clock for digital phy. Signed-off-by: Chunfeng Yun Signed-off-by: Frank Wunderlich Reviewed-by: Weijie Gao --- drivers/phy/phy-mtk-tphy.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c index 20167fe7cb9..81525a48b70 100644 --- a/drivers/phy/phy-mtk-tphy.c +++ b/drivers/phy/phy-mtk-tphy.c @@ -199,8 +199,8 @@ struct mtk_phy_instance { struct u3phy_banks u3_banks; }; - /* reference clock of anolog phy */ - struct clk ref_clk; + struct clk ref_clk; /* reference clock of (digital) phy */ + struct clk da_ref_clk; /* reference clock of analog phy */ u32 index; u32 type; }; @@ -450,8 +450,17 @@ static int mtk_phy_init(struct phy *phy) int ret; ret = clk_enable(&instance->ref_clk); - if (ret) + if (ret < 0) { + dev_err(tphy->dev, "failed to enable ref_clk\n"); return ret; + } + + ret = clk_enable(&instance->da_ref_clk); + if (ret < 0) { + dev_err(tphy->dev, "failed to enable da_ref_clk %d\n", ret); + clk_disable(&instance->ref_clk); + return ret; + } switch (instance->type) { case PHY_TYPE_USB2: @@ -502,6 +511,7 @@ static int mtk_phy_exit(struct phy *phy) struct mtk_tphy *tphy = dev_get_priv(phy->dev); struct mtk_phy_instance *instance = tphy->phys[phy->id]; + clk_disable(&instance->da_ref_clk); clk_disable(&instance->ref_clk); return 0; @@ -611,6 +621,11 @@ static int mtk_tphy_probe(struct udevice *dev) &instance->ref_clk); if (err) return err; + + err = clk_get_optional_nodev(subnode, "da_ref", + &instance->da_ref_clk); + if (err) + return err; } return 0; From 74102834154c2e575c14e050a62f63e2e52f96de Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Sat, 2 May 2020 11:35:18 +0200 Subject: [PATCH 129/237] xhci: mediatek: Add support for MTK xHCI host controller This patch is used to support the on-chip xHCI controller on MediaTek SoCs, currently control/bulk/interrupt transfers are supported. Signed-off-by: Chunfeng Yun Signed-off-by: Frank Wunderlich Reviewed-by: Weijie Gao Reviewed-by: Jagan Teki --- drivers/usb/host/Kconfig | 6 + drivers/usb/host/Makefile | 1 + drivers/usb/host/xhci-mtk.c | 303 ++++++++++++++++++++++++++++++++++++ drivers/usb/host/xhci.c | 10 ++ include/usb/xhci.h | 3 + 5 files changed, 323 insertions(+) create mode 100644 drivers/usb/host/xhci-mtk.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 94ac969058e..2f381dc9580 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -30,6 +30,12 @@ config USB_XHCI_DWC3_OF_SIMPLE Support USB2/3 functionality in simple SoC integrations with USB controller based on the DesignWare USB3 IP Core. +config USB_XHCI_MTK + bool "Support for MediaTek on-chip xHCI USB controller" + depends on ARCH_MEDIATEK + help + Enables support for the on-chip xHCI controller on MediaTek SoCs. + config USB_XHCI_MVEBU bool "MVEBU USB 3.0 support" default y diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index b62f346094f..e8e3b17e42c 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o obj-$(CONFIG_USB_XHCI_ROCKCHIP) += xhci-rockchip.o obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o +obj-$(CONFIG_USB_XHCI_MTK) += xhci-mtk.o obj-$(CONFIG_USB_XHCI_MVEBU) += xhci-mvebu.o obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c new file mode 100644 index 00000000000..8ff71854fcd --- /dev/null +++ b/drivers/usb/host/xhci-mtk.c @@ -0,0 +1,303 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 MediaTek, Inc. + * Authors: Chunfeng Yun + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* IPPC (IP Port Control) registers */ +#define IPPC_IP_PW_CTRL0 0x00 +#define CTRL0_IP_SW_RST BIT(0) + +#define IPPC_IP_PW_CTRL1 0x04 +#define CTRL1_IP_HOST_PDN BIT(0) + +#define IPPC_IP_PW_STS1 0x10 +#define STS1_IP_SLEEP_STS BIT(30) +#define STS1_U3_MAC_RST BIT(16) +#define STS1_XHCI_RST BIT(11) +#define STS1_SYS125_RST BIT(10) +#define STS1_REF_RST BIT(8) +#define STS1_SYSPLL_STABLE BIT(0) + +#define IPPC_IP_XHCI_CAP 0x24 +#define CAP_U3_PORT_NUM(p) ((p) & 0xff) +#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff) + +#define IPPC_U3_CTRL_0P 0x30 +#define CTRL_U3_PORT_HOST_SEL BIT(2) +#define CTRL_U3_PORT_PDN BIT(1) +#define CTRL_U3_PORT_DIS BIT(0) + +#define IPPC_U2_CTRL_0P 0x50 +#define CTRL_U2_PORT_HOST_SEL BIT(2) +#define CTRL_U2_PORT_PDN BIT(1) +#define CTRL_U2_PORT_DIS BIT(0) + +#define IPPC_U3_CTRL(p) (IPPC_U3_CTRL_0P + ((p) * 0x08)) +#define IPPC_U2_CTRL(p) (IPPC_U2_CTRL_0P + ((p) * 0x08)) + +struct mtk_xhci { + struct xhci_ctrl ctrl; /* Needs to come first in this struct! */ + struct xhci_hccr *hcd; + void __iomem *ippc; + struct udevice *dev; + struct udevice *vusb33_supply; + struct udevice *vbus_supply; + struct clk_bulk clks; + struct phy_bulk phys; + int num_u2ports; + int num_u3ports; +}; + +static int xhci_mtk_host_enable(struct mtk_xhci *mtk) +{ + u32 value; + u32 check_val; + int ret; + int i; + + /* power on host ip */ + clrbits_le32(mtk->ippc + IPPC_IP_PW_CTRL1, CTRL1_IP_HOST_PDN); + + /* power on and enable all u3 ports */ + for (i = 0; i < mtk->num_u3ports; i++) { + clrsetbits_le32(mtk->ippc + IPPC_U3_CTRL(i), + CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS, + CTRL_U3_PORT_HOST_SEL); + } + + /* power on and enable all u2 ports */ + for (i = 0; i < mtk->num_u2ports; i++) { + clrsetbits_le32(mtk->ippc + IPPC_U2_CTRL(i), + CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS, + CTRL_U2_PORT_HOST_SEL); + } + + /* + * wait for clocks to be stable, and clock domains reset to + * be inactive after power on and enable ports + */ + check_val = STS1_SYSPLL_STABLE | STS1_REF_RST | + STS1_SYS125_RST | STS1_XHCI_RST; + + if (mtk->num_u3ports) + check_val |= STS1_U3_MAC_RST; + + ret = readl_poll_timeout(mtk->ippc + IPPC_IP_PW_STS1, value, + (check_val == (value & check_val)), 20000); + if (ret) + dev_err(mtk->dev, "clocks are not stable 0x%x!\n", value); + + return ret; +} + +static int xhci_mtk_host_disable(struct mtk_xhci *mtk) +{ + int i; + + /* power down all u3 ports */ + for (i = 0; i < mtk->num_u3ports; i++) + setbits_le32(mtk->ippc + IPPC_U3_CTRL(i), CTRL_U3_PORT_PDN); + + /* power down all u2 ports */ + for (i = 0; i < mtk->num_u2ports; i++) + setbits_le32(mtk->ippc + IPPC_U2_CTRL(i), CTRL_U2_PORT_PDN); + + /* power down host ip */ + setbits_le32(mtk->ippc + IPPC_IP_PW_CTRL1, CTRL1_IP_HOST_PDN); + + return 0; +} + +static int xhci_mtk_ssusb_init(struct mtk_xhci *mtk) +{ + u32 value; + + /* reset whole ip */ + setbits_le32(mtk->ippc + IPPC_IP_PW_CTRL0, CTRL0_IP_SW_RST); + udelay(1); + clrbits_le32(mtk->ippc + IPPC_IP_PW_CTRL0, CTRL0_IP_SW_RST); + + value = readl(mtk->ippc + IPPC_IP_XHCI_CAP); + mtk->num_u3ports = CAP_U3_PORT_NUM(value); + mtk->num_u2ports = CAP_U2_PORT_NUM(value); + dev_info(mtk->dev, "u2p:%d, u3p:%d\n", + mtk->num_u2ports, mtk->num_u3ports); + + return xhci_mtk_host_enable(mtk); +} + +static int xhci_mtk_ofdata_get(struct mtk_xhci *mtk) +{ + struct udevice *dev = mtk->dev; + int ret = 0; + + mtk->hcd = devfdt_remap_addr_name(dev, "mac"); + if (!mtk->hcd) { + dev_err(dev, "failed to get xHCI base address\n"); + return -ENXIO; + } + + mtk->ippc = devfdt_remap_addr_name(dev, "ippc"); + if (!mtk->ippc) { + dev_err(dev, "failed to get IPPC base address\n"); + return -ENXIO; + } + + dev_info(dev, "hcd: 0x%p, ippc: 0x%p\n", mtk->hcd, mtk->ippc); + + ret = clk_get_bulk(dev, &mtk->clks); + if (ret) { + dev_err(dev, "failed to get clocks %d!\n", ret); + return ret; + } + + ret = device_get_supply_regulator(dev, "vusb33-supply", + &mtk->vusb33_supply); + if (ret) + debug("can't get vusb33 regulator %d!\n", ret); + + ret = device_get_supply_regulator(dev, "vbus-supply", + &mtk->vbus_supply); + if (ret) + debug("can't get vbus regulator %d!\n", ret); + + return 0; +} + +static int xhci_mtk_ldos_enable(struct mtk_xhci *mtk) +{ + int ret; + + ret = regulator_set_enable(mtk->vusb33_supply, true); + if (ret < 0 && ret != -ENOSYS) { + dev_err(mtk->dev, "failed to enable vusb33 %d!\n", ret); + return ret; + } + + ret = regulator_set_enable(mtk->vbus_supply, true); + if (ret < 0 && ret != -ENOSYS) { + dev_err(mtk->dev, "failed to enable vbus %d!\n", ret); + regulator_set_enable(mtk->vusb33_supply, false); + return ret; + } + + return 0; +} + +static void xhci_mtk_ldos_disable(struct mtk_xhci *mtk) +{ + regulator_set_enable(mtk->vbus_supply, false); + regulator_set_enable(mtk->vusb33_supply, false); +} + +static int xhci_mtk_phy_setup(struct mtk_xhci *mtk) +{ + struct udevice *dev = mtk->dev; + struct phy_bulk *phys = &mtk->phys; + int ret; + + ret = generic_phy_get_bulk(dev, phys); + if (ret) + return ret; + + ret = generic_phy_init_bulk(phys); + if (ret) + return ret; + + ret = generic_phy_power_on_bulk(phys); + if (ret) + generic_phy_exit_bulk(phys); + + return ret; +} + +static void xhci_mtk_phy_shutdown(struct mtk_xhci *mtk) +{ + generic_phy_power_off_bulk(&mtk->phys); + generic_phy_exit_bulk(&mtk->phys); +} + +static int xhci_mtk_probe(struct udevice *dev) +{ + struct mtk_xhci *mtk = dev_get_priv(dev); + struct xhci_hcor *hcor; + int ret; + + mtk->dev = dev; + ret = xhci_mtk_ofdata_get(mtk); + if (ret) + return ret; + + ret = xhci_mtk_ldos_enable(mtk); + if (ret) + goto ldos_err; + + ret = clk_enable_bulk(&mtk->clks); + if (ret) + goto clks_err; + + ret = xhci_mtk_phy_setup(mtk); + if (ret) + goto phys_err; + + ret = xhci_mtk_ssusb_init(mtk); + if (ret) + goto ssusb_init_err; + + hcor = (struct xhci_hcor *)((uintptr_t)mtk->hcd + + HC_LENGTH(xhci_readl(&mtk->hcd->cr_capbase))); + + return xhci_register(dev, mtk->hcd, hcor); + +ssusb_init_err: + xhci_mtk_phy_shutdown(mtk); +phys_err: + clk_disable_bulk(&mtk->clks); +clks_err: + xhci_mtk_ldos_disable(mtk); +ldos_err: + return ret; +} + +static int xhci_mtk_remove(struct udevice *dev) +{ + struct mtk_xhci *mtk = dev_get_priv(dev); + + xhci_deregister(dev); + xhci_mtk_host_disable(mtk); + xhci_mtk_ldos_disable(mtk); + clk_disable_bulk(&mtk->clks); + + return 0; +} + +static const struct udevice_id xhci_mtk_ids[] = { + { .compatible = "mediatek,mtk-xhci" }, + { } +}; + +U_BOOT_DRIVER(usb_xhci) = { + .name = "xhci-mtk", + .id = UCLASS_USB, + .of_match = xhci_mtk_ids, + .probe = xhci_mtk_probe, + .remove = xhci_mtk_remove, + .ops = &xhci_usb_ops, + .bind = dm_scan_fdt_dev, + .priv_auto_alloc_size = sizeof(struct mtk_xhci), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 40dee2e6d9b..c370eb63942 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -610,6 +610,16 @@ static int xhci_set_configuration(struct usb_device *udev) ep_ctx[ep_index]->tx_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) | EP_AVG_TRB_LENGTH(avg_trb_len)); + + /* + * The MediaTek xHCI defines some extra SW parameters which + * are put into reserved DWs in Slot and Endpoint Contexts + * for synchronous endpoints. + */ + if (IS_ENABLED(CONFIG_USB_XHCI_MTK)) { + ep_ctx[ep_index]->reserved[0] = + cpu_to_le32(EP_BPKTS(1) | EP_BBM(1)); + } } return xhci_configure_endpoints(udev, false); diff --git a/include/usb/xhci.h b/include/usb/xhci.h index 60175044884..20e4a21066f 100644 --- a/include/usb/xhci.h +++ b/include/usb/xhci.h @@ -670,6 +670,9 @@ struct xhci_ep_ctx { /* deq bitmasks */ #define EP_CTX_CYCLE_MASK (1 << 0) +/* reserved[0] bitmasks, MediaTek xHCI used */ +#define EP_BPKTS(p) (((p) & 0x7f) << 0) +#define EP_BBM(p) (((p) & 0x1) << 11) /** * struct xhci_input_control_context From ba42c286f62181d933b6ddcbc5f46b6d4fb26e0b Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Sat, 2 May 2020 11:35:19 +0200 Subject: [PATCH 130/237] arm: dts: mt7629: add usb related nodes Add usb, phy and clock nodes Signed-off-by: Chunfeng Yun Signed-off-by: Frank Wunderlich Reviewed-by: Weijie Gao --- arch/arm/dts/mt7629-rfb.dts | 8 ++++++++ arch/arm/dts/mt7629.dtsi | 41 +++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts index 687fe1c0297..bf84f763440 100644 --- a/arch/arm/dts/mt7629-rfb.dts +++ b/arch/arm/dts/mt7629-rfb.dts @@ -82,6 +82,14 @@ status = "okay"; }; +&xhci { + status = "okay"; +}; + +&u3phy { + status = "okay"; +}; + &watchdog { pinctrl-names = "default"; pinctrl-0 = <&watchdog_pins>; diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi index 644d2da4a88..6850e0058d4 100644 --- a/arch/arm/dts/mt7629.dtsi +++ b/arch/arm/dts/mt7629.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include "skeleton.dtsi" / { @@ -222,6 +223,46 @@ #size-cells = <0>; }; + ssusbsys: ssusbsys@1a000000 { + compatible = "mediatek,mt7629-ssusbsys", "syscon"; + reg = <0x1a000000 0x1000>; + #clock-cells = <1>; + }; + + xhci: usb@1a0c0000 { + compatible = "mediatek,mt7629-xhci", "mediatek,mtk-xhci"; + reg = <0x1a0c0000 0x1000>, <0x1a0c3e00 0x0100>; + reg-names = "mac", "ippc"; + power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>; + clocks = <&ssusbsys CLK_SSUSB_SYS_EN>, + <&ssusbsys CLK_SSUSB_REF_EN>, + <&ssusbsys CLK_SSUSB_MCU_EN>, + <&ssusbsys CLK_SSUSB_DMA_EN>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + status = "disabled"; + }; + + u3phy: usb-phy@1a0c4000 { + compatible = "mediatek,mt7629-tphy", "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1a0c4000 0x1000>; + status = "disabled"; + + u2port0: usb-phy@0 { + reg = <0x0 0x0700>; + #phy-cells = <1>; + clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>; + clock-names = "ref"; + }; + + u3port0: usb-phy@700 { + reg = <0x0700 0x0700>; + #phy-cells = <1>; + }; + }; + ethsys: syscon@1b000000 { compatible = "mediatek,mt7629-ethsys", "syscon"; reg = <0x1b000000 0x1000>; From 95d3e1d09067c1434ad33702261b09cbed82775b Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Sat, 2 May 2020 11:35:20 +0200 Subject: [PATCH 131/237] dt-bindings: phy-mtk-tphy: add properties of address mapping and clocks 1. add the address mapping related properties; 2. make "ref" clock optional, and add optional clock "da_ref"; 3. add the banks layout of TPHY V1 and V2; Signed-off-by: Chunfeng Yun Signed-off-by: Frank Wunderlich Reviewed-by: Weijie Gao --- doc/device-tree-bindings/phy/phy-mtk-tphy.txt | 78 ++++++++++++++++--- 1 file changed, 68 insertions(+), 10 deletions(-) diff --git a/doc/device-tree-bindings/phy/phy-mtk-tphy.txt b/doc/device-tree-bindings/phy/phy-mtk-tphy.txt index 037c5a4be5c..8cd23d8c0bb 100644 --- a/doc/device-tree-bindings/phy/phy-mtk-tphy.txt +++ b/doc/device-tree-bindings/phy/phy-mtk-tphy.txt @@ -7,10 +7,17 @@ controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA. Required properties (controller (parent) node): - compatible : should be one of "mediatek,generic-tphy-v1" - - clocks : (deprecated, use port's clocks instead) a list of phandle + - clock-specifier pairs, one for each entry in clock-names - - clock-names : (deprecated, use port's one instead) must contain - "u3phya_ref": for reference clock of usb3.0 analog phy. + "mediatek,generic-tphy-v2" + +- #address-cells: the number of cells used to represent physical + base addresses. +- #size-cells: the number of cells used to represent the size of an address. +- ranges: the address mapping relationship to the parent, defined with + - empty value: if optional 'reg' is used. + - non-empty value: if optional 'reg' is not used. should set + the child's base address to 0, the physical address + within parent's address space, and the length of + the address map. Required nodes : a sub-node is required for each port the controller provides. Address range information including the usual @@ -27,12 +34,6 @@ Optional properties (controller (parent) node): Required properties (port (child) node): - reg : address and length of the register set for the port. -- clocks : a list of phandle + clock-specifier pairs, one for each - entry in clock-names -- clock-names : must contain - "ref": 48M reference clock for HighSpeed analog phy; and 26M - reference clock for SuperSpeed analog phy, sometimes is - 24M, 25M or 27M, depended on platform. - #phy-cells : should be 1 (See second example) cell after port phandle is phy type from: - PHY_TYPE_USB2 @@ -40,6 +41,17 @@ Required properties (port (child) node): - PHY_TYPE_PCIE - PHY_TYPE_SATA +Optional properties (port (child) node): +- clocks : a list of phandle + clock-specifier pairs, one for each + entry in clock-names +- clock-names : may contain + "ref": 48M reference clock for HighSpeed (digital) phy; and 26M + reference clock for SuperSpeed (digital) phy, sometimes is + 24M, 25M or 27M, depended on platform. + "da_ref": the reference clock of analog phy, used if the clocks + of analog and digital phys are separated, otherwise uses + "ref" clock only if needed. + Example: u3phy2: usb-phy@1a244000 { @@ -84,3 +96,49 @@ usb30: usb@11270000 { phy-names = "usb2-0", "usb3-0"; ... }; + +Layout differences of banks between TPHY V1 and V2 +------------------------------------------------------------- +IP V1: +port offset bank +shared 0x0000 SPLLC + 0x0100 FMREG +u2 port0 0x0800 U2PHY_COM +u3 port0 0x0900 U3PHYD + 0x0a00 U3PHYD_BANK2 + 0x0b00 U3PHYA + 0x0c00 U3PHYA_DA +u2 port1 0x1000 U2PHY_COM +u3 port1 0x1100 U3PHYD + 0x1200 U3PHYD_BANK2 + 0x1300 U3PHYA + 0x1400 U3PHYA_DA +u2 port2 0x1800 U2PHY_COM + ... + +IP V2: +port offset bank +u2 port0 0x0000 MISC + 0x0100 FMREG + 0x0300 U2PHY_COM +u3 port0 0x0700 SPLLC + 0x0800 CHIP + 0x0900 U3PHYD + 0x0a00 U3PHYD_BANK2 + 0x0b00 U3PHYA + 0x0c00 U3PHYA_DA +u2 port1 0x1000 MISC + 0x1100 FMREG + 0x1300 U2PHY_COM +u3 port1 0x1700 SPLLC + 0x1800 CHIP + 0x1900 U3PHYD + 0x1a00 U3PHYD_BANK2 + 0x1b00 U3PHYA + 0x1c00 U3PHYA_DA +u2 port2 0x2000 MISC + ... + + SPLLC shared by u3 ports and FMREG shared by u2 ports on +TPHY V1 are put back into each port; a new bank MISC for +u2 ports and CHIP for u3 ports are added on TPHY V2. From 44f5c9ab459f5fafb72b39ec1e1bbedb7b164628 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Sat, 2 May 2020 11:35:21 +0200 Subject: [PATCH 132/237] dt-bindings: usb: mtk-xhci: Add binding for MediaTek xHCI host controller Add dt-binding for MediaTek xHCI host controller Signed-off-by: Chunfeng Yun Signed-off-by: Frank Wunderlich Reviewed-by: Weijie Gao --- .../usb/mediatek,mtk-xhci.txt | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 doc/device-tree-bindings/usb/mediatek,mtk-xhci.txt diff --git a/doc/device-tree-bindings/usb/mediatek,mtk-xhci.txt b/doc/device-tree-bindings/usb/mediatek,mtk-xhci.txt new file mode 100644 index 00000000000..0447468a2d1 --- /dev/null +++ b/doc/device-tree-bindings/usb/mediatek,mtk-xhci.txt @@ -0,0 +1,40 @@ +MediaTek xHCI + +The device node for USB3 host controller on MediaTek SoCs. + +Required properties: + - compatible : should be "mediatek,mtk-xhci" + - reg : specifies physical base address and size of the registers + - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control + - power-domains : a phandle to USB power domain node to control USB's + MTCMOS + - vusb33-supply : regulator of USB avdd3.3v + + - clocks : a list of phandle + clock-specifier pairs, one for each + entry in clock-names + - clock-names : must contain + "sys_ck": controller clock used by normal mode, + the following ones are optional: + "ref_ck": reference clock used by low power mode etc, + "mcu_ck": mcu_bus clock for register access, + "dma_ck": dma_bus clock for data transfer by DMA, + "xhci_ck": controller clock + + - phys : list of all the USB PHYs on this HCD + - phy-names: name specifier for the USB PHY + +Optional properties: + - vbus-supply : reference to the VBUS regulator; + +Example: +xhci: usb@1a0c0000 { + compatible = "mediatek,mt7629-xhci", "mediatek,mtk-xhci"; + reg = <0x1a0c0000 0x1000>, <0x1a0c3e00 0x0100>; + reg-names = "mac", "ippc"; + power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>; + clocks = <&ssusbsys CLK_SSUSB_SYS_EN>, <&ssusbsys CLK_SSUSB_REF_EN>, + <&ssusbsys CLK_SSUSB_MCU_EN>, <&ssusbsys CLK_SSUSB_DMA_EN>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + status = "disabled"; +}; From c01a7773a5e71322d3458f20560344ff475cd26c Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Sat, 2 May 2020 11:35:22 +0200 Subject: [PATCH 133/237] MAINTAINERS: MediaTek: add USB related files Add dt-binding files of xhci-mtk and phys, C files of phys. Signed-off-by: Chunfeng Yun Signed-off-by: Frank Wunderlich Reviewed-by: Weijie Gao --- MAINTAINERS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 66f0b07263e..ec59ce8b880 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -244,9 +244,12 @@ S: Maintained F: arch/arm/mach-mediatek/ F: arch/arm/include/asm/arch-mediatek/ F: board/mediatek/ +F: doc/device-tree-bindings/phy/phy-mtk-* +F: doc/device-tree-bindings/usb/mediatek,* F: doc/README.mediatek F: drivers/clk/mediatek/ F: drivers/mmc/mtk-sd.c +F: drivers/phy/phy-mtk-* F: drivers/pinctrl/mediatek/ F: drivers/power/domain/mtk-power-domain.c F: drivers/ram/mediatek/ From 3bebb4f3589fc447dddaf687d7fb9d503a65eaa4 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:03:56 +0800 Subject: [PATCH 134/237] rtc: ds1337: Add driver model support Add support of driver model of ds1337 Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- drivers/rtc/ds1337.c | 128 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 128 insertions(+) diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c index 9b31048e972..af94bcfdf44 100644 --- a/drivers/rtc/ds1337.c +++ b/drivers/rtc/ds1337.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2001-2008 + * Copyright 2020 NXP * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * Keith Outwater, keith_outwater@mvis.com` */ @@ -12,6 +13,7 @@ #include #include +#include #include #include @@ -60,6 +62,7 @@ #define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */ +#if !CONFIG_IS_ENABLED(DM_RTC) static uchar rtc_read (uchar reg); static void rtc_write (uchar reg, uchar val); @@ -188,3 +191,128 @@ static void rtc_write (uchar reg, uchar val) { i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); } +#else +static uchar rtc_read(struct udevice *dev, uchar reg) +{ + return dm_i2c_reg_read(dev, reg); +} + +static void rtc_write(struct udevice *dev, uchar reg, uchar val) +{ + dm_i2c_reg_write(dev, reg, val); +} + +static int ds1337_rtc_get(struct udevice *dev, struct rtc_time *tmp) +{ + int rel = 0; + uchar sec, min, hour, mday, wday, mon_cent, year, control, status; + + control = rtc_read(dev, RTC_CTL_REG_ADDR); + status = rtc_read(dev, RTC_STAT_REG_ADDR); + sec = rtc_read(dev, RTC_SEC_REG_ADDR); + min = rtc_read(dev, RTC_MIN_REG_ADDR); + hour = rtc_read(dev, RTC_HR_REG_ADDR); + wday = rtc_read(dev, RTC_DAY_REG_ADDR); + mday = rtc_read(dev, RTC_DATE_REG_ADDR); + mon_cent = rtc_read(dev, RTC_MON_REG_ADDR); + year = rtc_read(dev, RTC_YR_REG_ADDR); + + /* No century bit, assume year 2000 */ +#ifdef CONFIG_RTC_DS1388 + mon_cent |= 0x80; +#endif + + debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x\n", + year, mon_cent, mday, wday); + debug("hr: %02x min: %02x sec: %02x control: %02x status: %02x\n", + hour, min, sec, control, status); + + if (status & RTC_STAT_BIT_OSF) { + printf("### Warning: RTC oscillator has stopped\n"); + /* clear the OSF flag */ + rtc_write(dev, RTC_STAT_REG_ADDR, + rtc_read(dev, RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF); + rel = -1; + } + + tmp->tm_sec = bcd2bin(sec & 0x7F); + tmp->tm_min = bcd2bin(min & 0x7F); + tmp->tm_hour = bcd2bin(hour & 0x3F); + tmp->tm_mday = bcd2bin(mday & 0x3F); + tmp->tm_mon = bcd2bin(mon_cent & 0x1F); + tmp->tm_year = bcd2bin(year) + ((mon_cent & 0x80) ? 2000 : 1900); + tmp->tm_wday = bcd2bin((wday - 1) & 0x07); + tmp->tm_yday = 0; + tmp->tm_isdst = 0; + + debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + return rel; +} + +static int ds1337_rtc_set(struct udevice *dev, const struct rtc_time *tmp) +{ + uchar century; + + debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + rtc_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100)); + + century = (tmp->tm_year >= 2000) ? 0x80 : 0; + rtc_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon) | century); + + rtc_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday + 1)); + rtc_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday)); + rtc_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour)); + rtc_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min)); + rtc_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec)); + + return 0; +} + +#ifdef CONFIG_RTC_DS1337_NOOSC + #define RTC_DS1337_RESET_VAL \ + (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) +#else + #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) +#endif +static int ds1337_rtc_reset(struct udevice *dev) +{ +#ifdef CONFIG_RTC_DS1337 + rtc_write(dev, RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL); +#elif defined CONFIG_RTC_DS1388 + rtc_write(dev, RTC_CTL_REG_ADDR, 0x0); /* hw default */ +#endif +#ifdef CONFIG_RTC_DS1339_TCR_VAL + rtc_write(dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL); +#endif +#ifdef CONFIG_RTC_DS1388_TCR_VAL + rtc_write(dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL); +#endif + return 0; +} + +static const struct rtc_ops ds1337_rtc_ops = { + .get = ds1337_rtc_get, + .set = ds1337_rtc_set, + .reset = ds1337_rtc_reset, +}; + +static const struct udevice_id ds1337_rtc_ids[] = { + { .compatible = "ds1337" }, + { .compatible = "ds1338" }, + { .compatible = "ds1338" }, + { } +}; + +U_BOOT_DRIVER(rtc_ds1337) = { + .name = "rtc-ds1337", + .id = UCLASS_RTC, + .of_match = ds1337_rtc_ids, + .ops = &ds1337_rtc_ops, +}; +#endif From 22e0a840727825eb5b1b2d510bfd2d48972e9c5d Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:03:57 +0800 Subject: [PATCH 135/237] rtc: pt7c4338: Add driver model support Add support of driver model of pt7c4338 Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- drivers/rtc/pt7c4338.c | 100 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/drivers/rtc/pt7c4338.c b/drivers/rtc/pt7c4338.c index 6a19fe1d23f..5211d075868 100644 --- a/drivers/rtc/pt7c4338.c +++ b/drivers/rtc/pt7c4338.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2020 NXP * * Author: Priyanka Jain */ @@ -19,6 +20,7 @@ #include #include +#include #include #include @@ -46,6 +48,7 @@ #define RTC_PT7C4338_RESET_VAL \ (RTC_CTL_STAT_BIT_RS0 | RTC_CTL_STAT_BIT_RS1 | RTC_CTL_STAT_BIT_OUT) +#if !CONFIG_IS_ENABLED(DM_RTC) /****** Helper functions ****************************************/ static u8 rtc_read(u8 reg) { @@ -125,3 +128,100 @@ void rtc_reset(void) rtc_write(RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */ rtc_write(RTC_CTL_STAT_REG_ADDR, RTC_PT7C4338_RESET_VAL); } +#else +static u8 rtc_read(struct udevice *dev, u8 reg) +{ + return dm_i2c_reg_read(dev, reg); +} + +static void rtc_write(struct udevice *dev, u8 reg, u8 val) +{ + dm_i2c_reg_write(dev, reg, val); +} + +static int pt7c4338_rtc_get(struct udevice *dev, struct rtc_time *tmp) +{ + int ret = 0; + u8 sec, min, hour, mday, wday, mon, year, ctl_stat; + + ctl_stat = rtc_read(dev, RTC_CTL_STAT_REG_ADDR); + sec = rtc_read(dev, RTC_SEC_REG_ADDR); + min = rtc_read(dev, RTC_MIN_REG_ADDR); + hour = rtc_read(dev, RTC_HR_REG_ADDR); + wday = rtc_read(dev, RTC_DAY_REG_ADDR); + mday = rtc_read(dev, RTC_DATE_REG_ADDR); + mon = rtc_read(dev, RTC_MON_REG_ADDR); + year = rtc_read(dev, RTC_YR_REG_ADDR); + debug("Get RTC year: %02x mon: %02x mday: %02x wday: %02x\n", + year, mon, mday, wday); + debug("hr: %02x min: %02x sec: %02x control_status: %02x\n", + hour, min, sec, ctl_stat); + + if (ctl_stat & RTC_CTL_STAT_BIT_OSF) { + printf("### Warning: RTC oscillator has stopped\n"); + /* clear the OSF flag */ + rtc_write(dev, RTC_CTL_STAT_REG_ADDR, + rtc_read(dev, + RTC_CTL_STAT_REG_ADDR) + & ~RTC_CTL_STAT_BIT_OSF); + ret = -1; + } + + tmp->tm_sec = bcd2bin(sec & 0x7F); + tmp->tm_min = bcd2bin(min & 0x7F); + tmp->tm_hour = bcd2bin(hour & 0x3F); + tmp->tm_mday = bcd2bin(mday & 0x3F); + tmp->tm_mon = bcd2bin(mon & 0x1F); + tmp->tm_year = bcd2bin(year) + 2000; + tmp->tm_wday = bcd2bin((wday - 1) & 0x07); + tmp->tm_yday = 0; + tmp->tm_isdst = 0; + debug("Get DATE: %4d-%02d-%02d [wday=%d] TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + return ret; +} + +static int pt7c4338_rtc_set(struct udevice *dev, const struct rtc_time *tmp) +{ + debug("Set DATE: %4d-%02d-%02d [wday=%d] TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + rtc_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100)); + rtc_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon)); + rtc_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday + 1)); + rtc_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday)); + rtc_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour)); + rtc_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min)); + rtc_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec)); + + return 0; +} + +static int pt7c4338_rtc_reset(struct udevice *dev) +{ + rtc_write(dev, RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */ + rtc_write(dev, RTC_CTL_STAT_REG_ADDR, RTC_PT7C4338_RESET_VAL); + return 0; +} + +static const struct rtc_ops pt7c4338_rtc_ops = { + .get = pt7c4338_rtc_get, + .set = pt7c4338_rtc_set, + .reset = pt7c4338_rtc_reset, +}; + +static const struct udevice_id pt7c4338_rtc_ids[] = { + { .compatible = "pericom,pt7c4338" }, + { } +}; + +U_BOOT_DRIVER(rtc_pt7c4338) = { + .name = "rtc-pt7c4338", + .id = UCLASS_RTC, + .of_match = pt7c4338_rtc_ids, + .ops = &pt7c4338_rtc_ops, +}; +#endif From 213b19054cc7a92c69da8897c77868b11458ec30 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:03:58 +0800 Subject: [PATCH 136/237] powerpc: create dts component of i2c to build up an SoC Provide a common i2c components that we can utilize to build up the various device tree. Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/powerpc/dts/pq3-i2c-0.dtsi | 15 +++++++++++++++ arch/powerpc/dts/pq3-i2c-1.dtsi | 15 +++++++++++++++ arch/powerpc/dts/qoriq-i2c-0.dtsi | 25 +++++++++++++++++++++++++ arch/powerpc/dts/qoriq-i2c-1.dtsi | 25 +++++++++++++++++++++++++ 4 files changed, 80 insertions(+) create mode 100644 arch/powerpc/dts/pq3-i2c-0.dtsi create mode 100644 arch/powerpc/dts/pq3-i2c-1.dtsi create mode 100644 arch/powerpc/dts/qoriq-i2c-0.dtsi create mode 100644 arch/powerpc/dts/qoriq-i2c-1.dtsi diff --git a/arch/powerpc/dts/pq3-i2c-0.dtsi b/arch/powerpc/dts/pq3-i2c-0.dtsi new file mode 100644 index 00000000000..86a91e63365 --- /dev/null +++ b/arch/powerpc/dts/pq3-i2c-0.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 I2C Device Tree stub + * + * Copyright 2020 NXP + */ +i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + u-boot,dm-pre-reloc; + reg = <0x3000 0x100>; + interrupts = <43 2 0 0>; +}; diff --git a/arch/powerpc/dts/pq3-i2c-1.dtsi b/arch/powerpc/dts/pq3-i2c-1.dtsi new file mode 100644 index 00000000000..5d79b1fb4c3 --- /dev/null +++ b/arch/powerpc/dts/pq3-i2c-1.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 I2C Device Tree stub + * + * Copyright 2020 NXP + */ +i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + u-boot,dm-pre-reloc; + reg = <0x3100 0x100>; + interrupts = <43 2 0 0>; +}; diff --git a/arch/powerpc/dts/qoriq-i2c-0.dtsi b/arch/powerpc/dts/qoriq-i2c-0.dtsi new file mode 100644 index 00000000000..9d0ab886e72 --- /dev/null +++ b/arch/powerpc/dts/qoriq-i2c-0.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * QorIQ I2C Device Tree stub + * + * Copyright 2020 NXP + */ +i2c0: i2c@118000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + u-boot,dm-pre-reloc; + reg = <0x118000 0x100>; + interrupts = <38 2 0 0>; +}; + +i2c1: i2c@118100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + u-boot,dm-pre-reloc; + reg = <0x118100 0x100>; + interrupts = <38 2 0 0>; +}; diff --git a/arch/powerpc/dts/qoriq-i2c-1.dtsi b/arch/powerpc/dts/qoriq-i2c-1.dtsi new file mode 100644 index 00000000000..de0a22e3e01 --- /dev/null +++ b/arch/powerpc/dts/qoriq-i2c-1.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * QorIQ I2C Device Tree stub + * + * Copyright 2020 NXP + */ +i2c2: i2c@119000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <2>; + compatible = "fsl-i2c"; + u-boot,dm-pre-reloc; + reg = <0x119000 0x100>; + interrupts = <39 2 0 0>; +}; + +i2c3: i2c@119100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <3>; + compatible = "fsl-i2c"; + u-boot,dm-pre-reloc; + reg = <0x119100 0x100>; + interrupts = <39 2 0 0>; +}; From 9919e7ea0e850f01c70d448cd6673e4f6ffce9e2 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:03:59 +0800 Subject: [PATCH 137/237] dm: powerpc: P5040DS: add i2c DM support This supports i2c DM for board P5040DS Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p5040.dtsi | 5 ++++- include/configs/corenet_ds.h | 8 +++++++- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi index 67a62a77253..45988574a2e 100644 --- a/arch/powerpc/dts/p5040.dtsi +++ b/arch/powerpc/dts/p5040.dtsi @@ -3,7 +3,7 @@ * P5040 Silicon/SoC Device Tree Source (pre include) * * Copyright 2012 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ /dts-v1/; @@ -85,6 +85,9 @@ reg = <0x114000 0x1000>; clock-frequency = <0>; }; + + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" }; pcie@ffe200000 { diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index b2c86ff722b..26f534a90ab 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2009-2012 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ /* @@ -276,14 +277,19 @@ #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif +#define CONFIG_SYS_I2C_FSL /* * RapidIO From d864f717bbf1b3e5917cedbd07a0cd5d686578f8 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:00 +0800 Subject: [PATCH 138/237] configs: P5040DS: enable DM_I2C This enable DM_I2C in P5040DS defconfigs, except P5040DS SECURE_BOOT defconfigs Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/P5040DS_NAND_defconfig | 1 + configs/P5040DS_SDCARD_defconfig | 1 + configs/P5040DS_SPIFLASH_defconfig | 1 + configs/P5040DS_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index 8be7d908021..79155e8a656 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -62,3 +62,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index 134ea01ed3d..d5da79486c7 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -60,3 +60,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index 2daceccd7d4..359f7ca3d57 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -61,3 +61,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index 14a97f8f79d..ab64a547f3d 100644 --- a/configs/P5040DS_defconfig +++ b/configs/P5040DS_defconfig @@ -59,3 +59,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y From 74014dfcd8d990225c9ce2943a41c08896d0e7a6 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:01 +0800 Subject: [PATCH 139/237] dm: powerpc: P1020: add i2c DM support This supports i2c DM for SoC P1020 Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p1020-post.dtsi | 2 ++ board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 24 ++++++++++++++++++++- include/configs/P1022DS.h | 4 +++- include/configs/p1_p2_rdb_pc.h | 9 +++++++- 4 files changed, 36 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index 1c77702f01e..1dce8e86e9a 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -44,6 +44,8 @@ clock-frequency = <0>; }; + /include/ "pq3-i2c-0.dtsi" + /include/ "pq3-i2c-1.dtsi" }; /* PCIe controller base address 0x9000 */ diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 71fca8ca1e1..f668d7efb12 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #include @@ -227,6 +228,7 @@ int checkboard(void) struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u8 in, out, io_config, val; + int bus_num = CONFIG_SYS_SPD_BUS_NUM; printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME, in_8(&cpld_data->cpld_rev_major) & 0x0F, @@ -234,7 +236,26 @@ int checkboard(void) in_8(&cpld_data->pcba_rev) & 0x0F); /* Initialize i2c early for rom_loc and flash bank information */ - i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); + #if defined(CONFIG_DM_I2C) + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_PCA9557_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return -ENXIO; + } + + if (dm_i2c_read(dev, 0, &in, 1) < 0 || + dm_i2c_read(dev, 1, &out, 1) < 0 || + dm_i2c_read(dev, 3, &io_config, 1) < 0) { + printf("Error reading i2c boot information!\n"); + return 0; /* Don't want to hang() on this error */ + } + #else /* Non DM I2C support - will be removed */ + i2c_set_bus_num(bus_num); if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 || i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 || @@ -242,6 +263,7 @@ int checkboard(void) printf("Error reading i2c boot information!\n"); return 0; /* Don't want to hang() on this error */ } + #endif val = (in & io_config) | (out & (~io_config)); diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 5cc2e069797..f8b035fb794 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -359,8 +359,8 @@ #endif /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 @@ -368,6 +368,8 @@ #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} +#endif +#define CONFIG_SYS_I2C_FSL /* * I2C2 EEPROM diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index c42f1a9fce7..d59fd033bda 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ /* @@ -537,8 +538,8 @@ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 @@ -546,6 +547,12 @@ #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif + +#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ From 3cbc3822d6c33929a4f170a5c544cd0166e07666 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:02 +0800 Subject: [PATCH 140/237] configs: P1020RDB: enable DM_I2C and DM_RTC This enables DM_I2C and DM_RTC in P1020RDB defconfigs Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/P1020RDB-PC_36BIT_NAND_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_defconfig | 2 ++ configs/P1020RDB-PC_NAND_defconfig | 2 ++ configs/P1020RDB-PC_SDCARD_defconfig | 2 ++ configs/P1020RDB-PC_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PC_defconfig | 2 ++ configs/P1020RDB-PD_NAND_defconfig | 2 ++ configs/P1020RDB-PD_SDCARD_defconfig | 2 ++ configs/P1020RDB-PD_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PD_defconfig | 2 ++ 12 files changed, 24 insertions(+) diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 2396d910115..cdcdefd9899 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -82,3 +82,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 745200da514..0fb3507e495 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -77,3 +77,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 3eadd3d83c9..24fdda7656d 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -79,3 +79,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 9b7901f5c37..b0a3e0f1884 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -66,3 +66,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index e99709a2b87..d94885dcbd6 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -81,3 +81,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index ef007e5fe4b..c324faff6dc 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -76,3 +76,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index c8b0923cb50..4058e918958 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -78,3 +78,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 1a30c97f7fa..58cb5845251 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -65,3 +65,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index e1858e4cac8..37b174623f6 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -85,3 +85,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index e24c89f7266..df89dcfc76a 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -80,3 +80,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index c89201f9788..68e3970d6d2 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -82,3 +82,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index c79d599b609..6251ca268ad 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -69,3 +69,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y From 2563aea1ea67cd524966974a0ad8627879f86864 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:03 +0800 Subject: [PATCH 141/237] dts: powerpc: P2020RDB: add i2c node This adds i2c node for board P2020RDB Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 5bbd5c54681..4ed093dad4e 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -37,6 +37,9 @@ /* Filled in by U-Boot */ clock-frequency = <0>; }; + + /include/ "pq3-i2c-0.dtsi" + /include/ "pq3-i2c-1.dtsi" }; /* PCIe controller base address 0x8000 */ From b36decf81e077a858db92bdbc3de3ddc5877033a Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:04 +0800 Subject: [PATCH 142/237] configs: P2020RDB: enable DM_I2C and DM_RTC This enables DM_I2C and DM_RTC in P2020RDB defconfigs Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/P2020RDB-PC_36BIT_NAND_defconfig | 2 ++ configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 2 ++ configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 2 ++ configs/P2020RDB-PC_36BIT_defconfig | 2 ++ configs/P2020RDB-PC_NAND_defconfig | 2 ++ configs/P2020RDB-PC_SDCARD_defconfig | 2 ++ configs/P2020RDB-PC_SPIFLASH_defconfig | 2 ++ configs/P2020RDB-PC_defconfig | 2 ++ 8 files changed, 16 insertions(+) diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index b419367e7e3..950fabef219 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -87,3 +87,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 0afddc2ed98..e9b21d2d7b9 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -82,3 +82,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 1a700a867fe..6de28bd0c5b 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -84,3 +84,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 8b98cb8b9a7..c48e993b71f 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -71,3 +71,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index b1a26af0f4b..8d7a7891fb0 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -86,3 +86,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index c76958e1f38..280b190be40 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -81,3 +81,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 0892596fd61..e0ebe44cac7 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -83,3 +83,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index e37ca66d1fc..dd5c14e4cba 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -70,3 +70,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y From 2f3bb4ab3e0ea2efa4e46b8f277a07532ec61298 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:05 +0800 Subject: [PATCH 143/237] dm: powerpc: P2041RDB: add i2c DM support This supports i2c DM for board P2041RDB Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2041.dtsi | 5 ++++- include/configs/P2041RDB.h | 9 ++++++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi index 0f5e7dbdc81..95931e299d8 100644 --- a/arch/powerpc/dts/p2041.dtsi +++ b/arch/powerpc/dts/p2041.dtsi @@ -3,7 +3,7 @@ * P2041 Silicon/SoC Device Tree Source (pre include) * * Copyright 2011 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ /dts-v1/; @@ -86,6 +86,9 @@ reg = <0x114000 0x1000>; clock-frequency = <0>; }; + + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" }; pcie@ffe200000 { diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 0dcba7deeae..dfc84583970 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2011-2012 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ /* @@ -267,14 +268,20 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif +#define CONFIG_SYS_I2C_FSL + /* * RapidIO From 84daa8118af44b7ccfa85929d1ed21e9f9d80029 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:06 +0800 Subject: [PATCH 144/237] config: P2041RDB: enable DM_I2C This enables DM_I2C in P2041RDB defconfig, except P2041RDB SRIO_PCIE_BOOT and SECURE_BOOT defconfigs Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/P2041RDB_NAND_defconfig | 1 + configs/P2041RDB_SDCARD_defconfig | 1 + configs/P2041RDB_SPIFLASH_defconfig | 1 + configs/P2041RDB_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 0399a27e5d3..79dcf659549 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -61,3 +61,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 0b53a0595ca..8be3f7f0530 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -60,3 +60,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 8c2e20eeaa6..973a37fdba7 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -61,3 +61,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index 6836d42932f..21db59492f6 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -59,3 +59,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y From 0a98d5b02dad297926d29afca20d2dce858e469d Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:07 +0800 Subject: [PATCH 145/237] powerpc: dts: P3041: add i2c node This adds i2c node for SoC P3041 Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p3041.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/dts/p3041.dtsi b/arch/powerpc/dts/p3041.dtsi index 6736d000356..3152683b846 100644 --- a/arch/powerpc/dts/p3041.dtsi +++ b/arch/powerpc/dts/p3041.dtsi @@ -3,7 +3,7 @@ * P3041 Silicon/SoC Device Tree Source (pre include) * * Copyright 2010 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ /dts-v1/; @@ -86,6 +86,8 @@ reg = <0x114000 0x1000>; clock-frequency = <0>; }; + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" }; pcie@ffe200000 { From b4a46f279a1dcd4f04841c9d74123a92b63ff802 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:08 +0800 Subject: [PATCH 146/237] configs: P3041DS: enable DM_I2C This enables DM_I2C in P3041DS defconfigs, except P3041DS SECURE_BOOT and SRIO_PCIE_BOOT defconfig Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/P3041DS_NAND_defconfig | 1 + configs/P3041DS_SDCARD_defconfig | 1 + configs/P3041DS_SPIFLASH_defconfig | 1 + configs/P3041DS_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig index eb000c8b3c4..bee937b65b9 100644 --- a/configs/P3041DS_NAND_defconfig +++ b/configs/P3041DS_NAND_defconfig @@ -61,3 +61,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig index ade8b58feee..74f1d0b3b6b 100644 --- a/configs/P3041DS_SDCARD_defconfig +++ b/configs/P3041DS_SDCARD_defconfig @@ -60,3 +60,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig index 0bb7288fa4b..9004e8eb5e3 100644 --- a/configs/P3041DS_SPIFLASH_defconfig +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -61,3 +61,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig index 428d9e3e6cf..58f585c6c73 100644 --- a/configs/P3041DS_defconfig +++ b/configs/P3041DS_defconfig @@ -59,3 +59,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y From 369cb8850505d04eb4ade2a035d095b3ed92e115 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:09 +0800 Subject: [PATCH 147/237] powerpc: dts: P4080: add i2c node This adds i2c node for SoC P4080 Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p4080.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi index 02f39fbfcb3..4a80561e188 100644 --- a/arch/powerpc/dts/p4080.dtsi +++ b/arch/powerpc/dts/p4080.dtsi @@ -3,7 +3,7 @@ * P4080/P4040 Silicon/SoC Device Tree Source (pre include) * * Copyright 2011 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ /dts-v1/; @@ -97,6 +97,8 @@ reg = <0x211000 0x1000>; phy_type = "ulpi"; }; + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" }; pcie@ffe200000 { From c55622540782daadfb64f90f142bd3648d9c65ef Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:10 +0800 Subject: [PATCH 148/237] configs: P4080DS: enable DM_I2C This enables DM_I2C in P4080DS defconfigs, except P4080DS SRIO_PCIE_BOOT and SECURE_BOOT defconfigs Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/P4080DS_SDCARD_defconfig | 1 + configs/P4080DS_SPIFLASH_defconfig | 1 + configs/P4080DS_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index 1318e261fb4..02d92449583 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -59,3 +59,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index f19ace2f2ed..fa1b8d94465 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -60,3 +60,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig index 31e91c12814..674eca65acb 100644 --- a/configs/P4080DS_defconfig +++ b/configs/P4080DS_defconfig @@ -58,3 +58,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y From 9e9771a6105785189828706418945748d4db89a1 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:11 +0800 Subject: [PATCH 149/237] dm: powerpc: T1023/T1024: add i2c DM support This supports i2c DM for SoC T1023/T1024 Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/powerpc/dts/t102x.dtsi | 4 +- board/freescale/t102xqds/t102xqds.c | 95 ++++++++++++++++++++++++++++- board/freescale/t102xqds/t102xqds.h | 3 +- board/freescale/t102xrdb/t102xrdb.c | 71 +++++++++++++++++++-- include/configs/T102xQDS.h | 10 ++- include/configs/T102xRDB.h | 8 ++- 6 files changed, 181 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi index a6b821a76af..521825d85a4 100644 --- a/arch/powerpc/dts/t102x.dtsi +++ b/arch/powerpc/dts/t102x.dtsi @@ -3,7 +3,7 @@ * T102X Silicon/SoC Device Tree Source (pre include) * * Copyright 2013 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ /dts-v1/; @@ -75,6 +75,8 @@ reg = <0x114000 0x1000>; clock-frequency = <0>; }; + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" }; pcie@ffe240000 { diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c index e42337e47a4..32b4780376a 100644 --- a/board/freescale/t102xqds/t102xqds.c +++ b/board/freescale/t102xqds/t102xqds.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #include @@ -75,11 +76,24 @@ int checkboard(void) return 0; } -int select_i2c_ch_pca9547(u8 ch) +int select_i2c_ch_pca9547(u8 ch, int bus_num) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + ret = dm_i2c_write(dev, 0, &ch, 1); +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -191,6 +205,82 @@ void board_retimer_ds125df111_init(void) { u8 reg; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret, bus_num = 0; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, + 1, &dev); + if (ret) + goto failed; + + /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */ + reg = I2C_MUX_CH7; + dm_i2c_write(dev, 0, ®, 1); + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC, + 1, &dev); + if (ret) + goto failed; + + reg = I2C_MUX_CH5; + dm_i2c_write(dev, 0, ®, 1); + + /* Access to Control/Shared register */ + ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR, + 1, &dev); + if (ret) + goto failed; + reg = 0x0; + dm_i2c_write(dev, 0xff, ®, 1); + + /* Read device revision and ID */ + dm_i2c_read(dev, 1, ®, 1); + debug("Retimer version id = 0x%x\n", reg); + + /* Enable Broadcast */ + reg = 0x0c; + dm_i2c_write(dev, 0xff, ®, 1); + + /* Reset Channel Registers */ + dm_i2c_read(dev, 0, ®, 1); + reg |= 0x4; + dm_i2c_write(dev, 0, ®, 1); + + /* Enable override divider select and Enable Override Output Mux */ + dm_i2c_read(dev, 9, ®, 1); + reg |= 0x24; + dm_i2c_write(dev, 9, ®, 1); + + /* Select VCO Divider to full rate (000) */ + dm_i2c_read(dev, 0x18, ®, 1); + reg &= 0x8f; + dm_i2c_write(dev, 0x18, ®, 1); + + /* Select active PFD MUX input as re-timed data (001) */ + dm_i2c_read(dev, 0x1e, ®, 1); + reg &= 0x3f; + reg |= 0x20; + dm_i2c_write(dev, 0x1e, ®, 1); + + /* Set data rate as 10.3125 Gbps */ + reg = 0x0; + dm_i2c_write(dev, 0x60, ®, 1); + reg = 0xb2; + dm_i2c_write(dev, 0x61, ®, 1); + reg = 0x90; + dm_i2c_write(dev, 0x62, ®, 1); + reg = 0xb3; + dm_i2c_write(dev, 0x63, ®, 1); + reg = 0xcd; + dm_i2c_write(dev, 0x64, ®, 1); + return; + +failed: + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return; +#else /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */ reg = I2C_MUX_CH7; i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1); @@ -241,6 +331,7 @@ void board_retimer_ds125df111_init(void) i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); reg = 0xcd; i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); +#endif } int board_early_init_f(void) @@ -281,7 +372,7 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); board_mux_lane_to_slot(); board_retimer_ds125df111_init(); diff --git a/board/freescale/t102xqds/t102xqds.h b/board/freescale/t102xqds/t102xqds.h index 15de1325988..d327b5edb9f 100644 --- a/board/freescale/t102xqds/t102xqds.h +++ b/board/freescale/t102xqds/t102xqds.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #ifndef __T102x_QDS_H__ @@ -8,6 +9,6 @@ void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, bd_t *bd); -int select_i2c_ch_pca9547(u8 ch); +int select_i2c_ch_pca9547(u8 ch, int bus_num); #endif diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index eee09a57019..a34490c8bdc 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #include @@ -250,8 +251,69 @@ static u32 t1023rdb_ctrl(u32 ctrl_type) { ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 val, orig_bus = i2c_get_bus_num(); + u32 val; u8 tmp; + int bus_num = I2C_PCA6408_BUS_NUM; + +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA6408_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + switch (ctrl_type) { + case GPIO1_SD_SEL: + val = in_be32(&pgpio->gpdat); + val |= GPIO1_SD_SEL; + out_be32(&pgpio->gpdat, val); + setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); + break; + case GPIO1_EMMC_SEL: + val = in_be32(&pgpio->gpdat); + val &= ~GPIO1_SD_SEL; + out_be32(&pgpio->gpdat, val); + setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); + break; + case GPIO3_GET_VERSION: + pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + + GPIO3_OFFSET); + val = in_be32(&pgpio->gpdat); + val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3; + if (val == 0x3) /* GPIO3_4/5 not used on RevB */ + val = 0; + return val; + case I2C_GET_BANK: + dm_i2c_read(dev, 0, &tmp, 1); + tmp &= 0x7; + tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2); + return tmp; + case I2C_SET_BANK0: + tmp = 0x0; + dm_i2c_write(dev, 1, &tmp, 1); + tmp = 0xf8; + dm_i2c_write(dev, 3, &tmp, 1); + /* asserting HRESET_REQ */ + out_be32(&gur->rstcr, 0x2); + break; + case I2C_SET_BANK4: + tmp = 0x1; + dm_i2c_write(dev, 1, &tmp, 1); + tmp = 0xf8; + dm_i2c_write(dev, 3, &tmp, 1); + out_be32(&gur->rstcr, 0x2); + break; + default: + break; + } +#else + u32 orig_bus; + + orig_bus = i2c_get_bus_num(); switch (ctrl_type) { case GPIO1_SD_SEL: @@ -275,14 +337,14 @@ static u32 t1023rdb_ctrl(u32 ctrl_type) val = 0; return val; case I2C_GET_BANK: - i2c_set_bus_num(I2C_PCA6408_BUS_NUM); + i2c_set_bus_num(bus_num); i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1); tmp &= 0x7; tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2); i2c_set_bus_num(orig_bus); return tmp; case I2C_SET_BANK0: - i2c_set_bus_num(I2C_PCA6408_BUS_NUM); + i2c_set_bus_num(bus_num); tmp = 0x0; i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1); tmp = 0xf8; @@ -291,7 +353,7 @@ static u32 t1023rdb_ctrl(u32 ctrl_type) out_be32(&gur->rstcr, 0x2); break; case I2C_SET_BANK4: - i2c_set_bus_num(I2C_PCA6408_BUS_NUM); + i2c_set_bus_num(bus_num); tmp = 0x1; i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1); tmp = 0xf8; @@ -301,6 +363,7 @@ static u32 t1023rdb_ctrl(u32 ctrl_type) default: break; } +#endif return 0; } diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 20c0534f5a3..7f9e0c84bb2 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ /* @@ -437,14 +438,20 @@ unsigned long get_board_ddr_clk(void); #endif /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif + +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define I2C_MUX_PCA_ADDR 0x77 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ @@ -460,6 +467,7 @@ unsigned long get_board_ddr_clk(void); /* LDI/DVI Encoder for display */ #define CONFIG_SYS_I2C_LDI_ADDR 0x38 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 +#define CONFIG_SYS_I2C_DVI_BUS_NUM 0 /* * RTC configuration diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 094795cc6d5..2b43b812b34 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ /* @@ -434,15 +435,20 @@ unsigned long get_board_ddr_clk(void); #endif /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define I2C_PCA6408_BUS_NUM 1 #define I2C_PCA6408_ADDR 0x20 From fe138b8a3f9eeac7487bb0761313fafc55ec3c29 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:12 +0800 Subject: [PATCH 150/237] configs: T1024RDB: enable DM_I2C and DM_RTC This enables DM_I2C and DM_RTC in T1024RDB defconfigs, except T1024RDB SECURE_BOOT defconfig Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/T1024RDB_NAND_defconfig | 2 ++ configs/T1024RDB_SDCARD_defconfig | 2 ++ configs/T1024RDB_SPIFLASH_defconfig | 2 ++ configs/T1024RDB_defconfig | 2 ++ 4 files changed, 8 insertions(+) diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index c2c73a744ac..f024d93da17 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -81,3 +81,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 3ded897dcf4..ebf42b40fe5 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -78,3 +78,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 123d8ddbb0b..9bc31496306 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -81,3 +81,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index dc6b62c67ef..f25fee0c8f6 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -66,3 +66,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y From 2703e640d218d9bf297bd9ad9ccdd10e8bd2ce56 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:13 +0800 Subject: [PATCH 151/237] dm: ppc: p1010: add i2c DM support This supports i2c DM for SoC P1010 Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- board/freescale/p1010rdb/p1010rdb.c | 156 +++++++++++++++++++++++++++- include/configs/P1010RDB.h | 8 +- 2 files changed, 162 insertions(+), 2 deletions(-) diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index a0866926832..65ac47263ec 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #include @@ -136,6 +137,125 @@ int config_board_mux(int ctrl_type) ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u8 tmp; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; +#if defined(CONFIG_TARGET_P1010RDB_PA) + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + + ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, + I2C_PCA9557_ADDR1, 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", + __func__, I2C_PCA9557_BUS_NUM); + return ret; + } + switch (ctrl_type) { + case MUX_TYPE_IFC: + tmp = 0xf0; + dm_i2c_write(dev, 3, &tmp, 1); + tmp = 0x01; + dm_i2c_write(dev, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_IFC; + clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); + break; + case MUX_TYPE_SDHC: + tmp = 0xf0; + dm_i2c_write(dev, 3, &tmp, 1); + tmp = 0x05; + dm_i2c_write(dev, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_SDHC; + clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, + PMUXCR1_SDHC_ENABLE); + break; + case MUX_TYPE_SPIFLASH: + out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); + break; + case MUX_TYPE_TDM: + out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); + out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); + break; + case MUX_TYPE_CAN: + out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); + break; + default: + break; + } +#elif defined(CONFIG_TARGET_P1010RDB_PB) + ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, + I2C_PCA9557_ADDR2, 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", + __func__, I2C_PCA9557_BUS_NUM); + return ret; + } + switch (ctrl_type) { + case MUX_TYPE_IFC: + dm_i2c_read(dev, 0, &tmp, 1); + clrbits_8(&tmp, 0x04); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x04); + dm_i2c_write(dev, 3, &tmp, 1); + sd_ifc_mux = MUX_TYPE_IFC; + clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); + break; + case MUX_TYPE_SDHC: + dm_i2c_read(dev, 0, &tmp, 1); + setbits_8(&tmp, 0x04); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x04); + dm_i2c_write(dev, 3, &tmp, 1); + sd_ifc_mux = MUX_TYPE_SDHC; + clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, + PMUXCR1_SDHC_ENABLE); + break; + case MUX_TYPE_SPIFLASH: + dm_i2c_read(dev, 0, &tmp, 1); + clrbits_8(&tmp, 0x80); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x80); + dm_i2c_write(dev, 3, &tmp, 1); + break; + case MUX_TYPE_TDM: + dm_i2c_read(dev, 0, &tmp, 1); + setbits_8(&tmp, 0x82); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x82); + dm_i2c_write(dev, 3, &tmp, 1); + break; + case MUX_TYPE_CAN: + dm_i2c_read(dev, 0, &tmp, 1); + clrbits_8(&tmp, 0x02); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x02); + dm_i2c_write(dev, 3, &tmp, 1); + break; + case MUX_TYPE_CS0_NOR: + dm_i2c_read(dev, 0, &tmp, 1); + clrbits_8(&tmp, 0x08); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x08); + dm_i2c_write(dev, 3, &tmp, 1); + break; + case MUX_TYPE_CS0_NAND: + dm_i2c_read(dev, 0, &tmp, 1); + setbits_8(&tmp, 0x08); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x08); + dm_i2c_write(dev, 3, &tmp, 1); + break; + default: + break; + } +#endif +#else #if defined(CONFIG_TARGET_P1010RDB_PA) struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); @@ -242,6 +362,7 @@ int config_board_mux(int ctrl_type) break; } i2c_set_bus_num(orig_bus); +#endif #endif return 0; } @@ -250,9 +371,23 @@ int config_board_mux(int ctrl_type) int i2c_pca9557_read(int type) { u8 val; + int bus_num = I2C_PCA9557_BUS_NUM; - i2c_set_bus_num(I2C_PCA9557_BUS_NUM); +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2, 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", + __func__, bus_num); + return ret; + } + dm_i2c_read(dev, 0, &val, 1); +#else + i2c_set_bus_num(bus_num); i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1); +#endif switch (type) { case I2C_READ_BANK: @@ -280,11 +415,26 @@ int checkboard(void) printf("Board: %sRDB-PA, ", cpu->name); #elif defined(CONFIG_TARGET_P1010RDB_PB) printf("Board: %sRDB-PB, ", cpu->name); +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + I2C_PCA9557_BUS_NUM); + return ret; + } + val = 0x0; /* no polarity inversion */ + dm_i2c_write(dev, 2, &val, 1); +#else i2c_set_bus_num(I2C_PCA9557_BUS_NUM); i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE); val = 0x0; /* no polarity inversion */ i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1); #endif +#endif #ifdef CONFIG_SDCARD /* switch to IFC to read info from CPLD */ @@ -308,7 +458,11 @@ int checkboard(void) case 0xe: puts("SDHC\n"); val = 0x60; /* set pca9557 pin input/output */ +#ifdef CONFIG_DM_I2C + dm_i2c_write(dev, 3, &val, 1); +#else i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1); +#endif break; case 0x5: config_board_mux(MUX_TYPE_IFC); diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 60e8904d429..41dbbedecc4 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ /* @@ -522,17 +523,22 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif #define I2C_PCA9557_ADDR1 0x18 #define I2C_PCA9557_ADDR2 0x19 #define I2C_PCA9557_BUS_NUM 0 +#define CONFIG_SYS_I2C_FSL /* I2C EEPROM */ #if defined(CONFIG_TARGET_P1010RDB_PB) From 70571f981b01e900c2ae320f7f06726ce69291bd Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:14 +0800 Subject: [PATCH 152/237] configs: P1010: Enable DM_I2C and DM_RTC Enable DM_I2C and DM_RTC in P1010RDB defconfigs, except P1010RDB SECBOOT defconfigs. Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PA_NAND_defconfig | 2 ++ configs/P1010RDB-PA_NOR_defconfig | 2 ++ configs/P1010RDB-PA_SDCARD_defconfig | 2 ++ configs/P1010RDB-PA_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PB_NAND_defconfig | 2 ++ configs/P1010RDB-PB_NOR_defconfig | 2 ++ configs/P1010RDB-PB_SDCARD_defconfig | 2 ++ configs/P1010RDB-PB_SPIFLASH_defconfig | 2 ++ 16 files changed, 32 insertions(+) diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index 74294fceee5..85b97d1e15f 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -77,3 +77,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index d43ad79f2e5..e1109637c13 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -58,3 +58,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index ddb7e604cd9..4b8ddd997c2 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -71,3 +71,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 12a073d42ae..2975f404fcd 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -73,3 +73,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index 67cba6a436d..632ecd7af54 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -76,3 +76,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index 05ec02451c5..037fe0ab890 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -57,3 +57,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 95a15f7a18e..48a1d34cc9a 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -70,3 +70,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index a7dd582c868..f43c60011ce 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -72,3 +72,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 6e71c2a48fe..dd7d6891633 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -77,3 +77,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 79e4117d776..7e8c150603e 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -58,3 +58,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 083fe79f7d9..7996490e936 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -71,3 +71,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 6247d4706f2..4291002d343 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -73,3 +73,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 12c74915ced..4a216dd55bc 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -76,3 +76,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 943ca96fadf..2cc52ed76de 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -57,3 +57,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 3548b951109..d90cc8e7bbf 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -70,3 +70,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index b54cf2b8b64..e6833d43e35 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -72,3 +72,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y From 01d97d5f18a28dfbb8d5e033f2408040fb4f8134 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:56:37 +0800 Subject: [PATCH 153/237] dm: ppc: MPC8548CDS: add i2c DM support This supports i2c DM for board MPC8548CDS Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- board/freescale/common/sys_eeprom.c | 3 ++- include/configs/MPC8548CDS.h | 9 ++++++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 6f151b0f717..c487e3a515f 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -595,6 +595,7 @@ unsigned int get_cpu_board_revision(void) (void *)&be, sizeof(be)); #else struct udevice *dev; + int ret; #ifdef CONFIG_SYS_EEPROM_BUS_NUM ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, CONFIG_SYS_I2C_EEPROM_ADDR, @@ -603,7 +604,7 @@ unsigned int get_cpu_board_revision(void) #else ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - &dev) + &dev); #endif if (!ret) dm_i2c_read(dev, 0, (void *)&be, sizeof(be)); diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index a68d190f6ab..b7796236fd4 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. + * Copyright 2020 NXP */ /* @@ -304,12 +305,18 @@ extern unsigned long get_clock_freq(void); /* * I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } +#else +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif +#define CONFIG_SYS_I2C_FSL /* EEPROM */ #define CONFIG_ID_EEPROM From 1321aef8cd13d89d36e8cda8482b87fcea93994a Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:16 +0800 Subject: [PATCH 154/237] configs: MPC8548CDS: enable DM_I2C This enables DM_I2C in MPC8548CDS defconfigs Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/MPC8548CDS_36BIT_defconfig | 1 + configs/MPC8548CDS_defconfig | 1 + configs/MPC8548CDS_legacy_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 22034409609..84ba9422d61 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -45,3 +45,4 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y +CONFIG_DM_I2C=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index b4ac4f1082a..242487524e5 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -44,3 +44,4 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y +CONFIG_DM_I2C=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 9b6f8be9cfe..43a1dff182b 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -44,3 +44,4 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y +CONFIG_DM_I2C=y From e6bd72f880a76652ce1d6742880e7efcd85b8fb1 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:17 +0800 Subject: [PATCH 155/237] dm: ppc: T4240: add i2c DM support This supports i2c DM for SoC T4240 Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/powerpc/dts/t4240.dtsi | 5 +- board/freescale/common/vsc3316_3308.c | 258 +++++++++++++++++++++++++- board/freescale/t4qds/t4240qds.c | 45 ++++- include/configs/T4240QDS.h | 13 ++ include/configs/T4240RDB.h | 9 +- 5 files changed, 320 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/dts/t4240.dtsi b/arch/powerpc/dts/t4240.dtsi index 43f98cd9e16..9b5902fe9e2 100644 --- a/arch/powerpc/dts/t4240.dtsi +++ b/arch/powerpc/dts/t4240.dtsi @@ -3,7 +3,7 @@ * T4240 Silicon/SoC Device Tree Source (pre include) * * Copyright 2013 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ /dts-v1/; @@ -125,6 +125,9 @@ reg = <0x114000 0x1000>; clock-frequency = <0>; }; + + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" }; pcie@ffe240000 { diff --git a/board/freescale/common/vsc3316_3308.c b/board/freescale/common/vsc3316_3308.c index 033fae020f1..f0d273ca201 100644 --- a/board/freescale/common/vsc3316_3308.c +++ b/board/freescale/common/vsc3316_3308.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #include "vsc3316_3308.h" @@ -32,7 +33,22 @@ int vsc_if_enable(unsigned int vsc_addr) /* enable 2-wire Serial InterFace (I2C) */ data = 0x02; +#ifdef CONFIG_DM_I2C + int ret, bus_num = 0; + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + return dm_i2c_write(dev, INTERFACE_MODE_REG, &data, 1); +#else return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, &data, 1); +#endif } int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2], @@ -45,6 +61,66 @@ int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2], debug("VSC:Initializing VSC3316 at I2C address 0x%2x" " for Tx\n", vsc_addr); +#ifdef CONFIG_DM_I2C + int bus_num = 0; + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1); + if (ret < 0) { + printf("VSC:0x%x could not read REV_ID from device.\n", + vsc_addr); + return ret; + } + + if (rev_id != 0xab) { + printf("VSC: device at address 0x%x is not VSC3316/3308.\n", + vsc_addr); + return -ENODEV; + } + + ret = vsc_if_enable(vsc_addr); + if (ret) { + printf("VSC:0x%x could not configured for 2-wire I/F.\n", + vsc_addr); + return ret; + } + + /* config connections - page 0x00 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); + + /* Making crosspoint connections, by connecting required + * input to output + */ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]); + + /* input state - page 0x13 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); + /* Configuring the required input of the switch */ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][0], 0x80); + + /* Setting Global Input LOS threshold value */ + dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0x60); + + /* config output mode - page 0x23 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); + /* Turn ON the Output driver correspond to required output*/ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][1], 0); + + /* configure global core control register, Turn on Global core power */ + dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0); + +#else ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); if (ret < 0) { printf("VSC:0x%x could not read REV_ID from device.\n", @@ -90,6 +166,7 @@ int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2], /* configure global core control register, Turn on Global core power */ i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); +#endif vsc_wp_config(vsc_addr); @@ -107,6 +184,105 @@ int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2], debug("VSC:Initializing VSC3308 at I2C address 0x%x for Tx\n", vsc_addr); +#ifdef CONFIG_DM_I2C + int bus_num = 0; + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1); + if (ret < 0) { + printf("VSC:0x%x could not read REV_ID from device.\n", + vsc_addr); + return ret; + } + + if (rev_id != 0xab) { + printf("VSC: device at address 0x%x is not VSC3316/3308.\n", + vsc_addr); + return -ENODEV; + } + + ret = vsc_if_enable(vsc_addr); + if (ret) { + printf("VSC:0x%x could not configured for 2-wire I/F.\n", + vsc_addr); + return ret; + } + + /* config connections - page 0x00 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); + + /* Configure Global Input ISE */ + dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE1, 0); + dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE2, 0); + + /* Configure Tx/Rx Global Output PE1 */ + dm_i2c_reg_write(dev, GLOBAL_OUTPUT_PE1, 0); + + /* Configure Tx/Rx Global Output PE2 */ + dm_i2c_reg_write(dev, GLOBAL_OUTPUT_PE2, 0); + + /* Configure Tx/Rx Global Input GAIN */ + dm_i2c_reg_write(dev, GLOBAL_INPUT_GAIN, 0x3F); + + /* Setting Global Input LOS threshold value */ + dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0xE0); + + /* Setting Global output termination */ + dm_i2c_reg_write(dev, GLOBAL_OUTPUT_TERMINATION, 0); + + /* Configure Tx/Rx Global Output level */ + if (vsc_addr == VSC3308_TX_ADDRESS) + dm_i2c_reg_write(dev, GLOBAL_OUTPUT_LEVEL, 4); + else + dm_i2c_reg_write(dev, GLOBAL_OUTPUT_LEVEL, 2); + + /* Making crosspoint connections, by connecting required + * input to output + */ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]); + + /* input state - page 0x13 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); + /* Turning off all the required input of the switch */ + for (i = 0; i < num_con; i++) + dm_i2c_reg_write(dev, con_arr[i][0], 1); + + /* only turn on specific Tx/Rx requested by the XFI erratum */ + if (vsc_addr == VSC3308_TX_ADDRESS) { + dm_i2c_reg_write(dev, 2, 0); + dm_i2c_reg_write(dev, 3, 0); + } else { + dm_i2c_reg_write(dev, 0, 0); + dm_i2c_reg_write(dev, 1, 0); + } + + /* config output mode - page 0x23 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); + /* Turn off the Output driver correspond to required output*/ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][1], 1); + + /* only turn on specific Tx/Rx requested by the XFI erratum */ + if (vsc_addr == VSC3308_TX_ADDRESS) { + dm_i2c_reg_write(dev, 0, 0); + dm_i2c_reg_write(dev, 1, 0); + } else { + dm_i2c_reg_write(dev, 3, 0); + dm_i2c_reg_write(dev, 4, 0); + } + + /* configure global core control register, Turn on Global core power */ + dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0); +#else ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); if (ret < 0) { printf("VSC:0x%x could not read REV_ID from device.\n", @@ -192,7 +368,7 @@ int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2], /* configure global core control register, Turn on Global core power */ i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); - +#endif vsc_wp_config(vsc_addr); return 0; @@ -208,7 +384,69 @@ int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2], debug("VSC:Initializing VSC3308 at I2C address 0x%x" " for Tx\n", vsc_addr); +#ifdef CONFIG_DM_I2C + int bus_num = 0; + struct udevice *dev; + ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1); + if (ret < 0) { + printf("VSC:0x%x could not read REV_ID from device.\n", + vsc_addr); + return ret; + } + + if (rev_id != 0xab) { + printf("VSC: device at address 0x%x is not VSC3316/3308.\n", + vsc_addr); + return -ENODEV; + } + + ret = vsc_if_enable(vsc_addr); + if (ret) { + printf("VSC:0x%x could not configured for 2-wire I/F.\n", + vsc_addr); + return ret; + } + + /* config connections - page 0x00 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); + + /* Making crosspoint connections, by connecting required + * input to output + */ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]); + + /*Configure Global Input ISE and gain */ + dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE1, 0x12); + dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE2, 0x12); + + /* input state - page 0x13 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); + /* Turning ON the required input of the switch */ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][0], 0); + + /* Setting Global Input LOS threshold value */ + dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0x60); + + /* config output mode - page 0x23 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); + /* Turn ON the Output driver correspond to required output*/ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][1], 0); + + /* configure global core control register, Turn on Global core power */ + dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0); +#else ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); if (ret < 0) { printf("VSC:0x%x could not read REV_ID from device.\n", @@ -258,7 +496,7 @@ int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2], /* configure global core control register, Turn on Global core power */ i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); - +#endif vsc_wp_config(vsc_addr); return 0; @@ -270,6 +508,22 @@ void vsc_wp_config(unsigned int vsc_addr) /* For new crosspoint configuration to occur, WP bit of * CORE_CONFIG_REG should be set 1 and then reset to 0 */ +#ifdef CONFIG_DM_I2C + int ret, bus_num = 0; + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return; + } + + dm_i2c_reg_write(dev, CORE_CONFIG_REG, 0x01); + dm_i2c_reg_write(dev, CORE_CONFIG_REG, 0x0); +#else i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x01); i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x0); +#endif } diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index 5608774afd1..869c01de92b 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2009-2012 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #include @@ -91,11 +92,25 @@ int checkboard(void) return 0; } -int select_i2c_ch_pca9547(u8 ch) +int select_i2c_ch_pca9547(u8 ch, int bus_num) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + ret = dm_i2c_write(dev, 0, &ch, 1); +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -115,10 +130,28 @@ static inline int read_voltage(void) { int i, ret, voltage_read = 0; u16 vol_mon; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int bus_num = 0; +#endif for (i = 0; i < NUM_READINGS; i++) { +#ifdef CONFIG_DM_I2C + ret = i2c_get_chip_for_busnum(bus_num, I2C_VOL_MONITOR_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + ret = dm_i2c_read(dev, + I2C_VOL_MONITOR_BUS_V_OFFSET, + (void *)&vol_mon, 2); +#else ret = i2c_read(I2C_VOL_MONITOR_ADDR, I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2); +#endif if (ret) { printf("VID: failed to read core voltage\n"); return ret; @@ -250,7 +283,7 @@ static int adjust_vdd(ulong vdd_override) unsigned voltage; }; - ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR); + ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0); if (ret) { debug("VID: I2c failed to switch channel\n"); ret = -1; @@ -348,7 +381,7 @@ int config_frontside_crossbar_vsc3316(void) u32 srds_prtcl_s1, srds_prtcl_s2; int ret; - ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS); + ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS, 0); if (ret) return ret; @@ -567,7 +600,7 @@ int board_early_init_r(void) /* Configure board SERDES ports crossbar */ config_frontside_crossbar_vsc3316(); config_backside_crossbar_mux(); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); return 0; } @@ -732,11 +765,11 @@ void board_detail(void) } /* Voltage secion */ - if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) { + if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0)) { vdd = read_voltage(); if (vdd > 0) printf("Core voltage= %d mV\n", vdd); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); } printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25); diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 91a7c70356e..5f91a52bbe9 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -280,6 +280,19 @@ unsigned long get_board_ddr_clk(void); #endif /* I2C */ +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#else +#undef CONFIG_SYS_I2C +#undef CONFIG_SYS_FSL_I2C2_OFFSET +#undef CONFIG_SYS_FSL_I2C2_SLAVE +#undef CONFIG_SYS_FSL_I2C2_SPEED +#undef CONFIG_SYS_FSL_I2C_SLAVE +#undef CONFIG_SYS_FSL_I2C_SPEED +#undef CONFIG_SYS_FSL_I2C_OFFSET +#endif + +#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 31cb1cf34a8..ce7634f4ea9 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ /* @@ -159,12 +160,18 @@ #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif + +#define CONFIG_SYS_I2C_FSL /* * General PCI From 30ea84768b678c64fbd890b952b719bf3b8d9dc0 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:18 +0800 Subject: [PATCH 156/237] configs: T4240RDB: enable DM_I2C This enable DM_I2C in T4240RDB defconfigs Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/T4240RDB_SDCARD_defconfig | 1 + configs/T4240RDB_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index 646cd88793a..33432d14cff 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -71,3 +71,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index d74afc71eb0..a47615e12f4 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -59,3 +59,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y From 8e4be6dfb755bda97bea4d4b211c4aaabe08b730 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:19 +0800 Subject: [PATCH 157/237] dm: powerpc: T2080/T2081: add i2c DM support This supports i2c DM for SoC T2080/T2081 Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/powerpc/dts/t2080.dtsi | 4 +++- board/freescale/t208xqds/t208xqds.c | 19 ++++++++++++++++--- include/configs/T208xQDS.h | 7 ++++++- include/configs/T208xRDB.h | 10 +++++++++- 4 files changed, 34 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/dts/t2080.dtsi b/arch/powerpc/dts/t2080.dtsi index 458019ae92f..a9e9b404f66 100644 --- a/arch/powerpc/dts/t2080.dtsi +++ b/arch/powerpc/dts/t2080.dtsi @@ -3,7 +3,7 @@ * T2080/T2081 Silicon/SoC Device Tree Source (pre include) * * Copyright 2013 Freescale Semiconductor Inc. - * Copyright 2018 NXP + * Copyright 2018,2020 NXP */ /dts-v1/; @@ -96,6 +96,8 @@ sata-number = <2>; sata-fpdma = <0>; }; + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" }; pcie@ffe240000 { diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index 79cc1543f95..91004010223 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2009-2013 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #include @@ -75,11 +76,23 @@ int checkboard(void) return 0; } -int select_i2c_ch_pca9547(u8 ch) +int select_i2c_ch_pca9547(u8 ch, int bus_num) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + ret = dm_i2c_write(dev, 0, &ch, 1); +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -90,7 +103,7 @@ int select_i2c_ch_pca9547(u8 ch) int i2c_multiplexer_select_vid_channel(u8 channel) { - return select_i2c_ch_pca9547(channel); + return select_i2c_ch_pca9547(channel, 0); } int brd_mux_lane_to_slot(void) @@ -368,7 +381,7 @@ int board_early_init_r(void) printf("Warning: Adjusting core voltage failed.\n"); brd_mux_lane_to_slot(); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); return 0; } diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 96801e5f099..aed2e87a1a1 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2011-2013 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ /* @@ -385,8 +386,8 @@ unsigned long get_board_ddr_clk(void); /* * I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F @@ -399,6 +400,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_I2C2_SPEED 100000 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 +#endif + +#define CONFIG_SYS_I2C_FSL + #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index a90ea11a2f8..e0ef2b25a19 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ /* @@ -333,8 +334,8 @@ unsigned long get_board_ddr_clk(void); /* * I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F @@ -347,6 +348,13 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_I2C2_SPEED 100000 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif + +#define CONFIG_SYS_I2C_FSL + #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ From 613e66eb80c2cb0f9c1db408ecd4c08e8fae5790 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:20 +0800 Subject: [PATCH 158/237] configs: T2080: enable DM_I2C This enables DM_I2C in T2080 defconfigs Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/T2080QDS_NAND_defconfig | 1 + configs/T2080QDS_SDCARD_defconfig | 1 + configs/T2080QDS_SECURE_BOOT_defconfig | 1 + configs/T2080QDS_SPIFLASH_defconfig | 1 + configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 1 + configs/T2080QDS_defconfig | 1 + configs/T2080RDB_NAND_defconfig | 1 + configs/T2080RDB_SDCARD_defconfig | 1 + configs/T2080RDB_SPIFLASH_defconfig | 1 + configs/T2080RDB_defconfig | 1 + 10 files changed, 10 insertions(+) diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index dc836642859..0b2e01bb0eb 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -80,3 +80,4 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_I2C=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 24359ed1a4b..33eb4cdddbd 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -77,3 +77,4 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_I2C=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index cc2449a25f6..4119bfbd1f9 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -67,3 +67,4 @@ CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y +CONFIG_DM_I2C=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 5d159607a89..7183728251c 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -80,3 +80,4 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_I2C=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index c3fef7afe34..aa0c4e3106f 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -57,3 +57,4 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_I2C=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index 9cf28152994..1f00e6ad7ce 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -65,3 +65,4 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_I2C=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 292a3beb41a..f7206a9cbb6 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -79,3 +79,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index b53a0ada3da..af528c22fd5 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -76,3 +76,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index ddf273f5458..d1dca225bcc 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -79,3 +79,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index c81f546f52d..ebb6239fa66 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -63,3 +63,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_I2C=y From d2e3f7c608b86fbbc027e46acb431abfba304333 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:21 +0800 Subject: [PATCH 159/237] dm: powerpc: T1040/T1042: add i2c DM support This supports i2c DM for SoC T1040/T1042 Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/powerpc/dts/t104x.dtsi | 4 +++- board/freescale/t1040qds/diu.c | 5 +++-- board/freescale/t1040qds/t1040qds.c | 18 ++++++++++++++++-- board/freescale/t1040qds/t1040qds.h | 3 ++- include/configs/T1040QDS.h | 7 +++++++ include/configs/T104xRDB.h | 10 +++++++++- 6 files changed, 40 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi index 093aaab834b..0a08a69f31a 100644 --- a/arch/powerpc/dts/t104x.dtsi +++ b/arch/powerpc/dts/t104x.dtsi @@ -3,7 +3,7 @@ * T104X Silicon/SoC Device Tree Source (pre include) * * Copyright 2013 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ /dts-v1/; @@ -85,6 +85,8 @@ reg = <0x114000 0x1000>; clock-frequency = <0>; }; + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" }; pcie@ffe240000 { diff --git a/board/freescale/t1040qds/diu.c b/board/freescale/t1040qds/diu.c index ab9e922a927..0b1aeed69e4 100644 --- a/board/freescale/t1040qds/diu.c +++ b/board/freescale/t1040qds/diu.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP * Author: Priyanka Jain */ @@ -48,7 +49,7 @@ void diu_set_pixel_clock(unsigned int pixclock) /* Program HDMI encoder */ /* Switch channel to DIU */ - select_i2c_ch_pca9547(I2C_MUX_CH_DIU); + select_i2c_ch_pca9547(I2C_MUX_CH_DIU, 0); /* Set dispaly encoder */ ret = diu_set_dvi_encoder(temp); @@ -58,7 +59,7 @@ void diu_set_pixel_clock(unsigned int pixclock) } /* Switch channel to default */ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); /* Program pixel clock */ out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index 92dd9237ec7..9e253fdec27 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #include @@ -79,11 +80,24 @@ int checkboard(void) return 0; } -int select_i2c_ch_pca9547(u8 ch) +int select_i2c_ch_pca9547(u8 ch, int bus_num) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + ret = dm_i2c_write(dev, 0, &ch, 1); +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -154,7 +168,7 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); return 0; } diff --git a/board/freescale/t1040qds/t1040qds.h b/board/freescale/t1040qds/t1040qds.h index d2f0203f177..781bcdefc93 100644 --- a/board/freescale/t1040qds/t1040qds.h +++ b/board/freescale/t1040qds/t1040qds.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #ifndef __T1040_QDS_H__ @@ -8,6 +9,6 @@ void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, bd_t *bd); -int select_i2c_ch_pca9547(u8 ch); +int select_i2c_ch_pca9547(u8 ch, int bus_bum); #endif diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index cda8251036e..ad8efb3503d 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -1,5 +1,6 @@ /* * Copyright 2013-2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP * * See file CREDITS for list of people who contributed to this * project. @@ -360,6 +361,8 @@ unsigned long get_board_ddr_clk(void); #endif /* I2C */ + +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ @@ -374,6 +377,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 +#endif + +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define I2C_MUX_PCA_ADDR 0x77 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ @@ -385,6 +391,7 @@ unsigned long get_board_ddr_clk(void); /* LDI/DVI Encoder for display */ #define CONFIG_SYS_I2C_LDI_ADDR 0x38 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 +#define CONFIG_SYS_I2C_DVI_BUS_NUM 0 /* * RTC configuration diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index bc651186578..7d15910f659 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #ifndef __CONFIG_H @@ -27,6 +28,7 @@ #define CONFIG_SPL_SKIP_RELOCATE #define CONFIG_SPL_COMMON_INIT_DDR #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#undef CONFIG_DM_I2C #endif #define RESET_VECTOR_OFFSET 0x27FFC #define BOOT_PAGE_OFFSET 0x27000 @@ -459,8 +461,8 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #endif /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C2_SPEED 400000 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 @@ -473,7 +475,12 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ /* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 #define I2C_MUX_CH_DEFAULT 0x8 @@ -484,6 +491,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg /* LDI/DVI Encoder for display */ #define CONFIG_SYS_I2C_LDI_ADDR 0x38 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 +#define CONFIG_SYS_I2C_DVI_BUS_NUM 0 /* * RTC configuration From a45fa9e8008506ba9f670611aa6efe8e31bd196d Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:22 +0800 Subject: [PATCH 160/237] configs: T1042D4RDB: enable DM_I2C and DM_RTC This enables DM_I2C and DM_RTC in T1042D4RDB defconfigs, except T1042D4RDB SECURE_BOOT defconfig Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/T1042D4RDB_NAND_defconfig | 2 ++ configs/T1042D4RDB_SDCARD_defconfig | 2 ++ configs/T1042D4RDB_SPIFLASH_defconfig | 2 ++ configs/T1042D4RDB_defconfig | 2 ++ 4 files changed, 8 insertions(+) diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index f5a3c440388..26d342db761 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -82,3 +82,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 18e51b1d604..5c6ef3527b1 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -79,3 +79,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 093d233b7c2..7b6e375ed92 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -82,3 +82,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 95160cdd16c..3e2156b6ca7 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -67,3 +67,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_DM_I2C=y +CONFIG_DM_RTC=y From d2d019b7c33d9dfa474cc13f2d8c0bcab7a73a04 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 1 May 2020 19:06:26 +0800 Subject: [PATCH 161/237] powerpc: Enable device tree support for P1010RDB Add device tree for P1010RDB boards and enable CONFIG_OF_CONTROL so that device tree can be compiled. Signed-off-by: Hou Zhiqiang Reviewed-by: Priyanka Jain --- arch/powerpc/dts/Makefile | 2 + arch/powerpc/dts/p1010rdb-pa.dts | 17 ++++++++ arch/powerpc/dts/p1010rdb-pa_36b.dts | 17 ++++++++ arch/powerpc/dts/p1010rdb-pb.dts | 17 ++++++++ arch/powerpc/dts/p1010rdb-pb_36b.dts | 17 ++++++++ arch/powerpc/dts/p1010rdb_32b.dtsi | 22 ++++++++++ arch/powerpc/dts/p1010rdb_36b.dtsi | 22 ++++++++++ arch/powerpc/dts/p1010si-post.dtsi | 46 ++++++++++++++++++++ arch/powerpc/dts/p1010si-pre.dtsi | 27 ++++++++++++ configs/P1010RDB-PA_36BIT_NAND_defconfig | 3 +- configs/P1010RDB-PA_36BIT_NOR_defconfig | 4 +- configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 3 +- configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 3 +- configs/P1010RDB-PA_NAND_defconfig | 3 +- configs/P1010RDB-PA_NOR_defconfig | 4 +- configs/P1010RDB-PA_SDCARD_defconfig | 3 +- configs/P1010RDB-PA_SPIFLASH_defconfig | 3 +- configs/P1010RDB-PB_36BIT_NAND_defconfig | 3 +- configs/P1010RDB-PB_36BIT_NOR_defconfig | 4 +- configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 3 +- configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 3 +- configs/P1010RDB-PB_NAND_defconfig | 3 +- configs/P1010RDB-PB_NOR_defconfig | 4 +- configs/P1010RDB-PB_SDCARD_defconfig | 3 +- configs/P1010RDB-PB_SPIFLASH_defconfig | 3 +- 25 files changed, 223 insertions(+), 16 deletions(-) create mode 100644 arch/powerpc/dts/p1010rdb-pa.dts create mode 100644 arch/powerpc/dts/p1010rdb-pa_36b.dts create mode 100644 arch/powerpc/dts/p1010rdb-pb.dts create mode 100644 arch/powerpc/dts/p1010rdb-pb_36b.dts create mode 100644 arch/powerpc/dts/p1010rdb_32b.dtsi create mode 100644 arch/powerpc/dts/p1010rdb_36b.dtsi create mode 100644 arch/powerpc/dts/p1010si-post.dtsi create mode 100644 arch/powerpc/dts/p1010si-pre.dtsi diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 3195351c9c3..7eb005f4501 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb +dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb +dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb diff --git a/arch/powerpc/dts/p1010rdb-pa.dts b/arch/powerpc/dts/p1010rdb-pa.dts new file mode 100644 index 00000000000..c66c4923ac3 --- /dev/null +++ b/arch/powerpc/dts/p1010rdb-pa.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010 RDB Device Tree Source + * + * Copyright 2020 NXP + */ + +/include/ "p1010si-pre.dtsi" + +/ { + model = "fsl,P1010RDB"; + compatible = "fsl,P1010RDB"; + + /include/ "p1010rdb_32b.dtsi" +}; + +/include/ "p1010si-post.dtsi" diff --git a/arch/powerpc/dts/p1010rdb-pa_36b.dts b/arch/powerpc/dts/p1010rdb-pa_36b.dts new file mode 100644 index 00000000000..b943de7cbb2 --- /dev/null +++ b/arch/powerpc/dts/p1010rdb-pa_36b.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010 RDB Device Tree Source (36-bit address map) + * + * Copyright 2020 NXP + */ + +/include/ "p1010si-pre.dtsi" + +/ { + model = "fsl,P1010RDB"; + compatible = "fsl,P1010RDB"; + + /include/ "p1010rdb_36b.dtsi" +}; + +/include/ "p1010si-post.dtsi" diff --git a/arch/powerpc/dts/p1010rdb-pb.dts b/arch/powerpc/dts/p1010rdb-pb.dts new file mode 100644 index 00000000000..2675d5d92b9 --- /dev/null +++ b/arch/powerpc/dts/p1010rdb-pb.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010RDB Device Tree Source + * + * Copyright 2020 NXP + */ + +/include/ "p1010si-pre.dtsi" + +/ { + model = "fsl,P1010RDB-PB"; + compatible = "fsl,P1010RDB-PB"; + + /include/ "p1010rdb_32b.dtsi" +}; + +/include/ "p1010si-post.dtsi" diff --git a/arch/powerpc/dts/p1010rdb-pb_36b.dts b/arch/powerpc/dts/p1010rdb-pb_36b.dts new file mode 100644 index 00000000000..45ccf91c41d --- /dev/null +++ b/arch/powerpc/dts/p1010rdb-pb_36b.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010 RDB Device Tree Source (36-bit address map) + * + * Copyright 2020 NXP + */ + +/include/ "p1010si-pre.dtsi" + +/ { + model = "fsl,P1010RDB-PB"; + compatible = "fsl,P1010RDB-PB"; + + /include/ "p1010rdb_36b.dtsi" +}; + +/include/ "p1010si-post.dtsi" diff --git a/arch/powerpc/dts/p1010rdb_32b.dtsi b/arch/powerpc/dts/p1010rdb_32b.dtsi new file mode 100644 index 00000000000..5da790da5e1 --- /dev/null +++ b/arch/powerpc/dts/p1010rdb_32b.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010RDB Device Tree Source + * + * Copyright 2020 NXP + */ + +soc: soc@ffe00000 { + ranges = <0x0 0x0 0xffe00000 0x100000>; +}; + +pci1: pcie@ffe09000 { + reg = <0 0xffe09000 0 0x1000>; + ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; +}; + +pci0: pcie@ffe0a000 { + reg = <0 0xffe0a000 0 0x1000>; + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; +}; diff --git a/arch/powerpc/dts/p1010rdb_36b.dtsi b/arch/powerpc/dts/p1010rdb_36b.dtsi new file mode 100644 index 00000000000..54dd16e43b3 --- /dev/null +++ b/arch/powerpc/dts/p1010rdb_36b.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010RDB Device Tree Source (36-bit address map) + * + * Copyright 2020 NXP + */ + +soc: soc@fffe00000 { + ranges = <0x0 0xf 0xffe00000 0x100000>; +}; + +pci1: pcie@fffe09000 { + reg = <0xf 0xffe09000 0 0x1000>; + ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; +}; + +pci0: pcie@fffe0a000 { + reg = <0xf 0xffe0a000 0 0x1000>; + ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; +}; diff --git a/arch/powerpc/dts/p1010si-post.dtsi b/arch/powerpc/dts/p1010si-post.dtsi new file mode 100644 index 00000000000..e24b5e4063b --- /dev/null +++ b/arch/powerpc/dts/p1010si-post.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2020 NXP + */ + +&soc { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,p1010-immr", "simple-bus"; + bus-frequency = <0>; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic"; + device_type = "open-pic"; + big-endian; + single-cpu-affinity; + last-interrupt-source = <255>; + }; +}; + +/* controller at 0x9000 */ +&pci1 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; + +/* controller at 0xa000 */ +&pci0 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; diff --git a/arch/powerpc/dts/p1010si-pre.dtsi b/arch/powerpc/dts/p1010si-pre.dtsi new file mode 100644 index 00000000000..9d7bb6c95d9 --- /dev/null +++ b/arch/powerpc/dts/p1010si-pre.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2020 NXP + */ + +/dts-v1/; + +/include/ "e500v2_power_isa.dtsi" + +/ { + compatible = "fsl,P1010"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,P1010@0 { + device_type = "cpu"; + reg = <0x0>; + }; + }; +}; diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index 85b97d1e15f..b0dd5f8f7e6 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -10,6 +10,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" @@ -76,6 +78,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index e1109637c13..93042f8cc8f 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -57,6 +60,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 4b8ddd997c2..657b10033b6 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -11,6 +11,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -70,6 +72,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 2975f404fcd..396921722da 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -72,6 +74,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index 632ecd7af54..b080bb726be 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -10,6 +10,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" +CONFIG_OF_CONTROL=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_FIT=y @@ -75,6 +77,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index 037fe0ab890..a5296a53a5c 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -56,6 +59,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 48a1d34cc9a..1df83cefe3d 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -11,6 +11,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -69,6 +71,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index f43c60011ce..6bff366f817 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -71,6 +73,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index dd7d6891633..abf8882f21d 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -10,6 +10,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" @@ -76,6 +78,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 7e8c150603e..beb8f098c49 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -57,6 +60,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 7996490e936..7244dacec0b 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -11,6 +11,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -70,6 +72,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 4291002d343..1d40aa054b8 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -72,6 +74,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 4a216dd55bc..0d9df36ea1f 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -10,6 +10,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" +CONFIG_OF_CONTROL=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_FIT=y @@ -75,6 +77,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 2cc52ed76de..653c89bfdd4 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -56,6 +59,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index d90cc8e7bbf..7bc05e57baa 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -11,6 +11,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -69,6 +71,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index e6833d43e35..16976e4a881 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -71,6 +73,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y From 177edd82b2dad578b2df212189ff94d6b9f47b61 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 1 May 2020 19:06:27 +0800 Subject: [PATCH 162/237] powerpc: P1010RDB: Compile legacy PCIe routines conditionally Compile the legacy PCIe initialization reoutines for P1010RDB boards only when DM_PCI is not enabled. Signed-off-by: Hou Zhiqiang Reviewed-by: Priyanka Jain --- board/freescale/p1010rdb/p1010rdb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 65ac47263ec..314646d4ff4 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -125,7 +125,7 @@ int board_early_init_r(void) return 0; } -#ifdef CONFIG_PCI +#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -611,7 +611,7 @@ int ft_board_setup(void *blob, bd_t *bd) base = env_get_bootm_low(); size = env_get_bootm_size(); -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) FT_FSL_PCI_SETUP; #endif From 9de7c76bba69dcf46cb9f382d7588b314c78bb10 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 1 May 2020 19:06:28 +0800 Subject: [PATCH 163/237] powerpc: P1010RDB: Disable legacy PCIe driver when DM_PCI is enabled Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled for P1010RDB board. Signed-off-by: Hou Zhiqiang Reviewed-by: Priyanka Jain --- include/configs/P1010RDB.h | 42 +++++++++++++++++++++++--------------- 1 file changed, 26 insertions(+), 16 deletions(-) diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 41dbbedecc4..ce48ae1ef90 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -114,8 +114,6 @@ #if defined(CONFIG_PCI) #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* @@ -123,19 +121,13 @@ * Memory space is mapped 1-1, but I/O space must start from 0. */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull #else @@ -143,27 +135,45 @@ #endif /* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#endif + +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ +#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + #if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" #elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" #endif -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ From fc888ac7d5016ce10346077514dc0777ef47d294 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 1 May 2020 19:06:29 +0800 Subject: [PATCH 164/237] configs: P1010RDB: Enable PCIe driver Enable the DM PCIe driver in P1010RDB defconfigs. Signed-off-by: Hou Zhiqiang Reviewed-by: Priyanka Jain --- configs/P1010RDB-PA_36BIT_NAND_defconfig | 4 ++++ configs/P1010RDB-PA_36BIT_NOR_defconfig | 4 ++++ configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 4 ++++ configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 4 ++++ configs/P1010RDB-PA_NAND_defconfig | 4 ++++ configs/P1010RDB-PA_NOR_defconfig | 4 ++++ configs/P1010RDB-PA_SDCARD_defconfig | 4 ++++ configs/P1010RDB-PA_SPIFLASH_defconfig | 4 ++++ configs/P1010RDB-PB_36BIT_NAND_defconfig | 4 ++++ configs/P1010RDB-PB_36BIT_NOR_defconfig | 4 ++++ configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 4 ++++ configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 4 ++++ configs/P1010RDB-PB_NAND_defconfig | 4 ++++ configs/P1010RDB-PB_NOR_defconfig | 4 ++++ configs/P1010RDB-PB_SDCARD_defconfig | 4 ++++ configs/P1010RDB-PB_SPIFLASH_defconfig | 4 ++++ 16 files changed, 64 insertions(+) diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index b0dd5f8f7e6..5280a1d070a 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -71,6 +71,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index 93042f8cc8f..b83e99f8f76 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -53,6 +53,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 657b10033b6..a1b08b17f92 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -65,6 +65,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 396921722da..2b336f4a92c 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -67,6 +67,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index b080bb726be..6062fd8d0f6 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -70,6 +70,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index a5296a53a5c..4ee53e85f78 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -52,6 +52,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 1df83cefe3d..f4e89592b8a 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -64,6 +64,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index 6bff366f817..6d4175e2d1d 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -66,6 +66,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index abf8882f21d..123c044cf78 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -71,6 +71,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index beb8f098c49..1e149f965db 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -53,6 +53,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 7244dacec0b..aeb7e16467a 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -65,6 +65,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 1d40aa054b8..7b6aaf64cbe 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -67,6 +67,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 0d9df36ea1f..0af9e1795aa 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -69,6 +69,10 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 653c89bfdd4..73fe54d13a3 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -51,6 +51,10 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 7bc05e57baa..d373cd28902 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -64,6 +64,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index 16976e4a881..88fc5fe5aee 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -66,6 +66,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y From d76485b9411a680be2a25e1bc4f8da36619815dd Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 19 Apr 2020 09:19:04 +0200 Subject: [PATCH 165/237] doc: fix references to README.qe_firmware In two files README.qe_firmware is referenced which never made it into the U-Boot tree. The README is available in the Linux kernel tree. Update the references. Cc: Timur Tabi Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass Reviewed-by: Priyanka Jain --- drivers/qe/qe.c | 6 ++++-- include/fsl_qe.h | 3 ++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 24549ece653..fbad124b51c 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -440,7 +440,8 @@ static void qe_upload_microcode(const void *base, /* * Upload a microcode to the I-RAM at a specific address. * - * See docs/README.qe_firmware for information on QE microcode uploading. + * See Documentation/powerpc/qe_firmware.rst in the Linux kernel tree for + * information on QE microcode uploading. * * Currently, only version 1 is supported, so the 'version' field must be * set to 1. @@ -579,7 +580,8 @@ int qe_upload_firmware(const struct qe_firmware *firmware) /* * Upload a microcode to the I-RAM at a specific address. * - * See docs/README.qe_firmware for information on QE microcode uploading. + * See Documentation/powerpc/qe_firmware.rst in the Linux kernel tree for + * information on QE microcode uploading. * * Currently, only version 1 is supported, so the 'version' field must be * set to 1. diff --git a/include/fsl_qe.h b/include/fsl_qe.h index d4eba824365..6e44cbdb562 100644 --- a/include/fsl_qe.h +++ b/include/fsl_qe.h @@ -227,7 +227,8 @@ typedef enum qe_clock { /* Structure that defines QE firmware binary files. * - * See doc/README.qe_firmware for a description of these fields. + * See Documentation/powerpc/qe_firmware.rst in the Linux kernel tree for + * a description of these fields. */ struct qe_firmware { struct qe_header { From 9e36eae1249f477275a607736eda75e663d1b57c Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Sun, 12 Apr 2020 17:05:28 +0800 Subject: [PATCH 166/237] powerpc: dts: p1010: add i2c node Add i2c node of p1010 Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p1010rdb-pb.dts | 1 + arch/powerpc/dts/p1010rdb-pb_36b.dts | 1 + arch/powerpc/dts/p1010rdb.dtsi | 14 ++++++++++++++ arch/powerpc/dts/p1010si-post.dtsi | 2 ++ 4 files changed, 18 insertions(+) create mode 100644 arch/powerpc/dts/p1010rdb.dtsi diff --git a/arch/powerpc/dts/p1010rdb-pb.dts b/arch/powerpc/dts/p1010rdb-pb.dts index 2675d5d92b9..9ca562534ff 100644 --- a/arch/powerpc/dts/p1010rdb-pb.dts +++ b/arch/powerpc/dts/p1010rdb-pb.dts @@ -15,3 +15,4 @@ }; /include/ "p1010si-post.dtsi" +/include/ "p1010rdb.dtsi" diff --git a/arch/powerpc/dts/p1010rdb-pb_36b.dts b/arch/powerpc/dts/p1010rdb-pb_36b.dts index 45ccf91c41d..eeff2a87044 100644 --- a/arch/powerpc/dts/p1010rdb-pb_36b.dts +++ b/arch/powerpc/dts/p1010rdb-pb_36b.dts @@ -15,3 +15,4 @@ }; /include/ "p1010si-post.dtsi" +/include/ "p1010rdb.dtsi" diff --git a/arch/powerpc/dts/p1010rdb.dtsi b/arch/powerpc/dts/p1010rdb.dtsi new file mode 100644 index 00000000000..4f58ee24460 --- /dev/null +++ b/arch/powerpc/dts/p1010rdb.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010RDB Device Tree Source + * + * Copyright 2020 NXP + */ +&soc { + i2c@3000 { + rtc@68 { + compatible = "pericom,pt7c4338"; + reg = <0x68>; + }; + }; +}; diff --git a/arch/powerpc/dts/p1010si-post.dtsi b/arch/powerpc/dts/p1010si-post.dtsi index e24b5e4063b..02894413818 100644 --- a/arch/powerpc/dts/p1010si-post.dtsi +++ b/arch/powerpc/dts/p1010si-post.dtsi @@ -23,6 +23,8 @@ single-cpu-affinity; last-interrupt-source = <255>; }; +/include/ "pq3-i2c-0.dtsi" +/include/ "pq3-i2c-1.dtsi" }; /* controller at 0x9000 */ From f49ac7e1c4107b88f30ab34b039e1c7ebff2d469 Mon Sep 17 00:00:00 2001 From: Jakov Petrina Date: Fri, 24 Apr 2020 11:24:08 +0200 Subject: [PATCH 167/237] arm: dts: uDPU: switch default PHY speed to 3.125Gbit This resolves issues with certain SFP modules. Signed-off-by: Jakov Petrina Signed-off-by: Vladimir Vid Reviewed-by: Stefan Roese --- arch/arm/dts/armada-3720-uDPU.dts | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/arch/arm/dts/armada-3720-uDPU.dts b/arch/arm/dts/armada-3720-uDPU.dts index 683dac2a7c1..07c7b91175a 100644 --- a/arch/arm/dts/armada-3720-uDPU.dts +++ b/arch/arm/dts/armada-3720-uDPU.dts @@ -109,11 +109,11 @@ &comphy { phy0 { phy-type = ; - phy-speed = ; + phy-speed = ; }; phy1 { phy-type = ; - phy-speed = ; + phy-speed = ; }; phy2 { @@ -125,22 +125,16 @@ ð0 { pinctrl-0 = <&pcie_pins>; status = "okay"; - phy-mode = "sgmii"; + phy-mode = "2500base-x"; + managed = "in-band-status"; phy = <ðphy0>; - fixed-link { - speed = <1000>; - full-duplex; - }; }; ð1 { status = "okay"; - phy-mode = "sgmii"; + phy-mode = "2500base-x"; + managed = "in-band-status"; phy = <ðphy1>; - fixed-link { - speed = <1000>; - full-duplex; - }; }; &i2c0 { From b40745e5c29a45ebe7efce53a1e3ba751d0ef351 Mon Sep 17 00:00:00 2001 From: Joel Johnson Date: Sat, 25 Apr 2020 20:54:56 -0600 Subject: [PATCH 168/237] cmd: mvebu: bubt: fix quoted string split across lines Update quoted string alignment to address checkpatch.pl warning originally introduced in commit f60a66ef5d7d ("cmd: mvebu: bubt: show image boot device"). Signed-off-by: Joel Johnson Reviewed-by: Simon Glass --- cmd/mvebu/bubt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c index dc0ce01c358..ef53153c46b 100644 --- a/cmd/mvebu/bubt.c +++ b/cmd/mvebu/bubt.c @@ -730,8 +730,8 @@ static int bubt_check_boot_mode(const struct bubt_dev *dst) for (int i = 0; i < ARRAY_SIZE(a38x_boot_modes); i++) { if (a38x_boot_modes[i].id == hdr->blockid) { - printf("Error: A38x image meant to be " - "booted from \"%s\", not \"%s\"!\n", + printf("Error: A38x image meant to be booted from " + "\"%s\", not \"%s\"!\n", a38x_boot_modes[i].name, dst->name); return -ENOEXEC; } From 7ec0e7b6356b12f495b780ecdb25b14204b62a9f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 30 Apr 2020 21:21:39 -0600 Subject: [PATCH 169/237] x86: Move coreboot-table detection to common 32/64-bit code At present this function is only available in 32-bit code. Move it to the common cpu file so it can be used by 64-bit U-Boot too. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/x86/cpu/cpu.c | 25 +++++++++++++++++++++++++ arch/x86/cpu/i386/cpu.c | 26 +------------------------- 2 files changed, 26 insertions(+), 25 deletions(-) diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 8526e856d7d..2e5d0ddd9f6 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -290,3 +290,28 @@ int reserve_arch(void) return 0; } #endif + +long detect_coreboot_table_at(ulong start, ulong size) +{ + u32 *ptr, *end; + + size /= 4; + for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) { + if (*ptr == 0x4f49424c) /* "LBIO" */ + return (long)ptr; + } + + return -ENOENT; +} + +long locate_coreboot_table(void) +{ + long addr; + + /* We look for LBIO in the first 4K of RAM and again at 960KB */ + addr = detect_coreboot_table_at(0x0, 0x1000); + if (addr < 0) + addr = detect_coreboot_table_at(0xf0000, 0x1000); + + return addr; +} diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 0312a26bbbf..facd4f58a69 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -447,31 +448,6 @@ int x86_cpu_init_f(void) return 0; } -long detect_coreboot_table_at(ulong start, ulong size) -{ - u32 *ptr, *end; - - size /= 4; - for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) { - if (*ptr == 0x4f49424c) /* "LBIO" */ - return (long)ptr; - } - - return -ENOENT; -} - -long locate_coreboot_table(void) -{ - long addr; - - /* We look for LBIO in the first 4K of RAM and again at 960KB */ - addr = detect_coreboot_table_at(0x0, 0x1000); - if (addr < 0) - addr = detect_coreboot_table_at(0xf0000, 0x1000); - - return addr; -} - int x86_cpu_reinit_f(void) { setup_identity(); From c2018cdd717732f3fc4b2bb9005d8c2e73088762 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 30 Apr 2020 21:21:40 -0600 Subject: [PATCH 170/237] x86: Allow building an SPL image for coreboot Coreboot runs in 32-bit mode and cannot run a 64-bit U-Boot. To get around this we can build a combined image with 32-bit SPL and 64-bit U-Boot. Add a build rule and binman definition for this. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- Makefile | 6 ++++++ arch/x86/cpu/coreboot/Kconfig | 1 + arch/x86/dts/coreboot-u-boot.dtsi | 18 ++++++++++++++++++ 3 files changed, 25 insertions(+) create mode 100644 arch/x86/dts/coreboot-u-boot.dtsi diff --git a/Makefile b/Makefile index 6bb9cf55f2a..cc99873062f 100644 --- a/Makefile +++ b/Makefile @@ -926,6 +926,9 @@ ALL-$(CONFIG_EFI_STUB) += u-boot-payload.efi ifneq ($(BUILD_ROM)$(CONFIG_BUILD_ROM),) ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom endif +ifeq ($(CONFIG_SYS_COREBOOT)$(CONFIG_SPL),yy) +ALL-$(CONFIG_BINMAN) += u-boot-x86-with-spl.bin +endif # Build a combined spl + u-boot image for sunxi ifeq ($(CONFIG_ARCH_SUNXI)$(CONFIG_SPL),yy) @@ -1626,6 +1629,9 @@ u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.itb FORCE endif endif +u-boot-x86-with-spl.bin: spl/u-boot-spl.bin u-boot.bin FORCE + $(call if_changed,binman) + ifneq ($(CONFIG_TEGRA),) ifneq ($(CONFIG_BINMAN),) # Makes u-boot-dtb-tegra.bin u-boot-tegra.bin u-boot-nodtb-tegra.bin diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig index c8e6a889d02..497d6284ac1 100644 --- a/arch/x86/cpu/coreboot/Kconfig +++ b/arch/x86/cpu/coreboot/Kconfig @@ -25,5 +25,6 @@ config SYS_COREBOOT imply FS_CBFS imply CBMEM_CONSOLE imply X86_TSC_READ_BASE + select BINMAN if X86_64 endif diff --git a/arch/x86/dts/coreboot-u-boot.dtsi b/arch/x86/dts/coreboot-u-boot.dtsi new file mode 100644 index 00000000000..38efc48d836 --- /dev/null +++ b/arch/x86/dts/coreboot-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Google LLC + * Written by Simon Glass + */ + +#include + +/ { + binman { + filename = "u-boot-x86-with-spl.bin"; + u-boot-spl { + }; + u-boot { + offset = <0x10000>; + }; + }; +}; From 37897c4073b408c6e0ea7faa4062b4e6876e9659 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 30 Apr 2020 21:21:41 -0600 Subject: [PATCH 171/237] x86: Move work-around out of cpu_jump_to_64bit_uboot() At present this function copies U-Boot from the last 1MB of ROM. This is not the right way to do it. Instead, the binman symbol should provide the location. But in any case the code should live in the caller, spl_board_load_image(), so that the 64-bit jump function can be used elsewhere. Move it. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/x86/cpu/i386/cpu.c | 10 ---------- arch/x86/lib/spl.c | 13 +++++++++++++ 2 files changed, 13 insertions(+), 10 deletions(-) diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index facd4f58a69..435e50edada 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -614,16 +614,6 @@ int cpu_jump_to_64bit_uboot(ulong target) func = (func_t)ptr; - /* - * Copy U-Boot from ROM - * TODO(sjg@chromium.org): Figure out a way to get the text base - * correctly here, and in the device-tree binman definition. - * - * Also consider using FIT so we get the correct image length and - * parameters. - */ - memcpy((char *)target, (char *)0xfff00000, 0x100000); - /* Jump to U-Boot */ func((ulong)pgtable, 0, (ulong)target); diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 90baec2a175..95a89c072d5 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -207,6 +207,19 @@ static int spl_board_load_image(struct spl_image_info *spl_image, spl_image->os = IH_OS_U_BOOT; spl_image->name = "U-Boot"; + if (!IS_ENABLED(CONFIG_SYS_COREBOOT)) { + /* + * Copy U-Boot from ROM + * TODO(sjg@chromium.org): Figure out a way to get the text base + * correctly here, and in the device-tree binman definition. + * + * Also consider using FIT so we get the correct image length + * and parameters. + */ + memcpy((char *)spl_image->load_addr, (char *)0xfff00000, + 0x100000); + } + debug("Loading to %lx\n", spl_image->load_addr); return 0; From fc486371c3696cf246163fc35e79c740a5d7d1b9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 30 Apr 2020 21:21:42 -0600 Subject: [PATCH 172/237] x86: Update SPL for coreboot At present SPL only works on bare-metal builds. With a few tweaks it can be used for coreboot also. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/x86/lib/spl.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 95a89c072d5..212b4d596d2 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -63,7 +63,7 @@ static int x86_spl_init(void) * is not needed. We could make this a CONFIG option or perhaps * place it immediately below CONFIG_SYS_TEXT_BASE. */ - char *ptr = (char *)0x110000; + __maybe_unused char *ptr = (char *)0x110000; #else struct udevice *punit; #endif @@ -111,7 +111,8 @@ static int x86_spl_init(void) __func__, ret); } -#ifndef CONFIG_TPL +#ifndef CONFIG_SYS_COREBOOT +# ifndef CONFIG_TPL memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start); /* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */ @@ -140,7 +141,7 @@ static int x86_spl_init(void) return ret; } mtrr_commit(true); -#else +# else ret = syscon_get_by_driver_data(X86_SYSCON_PUNIT, &punit); if (ret) debug("Could not find PUNIT (err=%d)\n", ret); @@ -148,6 +149,7 @@ static int x86_spl_init(void) ret = set_max_freq(); if (ret) debug("Failed to set CPU frequency (err=%d)\n", ret); +# endif #endif return 0; @@ -162,7 +164,7 @@ void board_init_f(ulong flags) debug("Error %d\n", ret); panic("x86_spl_init fail"); } -#ifdef CONFIG_TPL +#if IS_ENABLED(CONFIG_TPL) || IS_ENABLED(CONFIG_SYS_COREBOOT) gd->bd = malloc(sizeof(*gd->bd)); if (!gd->bd) { printf("Out of memory for bd_info size %x\n", sizeof(*gd->bd)); From b4d4f592b243d08791ce582073710444ede48446 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 30 Apr 2020 21:21:43 -0600 Subject: [PATCH 173/237] x86: coreboot: Allow building an SPL image Make a few adjustments to allow us to build an SPL image for coreboot. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/x86/cpu/Makefile | 4 +++- arch/x86/cpu/coreboot/Makefile | 8 +++++++- arch/x86/cpu/coreboot/coreboot.c | 3 ++- arch/x86/cpu/coreboot/coreboot_spl.c | 12 ++++++++++++ arch/x86/cpu/intel_common/Makefile | 2 ++ arch/x86/cpu/x86_64/cpu.c | 2 ++ 6 files changed, 28 insertions(+), 3 deletions(-) create mode 100644 arch/x86/cpu/coreboot/coreboot_spl.c diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 307267a8fb3..ee0499f5d79 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -54,9 +54,11 @@ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ obj-$(CONFIG_INTEL_TANGIER) += tangier/ obj-$(CONFIG_APIC) += lapic.o ioapic.o -obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o obj-$(CONFIG_$(SPL_TPL_)ACPI_GPE) += acpi_gpe.o obj-$(CONFIG_QFW) += qfw_cpu.o +ifndef CONFIG_SYS_COREBOOT +obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o +endif ifndef CONFIG_$(SPL_)X86_64 obj-$(CONFIG_SMP) += mp_init.o endif diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile index 35b15bb1da8..605f90304e3 100644 --- a/arch/x86/cpu/coreboot/Makefile +++ b/arch/x86/cpu/coreboot/Makefile @@ -11,8 +11,14 @@ # (C) Copyright 2002 # Daniel Engström, Omicron Ceti AB, daniel@omicron.se. +ifndef CONFIG_SPL obj-y += car.o +endif +ifdef CONFIG_SPL_BUILD +obj-y += coreboot_spl.o +else +obj-y += sdram.o +endif obj-y += coreboot.o obj-y += tables.o -obj-y += sdram.o obj-y += timestamp.o diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 0c4c6348d1d..624caf67a6a 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -27,7 +27,8 @@ int arch_cpu_init(void) timestamp_init(); - return x86_cpu_init_f(); + return IS_ENABLED(CONFIG_X86_RUN_64BIT) ? x86_cpu_reinit_f() : + x86_cpu_init_f(); } int checkcpu(void) diff --git a/arch/x86/cpu/coreboot/coreboot_spl.c b/arch/x86/cpu/coreboot/coreboot_spl.c new file mode 100644 index 00000000000..36661871e92 --- /dev/null +++ b/arch/x86/cpu/coreboot/coreboot_spl.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Google LLC + */ + +#include +#include + +int dram_init(void) +{ + return 0; +} diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index 1736bd2b530..374803b8760 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -32,6 +32,8 @@ obj-$(CONFIG_HAVE_P2SB) += p2sb.o ifdef CONFIG_SPL ifndef CONFIG_SPL_BUILD +ifndef CONFIG_SYS_COREBOOT obj-y += cpu_from_spl.o endif endif +endif diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c index 90925e46ea2..4b64339f259 100644 --- a/arch/x86/cpu/x86_64/cpu.c +++ b/arch/x86/cpu/x86_64/cpu.c @@ -53,6 +53,7 @@ int misc_init_r(void) return 0; } +#ifndef CONFIG_SYS_COREBOOT int checkcpu(void) { return 0; @@ -62,6 +63,7 @@ int print_cpuinfo(void) { return 0; } +#endif int x86_cpu_reinit_f(void) { From 8d99d5434b1c98c832f7a1aa0a0e0c9ab4c284a1 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 30 Apr 2020 22:02:13 -0600 Subject: [PATCH 174/237] cmd: Add an indication of 32/64-bit to bdinfo It is useful to know what mode U-Boot is running in. Add a message at the end of the 'bdinfo' output. Suggested-by: Mark Kettenis Signed-off-by: Simon Glass Reviewed-by: Heinrich Schuchardt Reviewed-by: Bin Meng Tested-by: Bin Meng [bmeng: change commit tag to 'cmd' as this is not x86 specific] Signed-off-by: Bin Meng --- cmd/bdinfo.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index d6a7175b379..9edcf8d74eb 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -15,6 +15,11 @@ DECLARE_GLOBAL_DATA_PTR; +__maybe_unused void print_cpu_word_size(void) +{ + printf("%-12s= %u-bit\n", "Build", (uint)sizeof(void *) * 8); +} + __maybe_unused static void print_num(const char *name, ulong value) { @@ -208,6 +213,8 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_baudrate(); print_num("relocaddr", gd->relocaddr); board_detail(); + print_cpu_word_size(); + return 0; } @@ -227,6 +234,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth_ip_addr(); print_baudrate(); + print_cpu_word_size(); return 0; } @@ -252,6 +260,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_num("fdt_blob", (ulong)gd->fdt_blob); print_num("new_fdt", (ulong)gd->new_fdt); print_num("fdt_size", (ulong)gd->fdt_size); + print_cpu_word_size(); return 0; } @@ -283,6 +292,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif print_eth_ip_addr(); print_baudrate(); + print_cpu_word_size(); return 0; } @@ -294,6 +304,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_std_bdinfo(gd->bd); print_num("relocaddr", gd->relocaddr); print_num("reloc off", gd->reloc_off); + print_cpu_word_size(); return 0; } @@ -354,6 +365,7 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, #endif if (gd->fdt_blob) print_num("fdt_blob", (ulong)gd->fdt_blob); + print_cpu_word_size(); return 0; } @@ -368,6 +380,8 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_bi_flash(bd); print_eth_ip_addr(); print_baudrate(); + print_cpu_word_size(); + return 0; } @@ -388,6 +402,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_mhz("ethspeed", bd->bi_ethspeed); #endif print_baudrate(); + print_cpu_word_size(); return 0; } @@ -405,6 +420,8 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) print_num("FB base ", gd->fb_base); #endif + print_cpu_word_size(); + return 0; } @@ -419,6 +436,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_bi_dram(bd); print_eth_ip_addr(); print_baudrate(); + print_cpu_word_size(); return 0; } @@ -435,6 +453,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_num("reloc off", gd->reloc_off); print_eth_ip_addr(); print_baudrate(); + print_cpu_word_size(); return 0; } @@ -448,6 +467,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_bi_mem(bd); print_eth_ip_addr(); print_baudrate(); + print_cpu_word_size(); return 0; } From 538437ed39e01b7ecfa79669982fe7db51fb2e1b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 1 May 2020 07:36:10 -0600 Subject: [PATCH 175/237] x86: Add a 64-bit 'coreboot64' build Coreboot is a first-stage bootloader mostly used on x86 devices as an alternative to UEFI. Coreboot runs in 32-bit mode. U-Boot currently supports booting from coreboot as a second-stage bootloader, also in 32-bit mode. However it is useful to be able to run U-Boot in 64-bit mode. To do this we can have a 32-bit SPL which switches over the CPU and jumps to a 64-bit U-Boot proper. Add a new 'coreboot64' board for running 64-bit U-Boot from coreboot. This uses binman to create an image with a 32-bit SPL and a 64-bit U-Boot. This allows running 64-bit EFI images on x86, for example, without needing a native U-Boot port for a board. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- board/coreboot/coreboot/MAINTAINERS | 7 +++++ configs/coreboot64_defconfig | 48 +++++++++++++++++++++++++++++ doc/board/coreboot/coreboot.rst | 10 ++++++ 3 files changed, 65 insertions(+) create mode 100644 configs/coreboot64_defconfig diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS index 188906b0803..a05673bb0be 100644 --- a/board/coreboot/coreboot/MAINTAINERS +++ b/board/coreboot/coreboot/MAINTAINERS @@ -4,3 +4,10 @@ S: Maintained F: board/coreboot/coreboot/ F: include/configs/chromebook_link.h F: configs/coreboot_defconfig + +COREBOOT64 BOARD +M: Simon Glass +S: Maintained +F: board/coreboot/coreboot/ +F: include/configs/chromebook_link.h +F: configs/coreboot64_defconfig diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig new file mode 100644 index 00000000000..80353b8eb36 --- /dev/null +++ b/configs/coreboot64_defconfig @@ -0,0 +1,48 @@ +CONFIG_X86=y +CONFIG_SYS_TEXT_BASE=0x1120000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_NR_DRAM_BANKS=8 +CONFIG_PRE_CON_BUF_ADDR=0x100000 +CONFIG_X86_RUN_64BIT=y +CONFIG_VENDOR_COREBOOT=y +CONFIG_TARGET_COREBOOT=y +CONFIG_SPL_TEXT_BASE=0x1110000 +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" +CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_IDE=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_SOUND=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MAC_PARTITION=y +# CONFIG_SPL_MAC_PARTITION is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="coreboot" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +# CONFIG_PCI_PNP is not set +CONFIG_SOUND=y +CONFIG_SOUND_I8254=y +CONFIG_CONSOLE_SCROLL_LINES=5 diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst index fd974229eb4..9c44c025a48 100644 --- a/doc/board/coreboot/coreboot.rst +++ b/doc/board/coreboot/coreboot.rst @@ -40,3 +40,13 @@ To enable video you must enable these options in coreboot: At present it seems that for Minnowboard Max, coreboot does not pass through the video information correctly (it always says the resolution is 0x0). This works correctly for link though. + +64-bit U-Boot +------------- + +In addition to the 32-bit 'coreboot' build there is a 'coreboot64' build. This +produces an image which can be booted from coreboot (32-bit). Internally it +works by using a 32-bit SPL binary to switch to 64-bit for running U-Boot. It +can be useful for running UEFI applications, for example. + +This has only been lightly tested. From 7b8b63fb8ead9bd4041ab5424deb465f14ee172a Mon Sep 17 00:00:00 2001 From: AKASHI Takahiro Date: Tue, 21 Apr 2020 09:37:52 +0900 Subject: [PATCH 176/237] lib/crypto, efi_loader: avoid multiple inclusions of header files By adding extra symbols, we can now avoid including x509_parser and pkcs7_parser.h files multiple times. Suggested-by: Heinrich Schuchardt Signed-off-by: AKASHI Takahiro Don't include include x509_parser.h twice. Reviewed-by: Heinrich Schuchardt --- lib/crypto/pkcs7_parser.h | 4 ++++ lib/crypto/x509_parser.h | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/lib/crypto/pkcs7_parser.h b/lib/crypto/pkcs7_parser.h index 6565fdc2d4c..b8234da45a6 100644 --- a/lib/crypto/pkcs7_parser.h +++ b/lib/crypto/pkcs7_parser.h @@ -5,6 +5,9 @@ * Written by David Howells (dhowells@redhat.com) */ +#ifndef _PKCS7_PARSER_H +#define _PKCS7_PARSER_H + #include #include #include "x509_parser.h" @@ -63,3 +66,4 @@ struct pkcs7_message { size_t data_hdrlen; /* Length of Data ASN.1 header */ const void *data; /* Content Data (or 0) */ }; +#endif /* _PKCS7_PARSER_H */ diff --git a/lib/crypto/x509_parser.h b/lib/crypto/x509_parser.h index c233f136fb3..4cbdc1d6612 100644 --- a/lib/crypto/x509_parser.h +++ b/lib/crypto/x509_parser.h @@ -5,6 +5,9 @@ * Written by David Howells (dhowells@redhat.com) */ +#ifndef _X509_PARSER_H +#define _X509_PARSER_H + #include #include #include @@ -55,3 +58,4 @@ extern int x509_decode_time(time64_t *_t, size_t hdrlen, */ extern int x509_get_sig_params(struct x509_certificate *cert); extern int x509_check_for_self_signed(struct x509_certificate *cert); +#endif /* _X509_PARSER_H */ From e3f5c9cb0fcc95aa9287b5f8609294fe1a59b9da Mon Sep 17 00:00:00 2001 From: AKASHI Takahiro Date: Tue, 21 Apr 2020 09:38:17 +0900 Subject: [PATCH 177/237] lib/crypto, efi_loader: move some headers to include/crypto Pkcs7_parse.h and x509_parser.h are used in UEFI subsystem, in particular, secure boot. So move them to include/crypto to avoid relative paths. Suggested-by: Heinrich Schuchardt Signed-off-by: AKASHI Takahiro Don't include include x509_parser.h twice. Reviewed-by: Heinrich Schuchardt --- {lib => include}/crypto/pkcs7_parser.h | 0 {lib => include}/crypto/x509_parser.h | 0 lib/crypto/pkcs7_parser.c | 4 ++++ lib/crypto/x509_cert_parser.c | 4 ++++ lib/crypto/x509_public_key.c | 6 ++++-- lib/efi_loader/efi_image_loader.c | 2 +- lib/efi_loader/efi_signature.c | 2 +- lib/efi_loader/efi_variable.c | 2 +- test/lib/asn1.c | 4 ++-- 9 files changed, 17 insertions(+), 7 deletions(-) rename {lib => include}/crypto/pkcs7_parser.h (100%) rename {lib => include}/crypto/x509_parser.h (100%) diff --git a/lib/crypto/pkcs7_parser.h b/include/crypto/pkcs7_parser.h similarity index 100% rename from lib/crypto/pkcs7_parser.h rename to include/crypto/pkcs7_parser.h diff --git a/lib/crypto/x509_parser.h b/include/crypto/x509_parser.h similarity index 100% rename from lib/crypto/x509_parser.h rename to include/crypto/x509_parser.h diff --git a/lib/crypto/pkcs7_parser.c b/lib/crypto/pkcs7_parser.c index f5dda1179f8..0ee207b6b1c 100644 --- a/lib/crypto/pkcs7_parser.c +++ b/lib/crypto/pkcs7_parser.c @@ -20,7 +20,11 @@ #include #include #include +#ifdef __UBOOT__ +#include +#else #include "pkcs7_parser.h" +#endif #include "pkcs7.asn1.h" MODULE_DESCRIPTION("PKCS#7 parser"); diff --git a/lib/crypto/x509_cert_parser.c b/lib/crypto/x509_cert_parser.c index 4e41cffd230..18f5407a076 100644 --- a/lib/crypto/x509_cert_parser.c +++ b/lib/crypto/x509_cert_parser.c @@ -18,7 +18,11 @@ #include #endif #include +#ifdef __UBOOT__ +#include +#else #include "x509_parser.h" +#endif #include "x509.asn1.h" #include "x509_akid.asn1.h" diff --git a/lib/crypto/x509_public_key.c b/lib/crypto/x509_public_key.c index 676c0df1741..571af9a0adf 100644 --- a/lib/crypto/x509_public_key.c +++ b/lib/crypto/x509_public_key.c @@ -16,15 +16,17 @@ #include #endif #include -#ifndef __UBOOT__ +#ifdef __UBOOT__ +#include +#else #include #include #include #include #include #include "asymmetric_keys.h" -#endif #include "x509_parser.h" +#endif /* * Set up the signature parameters in an X.509 certificate. This involves diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c index 6c270ce94f4..5a9a6424cc1 100644 --- a/lib/efi_loader/efi_image_loader.c +++ b/lib/efi_loader/efi_image_loader.c @@ -13,7 +13,7 @@ #include #include #include -#include "../lib/crypto/pkcs7_parser.h" +#include "crypto/pkcs7_parser.h" const efi_guid_t efi_global_variable_guid = EFI_GLOBAL_VARIABLE_GUID; const efi_guid_t efi_guid_device_path = EFI_DEVICE_PATH_PROTOCOL_GUID; diff --git a/lib/efi_loader/efi_signature.c b/lib/efi_loader/efi_signature.c index 658e3547da3..150ce41f366 100644 --- a/lib/efi_loader/efi_signature.c +++ b/lib/efi_loader/efi_signature.c @@ -10,11 +10,11 @@ #include #include #include +#include #include #include #include #include -#include "../lib/crypto/pkcs7_parser.h" const efi_guid_t efi_guid_image_security_database = EFI_IMAGE_SECURITY_DATABASE_GUID; diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index 7df881a74b4..0c6d1deb58e 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -12,9 +12,9 @@ #include #include #include +#include #include #include -#include "../lib/crypto/pkcs7_parser.h" enum efi_secure_mode { EFI_MODE_SETUP, diff --git a/test/lib/asn1.c b/test/lib/asn1.c index d2b3f67e68d..8661fdd3068 100644 --- a/test/lib/asn1.c +++ b/test/lib/asn1.c @@ -13,10 +13,10 @@ #include #ifdef CONFIG_PKCS7_MESSAGE_PARSER -#include "../../lib/crypto/pkcs7_parser.h" +#include #else #ifdef CONFIG_X509_CERTIFICATE_PARSER -#include "../../lib/crypto/x509_parser.h" +#include #endif #endif From 964d5326c91ab1fd891a26cbd7a1c98b7fc42014 Mon Sep 17 00:00:00 2001 From: AKASHI Takahiro Date: Tue, 21 Apr 2020 09:38:57 +0900 Subject: [PATCH 178/237] efi_loader: fix unreachable statement in efi_sigstore_parse_siglist "if (left < esl->signature_size)" is not reachable in a while loop. But it is still valuable in case that a given signature database is somehow corrupted. So fix the while loop condition. Reported-by: Heinrich Schuchardt Signed-off-by: AKASHI Takahiro Reviewed-by: Heinrich Schuchardt --- lib/efi_loader/efi_signature.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_signature.c b/lib/efi_loader/efi_signature.c index 150ce41f366..4ad818d5eee 100644 --- a/lib/efi_loader/efi_signature.c +++ b/lib/efi_loader/efi_signature.c @@ -667,7 +667,7 @@ efi_sigstore_parse_siglist(struct efi_signature_list *esl) esd = (struct efi_signature_data *) ((u8 *)esl + sizeof(*esl) + esl->signature_header_size); - while ((left > 0) && left >= esl->signature_size) { + while (left > 0) { /* Signature must exist if there is remaining data. */ if (left < esl->signature_size) { debug("Certificate is too small\n"); From f0ff75f2491ba27c04bb1f94e502a2be8fc0e78e Mon Sep 17 00:00:00 2001 From: AKASHI Takahiro Date: Tue, 21 Apr 2020 09:39:20 +0900 Subject: [PATCH 179/237] efi_loader: factor out the common code from efi_transfer_secure_state() efi_set_secure_stat() provides the common code for each stat transition caused by efi_transfer_secure_state(). Suggested-by: Heinrich Schuchardt Signed-off-by: AKASHI Takahiro Correct description of return value. Reviewed-by: Heinrich Schuchardt --- lib/efi_loader/efi_variable.c | 194 +++++++++++----------------------- 1 file changed, 64 insertions(+), 130 deletions(-) diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index 0c6d1deb58e..9a3f1f3d2ee 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -176,6 +176,59 @@ static efi_status_t efi_set_variable_internal(u16 *variable_name, const void *data, bool ro_check); +/** + * efi_set_secure_state - modify secure boot state variables + * @sec_boot: value of SecureBoot + * @setup_mode: value of SetupMode + * @audit_mode: value of AuditMode + * @deployed_mode: value of DeployedMode + * + * Modify secure boot stat-related variables as indicated. + * + * Return: status code + */ +static efi_status_t efi_set_secure_state(int sec_boot, int setup_mode, + int audit_mode, int deployed_mode) +{ + u32 attributes; + efi_status_t ret; + + attributes = EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS | + READ_ONLY; + ret = efi_set_variable_internal(L"SecureBoot", + &efi_global_variable_guid, + attributes, + sizeof(sec_boot), &sec_boot, + false); + if (ret != EFI_SUCCESS) + goto err; + + ret = efi_set_variable_internal(L"SetupMode", + &efi_global_variable_guid, + attributes, + sizeof(setup_mode), &setup_mode, + false); + if (ret != EFI_SUCCESS) + goto err; + + ret = efi_set_variable_internal(L"AuditMode", + &efi_global_variable_guid, + attributes, + sizeof(audit_mode), &audit_mode, + false); + if (ret != EFI_SUCCESS) + goto err; + + ret = efi_set_variable_internal(L"DeployedMode", + &efi_global_variable_guid, + attributes, + sizeof(deployed_mode), &deployed_mode, + false); +err: + return ret; +} + /** * efi_transfer_secure_state - handle a secure boot state transition * @mode: new state @@ -188,157 +241,38 @@ static efi_status_t efi_set_variable_internal(u16 *variable_name, */ static efi_status_t efi_transfer_secure_state(enum efi_secure_mode mode) { - u32 attributes; - u8 val; efi_status_t ret; - debug("Secure state from %d to %d\n", efi_secure_mode, mode); + debug("Switching secure state from %d to %d\n", efi_secure_mode, mode); - attributes = EFI_VARIABLE_BOOTSERVICE_ACCESS | - EFI_VARIABLE_RUNTIME_ACCESS; if (mode == EFI_MODE_DEPLOYED) { - val = 1; - ret = efi_set_variable_internal(L"SecureBoot", - &efi_global_variable_guid, - attributes | READ_ONLY, - sizeof(val), &val, - false); - if (ret != EFI_SUCCESS) - goto err; - val = 0; - ret = efi_set_variable_internal(L"SetupMode", - &efi_global_variable_guid, - attributes | READ_ONLY, - sizeof(val), &val, - false); - if (ret != EFI_SUCCESS) - goto err; - val = 0; - ret = efi_set_variable_internal(L"AuditMode", - &efi_global_variable_guid, - attributes | READ_ONLY, - sizeof(val), &val, - false); - if (ret != EFI_SUCCESS) - goto err; - val = 1; - ret = efi_set_variable_internal(L"DeployedMode", - &efi_global_variable_guid, - attributes | READ_ONLY, - sizeof(val), &val, - false); + ret = efi_set_secure_state(1, 0, 0, 1); if (ret != EFI_SUCCESS) goto err; efi_secure_boot = true; } else if (mode == EFI_MODE_AUDIT) { - ret = efi_set_variable_internal(L"PK", - &efi_global_variable_guid, - attributes, - 0, NULL, - false); + ret = efi_set_variable_internal( + L"PK", &efi_global_variable_guid, + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS, + 0, NULL, false); if (ret != EFI_SUCCESS) goto err; - val = 0; - ret = efi_set_variable_internal(L"SecureBoot", - &efi_global_variable_guid, - attributes | READ_ONLY, - sizeof(val), &val, - false); - if (ret != EFI_SUCCESS) - goto err; - val = 1; - ret = efi_set_variable_internal(L"SetupMode", - &efi_global_variable_guid, - attributes | READ_ONLY, - sizeof(val), &val, - false); - if (ret != EFI_SUCCESS) - goto err; - val = 1; - ret = efi_set_variable_internal(L"AuditMode", - &efi_global_variable_guid, - attributes | READ_ONLY, - sizeof(val), &val, - false); - if (ret != EFI_SUCCESS) - goto err; - val = 0; - ret = efi_set_variable_internal(L"DeployedMode", - &efi_global_variable_guid, - attributes | READ_ONLY, - sizeof(val), &val, - false); + + ret = efi_set_secure_state(0, 1, 1, 0); if (ret != EFI_SUCCESS) goto err; efi_secure_boot = true; } else if (mode == EFI_MODE_USER) { - val = 1; - ret = efi_set_variable_internal(L"SecureBoot", - &efi_global_variable_guid, - attributes | READ_ONLY, - sizeof(val), &val, - false); - if (ret != EFI_SUCCESS) - goto err; - val = 0; - ret = efi_set_variable_internal(L"SetupMode", - &efi_global_variable_guid, - attributes | READ_ONLY, - sizeof(val), &val, - false); - if (ret != EFI_SUCCESS) - goto err; - val = 0; - ret = efi_set_variable_internal(L"AuditMode", - &efi_global_variable_guid, - attributes, - sizeof(val), &val, - false); - if (ret != EFI_SUCCESS) - goto err; - val = 0; - ret = efi_set_variable_internal(L"DeployedMode", - &efi_global_variable_guid, - attributes, - sizeof(val), &val, - false); + ret = efi_set_secure_state(1, 0, 0, 0); if (ret != EFI_SUCCESS) goto err; efi_secure_boot = true; } else if (mode == EFI_MODE_SETUP) { - val = 0; - ret = efi_set_variable_internal(L"SecureBoot", - &efi_global_variable_guid, - attributes | READ_ONLY, - sizeof(val), &val, - false); - if (ret != EFI_SUCCESS) - goto err; - val = 1; - ret = efi_set_variable_internal(L"SetupMode", - &efi_global_variable_guid, - attributes | READ_ONLY, - sizeof(val), &val, - false); - if (ret != EFI_SUCCESS) - goto err; - val = 0; - ret = efi_set_variable_internal(L"AuditMode", - &efi_global_variable_guid, - attributes, - sizeof(val), &val, - false); - if (ret != EFI_SUCCESS) - goto err; - val = 0; - ret = efi_set_variable_internal(L"DeployedMode", - &efi_global_variable_guid, - attributes | READ_ONLY, - sizeof(val), &val, - false); + ret = efi_set_secure_state(0, 1, 0, 0); if (ret != EFI_SUCCESS) goto err; } else { From 41fd506842c2d9385d940cffe8ceeb8456c29fc5 Mon Sep 17 00:00:00 2001 From: AKASHI Takahiro Date: Mon, 27 Apr 2020 18:48:20 +0900 Subject: [PATCH 180/237] efi_loader: disk: add efi_disk_is_system_part() This function will check if a given handle to device is an EFI system partition. It will be utilised in implementing capsule-on-disk feature. Signed-off-by: AKASHI Takahiro Add function description. Return bool. Reviewed-off-by: Heinrich Schuchardt --- include/efi_loader.h | 2 ++ lib/efi_loader/efi_disk.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/include/efi_loader.h b/include/efi_loader.h index f92bfe57e68..0e924ad1093 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -394,6 +394,8 @@ efi_status_t efi_disk_register(void); int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc, const char *if_typename, int diskid, const char *pdevname); +/* Check if it is EFI system partition */ +bool efi_disk_is_system_part(efi_handle_t handle); /* Called by bootefi to make GOP (graphical) interface available */ efi_status_t efi_gop_register(void); /* Called by bootefi to make the network interface available */ diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c index fd3df80b0b9..0582e02158f 100644 --- a/lib/efi_loader/efi_disk.c +++ b/lib/efi_loader/efi_disk.c @@ -588,3 +588,32 @@ efi_status_t efi_disk_register(void) return EFI_SUCCESS; } + +/** + * efi_disk_is_system_part() - check if handle refers to an EFI system partition + * + * @handle: handle of partition + * + * Return: true if handle refers to an EFI system partition + */ +bool efi_disk_is_system_part(efi_handle_t handle) +{ + struct efi_handler *handler; + struct efi_disk_obj *diskobj; + disk_partition_t info; + efi_status_t ret; + int r; + + /* check if this is a block device */ + ret = efi_search_protocol(handle, &efi_block_io_guid, &handler); + if (ret != EFI_SUCCESS) + return false; + + diskobj = container_of(handle, struct efi_disk_obj, header); + + r = part_get_info(diskobj->desc, diskobj->part, &info); + if (r) + return false; + + return !!(info.bootable & PART_EFI_SYSTEM_PARTITION); +} From a30c72319cc1e486a680efe2d0c94d58f4957e85 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sat, 2 May 2020 16:08:37 +0200 Subject: [PATCH 181/237] cmd: efidebug: simplify UEFI protocol calls We should not to refer to a function via the run-time or boot services tables if the function is exported. Signed-off-by: Heinrich Schuchardt --- cmd/efidebug.c | 40 +++++++++++++++++++--------------------- 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/cmd/efidebug.c b/cmd/efidebug.c index d4030fee645..d8a76d78a38 100644 --- a/cmd/efidebug.c +++ b/cmd/efidebug.c @@ -17,7 +17,6 @@ #include #define BS systab.boottime -#define RT systab.runtime /** * efi_get_device_handle_info() - get information of UEFI device @@ -69,7 +68,7 @@ static int do_efi_show_devices(cmd_tbl_t *cmdtp, int flag, u16 *dev_path_text; efi_status_t ret; - ret = EFI_CALL(BS->locate_handle_buffer(ALL_HANDLES, NULL, NULL, + ret = EFI_CALL(efi_locate_handle_buffer(ALL_HANDLES, NULL, NULL, &num, &handles)); if (ret != EFI_SUCCESS) return CMD_RET_FAILURE; @@ -86,7 +85,7 @@ static int do_efi_show_devices(cmd_tbl_t *cmdtp, int flag, } } - EFI_CALL(BS->free_pool(handles)); + efi_free_pool(handles); return CMD_RET_SUCCESS; } @@ -148,7 +147,7 @@ static int do_efi_show_drivers(cmd_tbl_t *cmdtp, int flag, u16 *driver_name, *image_path_text; efi_status_t ret; - ret = EFI_CALL(BS->locate_handle_buffer( + ret = EFI_CALL(efi_locate_handle_buffer( BY_PROTOCOL, &efi_guid_driver_binding_protocol, NULL, &num, &handles)); if (ret != EFI_SUCCESS) @@ -170,12 +169,12 @@ static int do_efi_show_drivers(cmd_tbl_t *cmdtp, int flag, else printf("%p %-20ls \n", handles[i], driver_name); - EFI_CALL(BS->free_pool(driver_name)); - EFI_CALL(BS->free_pool(image_path_text)); + efi_free_pool(driver_name); + efi_free_pool(image_path_text); } } - EFI_CALL(BS->free_pool(handles)); + efi_free_pool(handles); return CMD_RET_SUCCESS; } @@ -321,7 +320,7 @@ static int do_efi_show_handles(cmd_tbl_t *cmdtp, int flag, const char *guid_text; efi_status_t ret; - ret = EFI_CALL(BS->locate_handle_buffer(ALL_HANDLES, NULL, NULL, + ret = EFI_CALL(efi_locate_handle_buffer(ALL_HANDLES, NULL, NULL, &num, &handles)); if (ret != EFI_SUCCESS) return CMD_RET_FAILURE; @@ -355,7 +354,7 @@ static int do_efi_show_handles(cmd_tbl_t *cmdtp, int flag, putc('\n'); } - EFI_CALL(BS->free_pool(handles)); + efi_free_pool(handles); return CMD_RET_SUCCESS; } @@ -463,18 +462,17 @@ static int do_efi_show_memmap(cmd_tbl_t *cmdtp, int flag, int i; efi_status_t ret; - ret = EFI_CALL(BS->get_memory_map(&map_size, memmap, NULL, NULL, NULL)); + ret = efi_get_memory_map(&map_size, memmap, NULL, NULL, NULL); if (ret == EFI_BUFFER_TOO_SMALL) { map_size += sizeof(struct efi_mem_desc); /* for my own */ - ret = EFI_CALL(BS->allocate_pool(EFI_LOADER_DATA, - map_size, (void *)&memmap)); + ret = efi_allocate_pool(EFI_LOADER_DATA, map_size, + (void *)&memmap); if (ret != EFI_SUCCESS) return CMD_RET_FAILURE; - ret = EFI_CALL(BS->get_memory_map(&map_size, memmap, - NULL, NULL, NULL)); + ret = efi_get_memory_map(&map_size, memmap, NULL, NULL, NULL); } if (ret != EFI_SUCCESS) { - EFI_CALL(BS->free_pool(memmap)); + efi_free_pool(memmap); return CMD_RET_FAILURE; } @@ -501,7 +499,7 @@ static int do_efi_show_memmap(cmd_tbl_t *cmdtp, int flag, putc('\n'); } - EFI_CALL(BS->free_pool(memmap)); + efi_free_pool(memmap); return CMD_RET_SUCCESS; } @@ -615,7 +613,7 @@ static int do_efi_boot_add(cmd_tbl_t *cmdtp, int flag, goto out; } - ret = EFI_CALL(RT->set_variable(var_name16, &guid, + ret = EFI_CALL(efi_set_variable(var_name16, &guid, EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, @@ -670,7 +668,7 @@ static int do_efi_boot_rm(cmd_tbl_t *cmdtp, int flag, p = var_name16; utf8_utf16_strncpy(&p, var_name, 9); - ret = EFI_CALL(RT->set_variable(var_name16, &guid, 0, 0, NULL)); + ret = EFI_CALL(efi_set_variable(var_name16, &guid, 0, 0, NULL)); if (ret) { printf("Cannot remove %ls\n", var_name16); return CMD_RET_FAILURE; @@ -864,7 +862,7 @@ static int show_efi_boot_order(void) efi_status_t ret; size = 0; - ret = EFI_CALL(RT->get_variable(L"BootOrder", &efi_global_variable_guid, + ret = EFI_CALL(efi_get_variable(L"BootOrder", &efi_global_variable_guid, NULL, &size, NULL)); if (ret != EFI_BUFFER_TOO_SMALL) { if (ret == EFI_NOT_FOUND) { @@ -975,7 +973,7 @@ static int do_efi_boot_next(cmd_tbl_t *cmdtp, int flag, guid = efi_global_variable_guid; size = sizeof(u16); - ret = EFI_CALL(RT->set_variable(L"BootNext", &guid, + ret = EFI_CALL(efi_set_variable(L"BootNext", &guid, EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, @@ -1036,7 +1034,7 @@ static int do_efi_boot_order(cmd_tbl_t *cmdtp, int flag, } guid = efi_global_variable_guid; - ret = EFI_CALL(RT->set_variable(L"BootOrder", &guid, + ret = EFI_CALL(efi_set_variable(L"BootOrder", &guid, EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, From c08cac0edc17f0d3c74425e5d41efa3c92686322 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sat, 18 Apr 2020 12:31:17 +0200 Subject: [PATCH 182/237] efi_loader: eliminate efi_get_(non)volatile_variable Eliminate superfluous functions efi_get_volatile_variable() and efi_get_nonvolatile_variable(). Signed-off-by: Heinrich Schuchardt --- lib/efi_loader/efi_variable.c | 32 +++----------------------------- 1 file changed, 3 insertions(+), 29 deletions(-) diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index 9a3f1f3d2ee..ceb6b17b004 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -600,8 +600,7 @@ static efi_status_t EFIAPI efi_get_variable_common(u16 *variable_name, const efi_guid_t *vendor, u32 *attributes, - efi_uintn_t *data_size, void *data, - bool is_non_volatile) + efi_uintn_t *data_size, void *data) { char *native_name; efi_status_t ret; @@ -684,27 +683,6 @@ out: return ret; } -static -efi_status_t EFIAPI efi_get_volatile_variable(u16 *variable_name, - const efi_guid_t *vendor, - u32 *attributes, - efi_uintn_t *data_size, - void *data) -{ - return efi_get_variable_common(variable_name, vendor, attributes, - data_size, data, false); -} - -efi_status_t EFIAPI efi_get_nonvolatile_variable(u16 *variable_name, - const efi_guid_t *vendor, - u32 *attributes, - efi_uintn_t *data_size, - void *data) -{ - return efi_get_variable_common(variable_name, vendor, attributes, - data_size, data, true); -} - /** * efi_efi_get_variable() - retrieve value of a UEFI variable * @@ -729,12 +707,8 @@ efi_status_t EFIAPI efi_get_variable(u16 *variable_name, EFI_ENTRY("\"%ls\" %pUl %p %p %p", variable_name, vendor, attributes, data_size, data); - ret = efi_get_volatile_variable(variable_name, vendor, attributes, - data_size, data); - if (ret == EFI_NOT_FOUND) - ret = efi_get_nonvolatile_variable(variable_name, vendor, - attributes, data_size, data); - + ret = efi_get_variable_common(variable_name, vendor, attributes, + data_size, data); return EFI_EXIT(ret); } From bb0e585c71e724d26eaeede7fdaaaa46ed26f930 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 3 May 2020 10:02:20 +0200 Subject: [PATCH 183/237] efi_loader: eliminate efi_set_(non)volatile_variable Eliminate superfluous functions efi_set_volatile_variable() and efi_set_nonvolatile_variable(). Signed-off-by: Heinrich Schuchardt --- lib/efi_loader/efi_variable.c | 141 +++++++++------------------------- 1 file changed, 37 insertions(+), 104 deletions(-) diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index ceb6b17b004..b9c2e4ebf68 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -169,12 +169,12 @@ static const char *parse_attr(const char *str, u32 *attrp, u64 *timep) return str; } -static efi_status_t efi_set_variable_internal(u16 *variable_name, - const efi_guid_t *vendor, - u32 attributes, - efi_uintn_t data_size, - const void *data, - bool ro_check); +static efi_status_t efi_set_variable_common(u16 *variable_name, + const efi_guid_t *vendor, + u32 attributes, + efi_uintn_t data_size, + const void *data, + bool ro_check); /** * efi_set_secure_state - modify secure boot state variables @@ -196,35 +196,28 @@ static efi_status_t efi_set_secure_state(int sec_boot, int setup_mode, attributes = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | READ_ONLY; - ret = efi_set_variable_internal(L"SecureBoot", - &efi_global_variable_guid, - attributes, - sizeof(sec_boot), &sec_boot, - false); + ret = efi_set_variable_common(L"SecureBoot", &efi_global_variable_guid, + attributes, sizeof(sec_boot), &sec_boot, + false); if (ret != EFI_SUCCESS) goto err; - ret = efi_set_variable_internal(L"SetupMode", - &efi_global_variable_guid, - attributes, - sizeof(setup_mode), &setup_mode, - false); + ret = efi_set_variable_common(L"SetupMode", &efi_global_variable_guid, + attributes, sizeof(setup_mode), + &setup_mode, false); if (ret != EFI_SUCCESS) goto err; - ret = efi_set_variable_internal(L"AuditMode", - &efi_global_variable_guid, - attributes, - sizeof(audit_mode), &audit_mode, - false); + ret = efi_set_variable_common(L"AuditMode", &efi_global_variable_guid, + attributes, sizeof(audit_mode), + &audit_mode, false); if (ret != EFI_SUCCESS) goto err; - ret = efi_set_variable_internal(L"DeployedMode", - &efi_global_variable_guid, - attributes, - sizeof(deployed_mode), &deployed_mode, - false); + ret = efi_set_variable_common(L"DeployedMode", + &efi_global_variable_guid, attributes, + sizeof(deployed_mode), &deployed_mode, + false); err: return ret; } @@ -234,7 +227,7 @@ err: * @mode: new state * * Depending on @mode, secure boot related variables are updated. - * Those variables are *read-only* for users, efi_set_variable_internal() + * Those variables are *read-only* for users, efi_set_variable_common() * is called here. * * Return: EFI_SUCCESS on success, status code (negative) on error @@ -252,11 +245,10 @@ static efi_status_t efi_transfer_secure_state(enum efi_secure_mode mode) efi_secure_boot = true; } else if (mode == EFI_MODE_AUDIT) { - ret = efi_set_variable_internal( - L"PK", &efi_global_variable_guid, - EFI_VARIABLE_BOOTSERVICE_ACCESS | - EFI_VARIABLE_RUNTIME_ACCESS, - 0, NULL, false); + ret = efi_set_variable_common(L"PK", &efi_global_variable_guid, + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS, + 0, NULL, false); if (ret != EFI_SUCCESS) goto err; @@ -326,14 +318,13 @@ static efi_status_t efi_init_secure_state(void) ret = efi_transfer_secure_state(mode); if (ret == EFI_SUCCESS) - ret = efi_set_variable_internal(L"VendorKeys", - &efi_global_variable_guid, - EFI_VARIABLE_BOOTSERVICE_ACCESS - | EFI_VARIABLE_RUNTIME_ACCESS - | READ_ONLY, - sizeof(efi_vendor_keys), - &efi_vendor_keys, - false); + ret = efi_set_variable_common(L"VendorKeys", + &efi_global_variable_guid, + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS | + READ_ONLY, + sizeof(efi_vendor_keys), + &efi_vendor_keys, false); err: return ret; @@ -872,14 +863,12 @@ efi_status_t EFIAPI efi_get_next_variable_name(efi_uintn_t *variable_name_size, return EFI_EXIT(ret); } -static -efi_status_t EFIAPI efi_set_variable_common(u16 *variable_name, +static efi_status_t efi_set_variable_common(u16 *variable_name, const efi_guid_t *vendor, u32 attributes, efi_uintn_t data_size, const void *data, - bool ro_check, - bool is_non_volatile) + bool ro_check) { char *native_name = NULL, *old_data = NULL, *val = NULL, *s; efi_uintn_t old_size; @@ -906,14 +895,6 @@ efi_status_t EFIAPI efi_set_variable_common(u16 *variable_name, attr = 0; ret = EFI_CALL(efi_get_variable(variable_name, vendor, &attr, &old_size, NULL)); - if (ret == EFI_BUFFER_TOO_SMALL) { - if ((is_non_volatile && !(attr & EFI_VARIABLE_NON_VOLATILE)) || - (!is_non_volatile && (attr & EFI_VARIABLE_NON_VOLATILE))) { - ret = EFI_INVALID_PARAMETER; - goto err; - } - } - append = !!(attributes & EFI_VARIABLE_APPEND_WRITE); attributes &= ~(u32)EFI_VARIABLE_APPEND_WRITE; delete = !append && (!data_size || !attributes); @@ -1087,7 +1068,7 @@ out: /* update VendorKeys */ if (vendor_keys_modified & efi_vendor_keys) { efi_vendor_keys = 0; - ret = efi_set_variable_internal( + ret = efi_set_variable_common( L"VendorKeys", &efi_global_variable_guid, EFI_VARIABLE_BOOTSERVICE_ACCESS @@ -1109,54 +1090,6 @@ err: return ret; } -static -efi_status_t EFIAPI efi_set_volatile_variable(u16 *variable_name, - const efi_guid_t *vendor, - u32 attributes, - efi_uintn_t data_size, - const void *data, - bool ro_check) -{ - return efi_set_variable_common(variable_name, vendor, attributes, - data_size, data, ro_check, false); -} - -efi_status_t EFIAPI efi_set_nonvolatile_variable(u16 *variable_name, - const efi_guid_t *vendor, - u32 attributes, - efi_uintn_t data_size, - const void *data, - bool ro_check) -{ - efi_status_t ret; - - ret = efi_set_variable_common(variable_name, vendor, attributes, - data_size, data, ro_check, true); - - return ret; -} - -static efi_status_t efi_set_variable_internal(u16 *variable_name, - const efi_guid_t *vendor, - u32 attributes, - efi_uintn_t data_size, - const void *data, - bool ro_check) -{ - efi_status_t ret; - - if (attributes & EFI_VARIABLE_NON_VOLATILE) - ret = efi_set_nonvolatile_variable(variable_name, vendor, - attributes, - data_size, data, ro_check); - else - ret = efi_set_volatile_variable(variable_name, vendor, - attributes, data_size, data, - ro_check); - - return ret; -} - /** * efi_set_variable() - set value of a UEFI variable * @@ -1182,9 +1115,9 @@ efi_status_t EFIAPI efi_set_variable(u16 *variable_name, /* READ_ONLY bit is not part of API */ attributes &= ~(u32)READ_ONLY; - return EFI_EXIT(efi_set_variable_internal(variable_name, vendor, - attributes, data_size, data, - true)); + return EFI_EXIT(efi_set_variable_common(variable_name, vendor, + attributes, data_size, data, + true)); } /** From 30f92ce9d5e895336f73cc1132a7fdc42e378353 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 3 May 2020 16:29:00 +0200 Subject: [PATCH 184/237] efi_loader: correct comments for efi_status_t EFI_STATUS is unsigned (UINTN). Hence it cannot be negative. Correct comments for 'Return:'. Signed-off-by: Heinrich Schuchardt --- lib/efi_loader/efi_setup.c | 2 +- lib/efi_loader/efi_signature.c | 2 +- lib/efi_loader/efi_variable.c | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c index 1b648c84673..65739aca493 100644 --- a/lib/efi_loader/efi_setup.c +++ b/lib/efi_loader/efi_setup.c @@ -86,7 +86,7 @@ out: /** * efi_init_secure_boot - initialize secure boot state * - * Return: EFI_SUCCESS on success, status code (negative) on error + * Return: status code */ static efi_status_t efi_init_secure_boot(void) { diff --git a/lib/efi_loader/efi_signature.c b/lib/efi_loader/efi_signature.c index 4ad818d5eee..adcb8c9cca6 100644 --- a/lib/efi_loader/efi_signature.c +++ b/lib/efi_loader/efi_signature.c @@ -528,7 +528,7 @@ out: * pointed to by @regs. If @nocheck is false, overlapping among entries * will be checked first. * - * Return: 0 on success, status code (negative) on error + * Return: status code */ efi_status_t efi_image_region_add(struct efi_image_regions *regs, const void *start, const void *end, diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index b9c2e4ebf68..58f8fae358c 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -230,7 +230,7 @@ err: * Those variables are *read-only* for users, efi_set_variable_common() * is called here. * - * Return: EFI_SUCCESS on success, status code (negative) on error + * Return: status code */ static efi_status_t efi_transfer_secure_state(enum efi_secure_mode mode) { @@ -284,7 +284,7 @@ err: /** * efi_init_secure_state - initialize secure boot state * - * Return: EFI_SUCCESS on success, status code (negative) on error + * Return: status code */ static efi_status_t efi_init_secure_state(void) { @@ -438,7 +438,7 @@ out: * attributes and signed time will also be returned in @env_attr and @time, * respectively. * - * Return: EFI_SUCCESS on success, status code (negative) on error + * Return: status code */ static efi_status_t efi_variable_authenticate(u16 *variable, const efi_guid_t *vendor, From 5827c2545849441dd60467565aac11964259972f Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 4 May 2020 12:21:51 +0200 Subject: [PATCH 185/237] test: stabilize test_efi_secboot When setting up the console via function efi_console_register() we call query_console_serial(). This functions sends an escape sequence to the terminal to query the display size. The response is another escape sequence. console.run_command_list() is looking for a regular expression '^==>'. If the escape sequence for the screen size precedes the prompt without a line break, no match is found. When efi_disk_register() is called before efi_console_register() this leads to a test failuere of the UEFI secure boot tests. We can avoid the problem if the first UEFI command passed to u_boot_console.run_command_list() produces output. This patch achieves this by appending '; echo' to the first UEFI related command of the problematic tests. Signed-off-by: Heinrich Schuchardt --- test/py/tests/test_efi_secboot/test_authvar.py | 8 ++++---- test/py/tests/test_efi_secboot/test_signed.py | 4 ++-- test/py/tests/test_efi_secboot/test_unsigned.py | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/test/py/tests/test_efi_secboot/test_authvar.py b/test/py/tests/test_efi_secboot/test_authvar.py index 55dcaa95f1e..9912694a3e3 100644 --- a/test/py/tests/test_efi_secboot/test_authvar.py +++ b/test/py/tests/test_efi_secboot/test_authvar.py @@ -133,7 +133,7 @@ class TestEfiAuthVar(object): output = u_boot_console.run_command_list([ 'host bind 0 %s' % disk_img, 'fatload host 0:1 4000000 PK.auth', - 'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK', + 'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK; echo', 'fatload host 0:1 4000000 KEK.auth', 'setenv -e -nv -bs -rt -at -i 4000000,$filesize KEK', 'fatload host 0:1 4000000 db.auth', @@ -174,7 +174,7 @@ class TestEfiAuthVar(object): output = u_boot_console.run_command_list([ 'host bind 0 %s' % disk_img, 'fatload host 0:1 4000000 PK.auth', - 'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK', + 'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK; echo', 'fatload host 0:1 4000000 KEK.auth', 'setenv -e -nv -bs -rt -at -i 4000000,$filesize KEK', 'fatload host 0:1 4000000 db.auth', @@ -215,7 +215,7 @@ class TestEfiAuthVar(object): output = u_boot_console.run_command_list([ 'host bind 0 %s' % disk_img, 'fatload host 0:1 4000000 PK.auth', - 'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK', + 'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK; echo', 'fatload host 0:1 4000000 KEK.auth', 'setenv -e -nv -bs -rt -at -i 4000000,$filesize KEK', 'fatload host 0:1 4000000 db.auth', @@ -249,7 +249,7 @@ class TestEfiAuthVar(object): output = u_boot_console.run_command_list([ 'host bind 0 %s' % disk_img, 'fatload host 0:1 4000000 PK.auth', - 'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK', + 'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK; echo', 'fatload host 0:1 4000000 KEK.auth', 'setenv -e -nv -bs -rt -at -i 4000000,$filesize KEK', 'fatload host 0:1 4000000 db.auth', diff --git a/test/py/tests/test_efi_secboot/test_signed.py b/test/py/tests/test_efi_secboot/test_signed.py index 584282b338b..fc722ab506c 100644 --- a/test/py/tests/test_efi_secboot/test_signed.py +++ b/test/py/tests/test_efi_secboot/test_signed.py @@ -29,7 +29,7 @@ class TestEfiSignedImage(object): # Test Case 1a, run signed image if no db/dbx output = u_boot_console.run_command_list([ 'host bind 0 %s' % disk_img, - 'efidebug boot add 1 HELLO1 host 0:1 /helloworld.efi.signed ""', + 'efidebug boot add 1 HELLO1 host 0:1 /helloworld.efi.signed ""; echo', 'efidebug boot next 1', 'bootefi bootmgr']) assert(re.search('Hello, world!', ''.join(output))) @@ -81,7 +81,7 @@ class TestEfiSignedImage(object): output = u_boot_console.run_command_list([ 'host bind 0 %s' % disk_img, 'fatload host 0:1 4000000 db.auth', - 'setenv -e -nv -bs -rt -at -i 4000000,$filesize dbx', + 'setenv -e -nv -bs -rt -at -i 4000000,$filesize dbx; echo', 'fatload host 0:1 4000000 KEK.auth', 'setenv -e -nv -bs -rt -at -i 4000000,$filesize KEK', 'fatload host 0:1 4000000 PK.auth', diff --git a/test/py/tests/test_efi_secboot/test_unsigned.py b/test/py/tests/test_efi_secboot/test_unsigned.py index 22d849afb89..a4af845c514 100644 --- a/test/py/tests/test_efi_secboot/test_unsigned.py +++ b/test/py/tests/test_efi_secboot/test_unsigned.py @@ -30,7 +30,7 @@ class TestEfiUnsignedImage(object): output = u_boot_console.run_command_list([ 'host bind 0 %s' % disk_img, 'fatload host 0:1 4000000 KEK.auth', - 'setenv -e -nv -bs -rt -at -i 4000000,$filesize KEK', + 'setenv -e -nv -bs -rt -at -i 4000000,$filesize KEK; echo', 'fatload host 0:1 4000000 PK.auth', 'setenv -e -nv -bs -rt -at -i 4000000,$filesize PK']) assert(not re.search('Failed to set EFI variable', ''.join(output))) @@ -58,7 +58,7 @@ class TestEfiUnsignedImage(object): output = u_boot_console.run_command_list([ 'host bind 0 %s' % disk_img, 'fatload host 0:1 4000000 db_hello.auth', - 'setenv -e -nv -bs -rt -at -i 4000000,$filesize db', + 'setenv -e -nv -bs -rt -at -i 4000000,$filesize db; echo', 'fatload host 0:1 4000000 KEK.auth', 'setenv -e -nv -bs -rt -at -i 4000000,$filesize KEK', 'fatload host 0:1 4000000 PK.auth', @@ -82,7 +82,7 @@ class TestEfiUnsignedImage(object): output = u_boot_console.run_command_list([ 'host bind 0 %s' % disk_img, 'fatload host 0:1 4000000 db_hello.auth', - 'setenv -e -nv -bs -rt -at -i 4000000,$filesize dbx', + 'setenv -e -nv -bs -rt -at -i 4000000,$filesize dbx; echo', 'fatload host 0:1 4000000 KEK.auth', 'setenv -e -nv -bs -rt -at -i 4000000,$filesize KEK', 'fatload host 0:1 4000000 PK.auth', From 16ad946f41d3dc3e475d8313f4acbba0df527a2a Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 19 Mar 2020 18:21:58 +0000 Subject: [PATCH 186/237] efi_loader: change setup sequence If we want to restore variables from disk, we need to initialize block devices before variables. Signed-off-by: Heinrich Schuchardt --- lib/efi_loader/efi_setup.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c index 65739aca493..26a74232036 100644 --- a/lib/efi_loader/efi_setup.c +++ b/lib/efi_loader/efi_setup.c @@ -135,6 +135,11 @@ efi_status_t efi_init_obj_list(void) /* On ARM switch from EL3 or secure mode to EL2 or non-secure mode */ switch_to_non_secure_mode(); +#ifdef CONFIG_PARTITIONS + ret = efi_disk_register(); + if (ret != EFI_SUCCESS) + goto out; +#endif /* Initialize variable services */ ret = efi_init_variables(); if (ret != EFI_SUCCESS) @@ -183,11 +188,6 @@ efi_status_t efi_init_obj_list(void) ret = efi_console_register(); if (ret != EFI_SUCCESS) goto out; -#ifdef CONFIG_PARTITIONS - ret = efi_disk_register(); - if (ret != EFI_SUCCESS) - goto out; -#endif #if defined(CONFIG_LCD) || defined(CONFIG_DM_VIDEO) ret = efi_gop_register(); if (ret != EFI_SUCCESS) From 20a154f95bfe0a3b5bfba90bea7f001c58217536 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 1 May 2020 17:40:25 +0200 Subject: [PATCH 187/237] mkimage: fit: Do not tail-pad fitImage with external data There is no reason to tail-pad fitImage with external data to 4-bytes, while fitImage without external data does not have any such padding and is often unaligned. DT spec also does not mandate any such padding. Moreover, the tail-pad fills the last few bytes with uninitialized data, which could lead to a potential information leak. $ echo -n xy > /tmp/data ; \ ./tools/mkimage -E -f auto -d /tmp/data /tmp/fitImage ; \ hexdump -vC /tmp/fitImage | tail -n 3 before: 00000260 61 2d 6f 66 66 73 65 74 00 64 61 74 61 2d 73 69 |a-offset.data-si| 00000270 7a 65 00 00 78 79 64 64 |ze..xydd| ^^ ^^ ^^ after: 00000260 61 2d 6f 66 66 73 65 74 00 64 61 74 61 2d 73 69 |a-offset.data-si| 00000270 7a 65 00 78 79 |ze.xy| Signed-off-by: Marek Vasut Reviewed-by: Simon Glass Cc: Heinrich Schuchardt Cc: Tom Rini --- tools/fit_image.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/tools/fit_image.c b/tools/fit_image.c index 88ff093d05b..1e0f1e9fce8 100644 --- a/tools/fit_image.c +++ b/tools/fit_image.c @@ -435,7 +435,7 @@ static int fit_extract_data(struct image_tool_params *params, const char *fname) int image_number; int align_size; - align_size = params->bl_len ? params->bl_len : 4; + align_size = params->bl_len ? params->bl_len : 1; fd = mmap_fdt(params->cmdname, fname, 0, &fdt, &sbuf, false, false); if (fd < 0) return -EIO; @@ -493,7 +493,6 @@ static int fit_extract_data(struct image_tool_params *params, const char *fname) fdt_pack(fdt); new_size = fdt_totalsize(fdt); - new_size = ALIGN(new_size, align_size); fdt_set_totalsize(fdt, new_size); debug("Size reduced from %x to %x\n", fit_size, fdt_totalsize(fdt)); debug("External data size %x\n", buf_ptr); From 8510580f2e85a8687b40fe5fc3d8c060e5278505 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Sun, 3 May 2020 19:43:32 +0200 Subject: [PATCH 188/237] net: pcnet: fix I/O primitives for memory access Commit 69529c912059 ("net: pcnet: Switch to PCI memory access") switched from PCI IO access to PCI memory access without updating the I/O primitives. Contrary to SH, the primitives for memory access and IO access are implemented differently. Thus doing memory access with IO port primitives breaks the driver on MIPS Malta board. Signed-off-by: Daniel Schwierzeck --- drivers/net/pcnet.c | 34 +++++++++++++++++++++++----------- 1 file changed, 23 insertions(+), 11 deletions(-) diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 34a5a16cfe8..f97e7f8c6a3 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -91,37 +91,49 @@ static pcnet_priv_t *lp; static u16 pcnet_read_csr(struct eth_device *dev, int index) { - outw(index, dev->iobase + PCNET_RAP); - return inw(dev->iobase + PCNET_RDP); + void __iomem *base = (void __iomem *)dev->iobase; + + writew(index, base + PCNET_RAP); + return readw(base + PCNET_RDP); } static void pcnet_write_csr(struct eth_device *dev, int index, u16 val) { - outw(index, dev->iobase + PCNET_RAP); - outw(val, dev->iobase + PCNET_RDP); + void __iomem *base = (void __iomem *)dev->iobase; + + writew(index, base + PCNET_RAP); + writew(val, base + PCNET_RDP); } static u16 pcnet_read_bcr(struct eth_device *dev, int index) { - outw(index, dev->iobase + PCNET_RAP); - return inw(dev->iobase + PCNET_BDP); + void __iomem *base = (void __iomem *)dev->iobase; + + writew(index, base + PCNET_RAP); + return readw(base + PCNET_BDP); } static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val) { - outw(index, dev->iobase + PCNET_RAP); - outw(val, dev->iobase + PCNET_BDP); + void __iomem *base = (void __iomem *)dev->iobase; + + writew(index, base + PCNET_RAP); + writew(val, base + PCNET_BDP); } static void pcnet_reset(struct eth_device *dev) { - inw(dev->iobase + PCNET_RESET); + void __iomem *base = (void __iomem *)dev->iobase; + + readw(base + PCNET_RESET); } static int pcnet_check(struct eth_device *dev) { - outw(88, dev->iobase + PCNET_RAP); - return inw(dev->iobase + PCNET_RAP) == 88; + void __iomem *base = (void __iomem *)dev->iobase; + + writew(88, base + PCNET_RAP); + return readw(base + PCNET_RAP) == 88; } static int pcnet_init (struct eth_device *dev, bd_t * bis); From 15c160301cf4761d45e09808f9d818525425901b Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Mon, 6 Jan 2020 12:01:17 +0000 Subject: [PATCH 189/237] scripts/get_default_envs.sh: preserve order of multiple entries for same variable It's possible that the default_environment[] array contains multiple entries for the same variable, e.g. a setting from env_default.h based on some CONFIG_* variable, and another from CONFIG_EXTRA_ENV_SETTINGS. In such a case, the last setting takes effect. Hence, in order to be able to use the output from this script as an CONFIG_DEFAULT_ENV_FILE and get the same default environment as one currently has, we need to preserve the order. So only sort by the variable name, and disable the last-resort comparison. We could pipe the result through uniq to remove duplicate lines, but I think there's some value in seeing that certain variables are defined multiple times. Signed-off-by: Rasmus Villemoes Reviewed-by: Lukasz Majewski Reviewed-by: Simon Glass --- scripts/get_default_envs.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/get_default_envs.sh b/scripts/get_default_envs.sh index da86a9d69cc..d1f2ce4d5c5 100755 --- a/scripts/get_default_envs.sh +++ b/scripts/get_default_envs.sh @@ -35,7 +35,7 @@ cp ${env_obj_file_path} ${ENV_OBJ_FILE_COPY} ${OBJCOPY} -O binary -j ".rodata.default_environment" ${ENV_OBJ_FILE_COPY} # Replace default '\0' with '\n' and sort entries -tr '\0' '\n' < ${ENV_OBJ_FILE_COPY} | sort -u +tr '\0' '\n' < ${ENV_OBJ_FILE_COPY} | sort --field-separator== -k1,1 --stable rm ${ENV_OBJ_FILE_COPY} From 653f7c44677cd13bb106673bb7c46542e217fa13 Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Mon, 4 May 2020 18:41:55 +0800 Subject: [PATCH 190/237] cache: l2x0: Fix missing write to Auxiliary Control Register In commit f62782fb2999 ("cache: l2x0: Fix write to incorrect shared-override bit") we removed writel to regs->pl310_aux_ctrl by accident. This commit restores it back. Fixes: f62782fb2999 ("cache: l2x0: Fix write to incorrect shared-override bit") Signed-off-by: Ley Foon Tan --- drivers/cache/cache-l2x0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c index 226824c2832..a1556fbf174 100644 --- a/drivers/cache/cache-l2x0.c +++ b/drivers/cache/cache-l2x0.c @@ -36,6 +36,8 @@ static void l2c310_of_parse_and_init(struct udevice *dev) if (dev_read_bool(dev, "arm,shared-override")) saved_reg |= L310_SHARED_ATT_OVERRIDE_ENABLE; + writel(saved_reg, ®s->pl310_aux_ctrl); + saved_reg = readl(®s->pl310_tag_latency_ctrl); if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3)) saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) | From 7946a814a31989998120b4b4aa417222ba21b2fa Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 6 May 2020 11:05:17 -0400 Subject: [PATCH 191/237] Revert "mkimage: fit: Do not tail-pad fitImage with external data" This has been reported to break booting of U-Boot from SPL on a number of platforms due to a lack of alignment of the external data. The issues this commit is addressing will need to be resolved another way. Re-introduce a data leak in the padding for now. This reverts commit 20a154f95bfe0a3b5bfba90bea7f001c58217536. Reported-by: Alex Kiernan Reported-by: Michael Walle Tested-by: Jan Kiszka Signed-off-by: Tom Rini --- tools/fit_image.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/fit_image.c b/tools/fit_image.c index 1e0f1e9fce8..88ff093d05b 100644 --- a/tools/fit_image.c +++ b/tools/fit_image.c @@ -435,7 +435,7 @@ static int fit_extract_data(struct image_tool_params *params, const char *fname) int image_number; int align_size; - align_size = params->bl_len ? params->bl_len : 1; + align_size = params->bl_len ? params->bl_len : 4; fd = mmap_fdt(params->cmdname, fname, 0, &fdt, &sbuf, false, false); if (fd < 0) return -EIO; @@ -493,6 +493,7 @@ static int fit_extract_data(struct image_tool_params *params, const char *fname) fdt_pack(fdt); new_size = fdt_totalsize(fdt); + new_size = ALIGN(new_size, align_size); fdt_set_totalsize(fdt, new_size); debug("Size reduced from %x to %x\n", fit_size, fdt_totalsize(fdt)); debug("External data size %x\n", buf_ptr); From 682fef9ff6b464602b35e4fcc0cca83568ad2ffa Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Tue, 18 Feb 2020 08:39:42 +0000 Subject: [PATCH 192/237] include/eeprom.h: fix build errors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CMD_EEPROM and ENV_IS_IN_EEPROM can be selected independently, and cmd/eeprom.o gets built in either case, so whether to declare the real prototypes needs to follow the same logic as whether cmd/eeprom.c is built. Otherwise a ENV_IS_IN_EEPROM=y, CMD_EEPROM=n build fails cmd/eeprom.c:73:1: error: expected identifier or ‘(’ before ‘{’ token { While at it, fix the dummy replacements (at least assuming they are meant to allow the code to compile) - they need to have the same type as the expression they replace, or one gets errors such as env/eeprom.c: In function ‘eeprom_bus_read’: env/eeprom.c:37:8: error: void value not ignored as it ought to be rcode = eeprom_read(dev_addr, offset, buffer, cnt); Signed-off-by: Rasmus Villemoes Reviewed-by: Tom Rini --- include/eeprom.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/eeprom.h b/include/eeprom.h index 79118eb83de..6820844cea3 100644 --- a/include/eeprom.h +++ b/include/eeprom.h @@ -7,7 +7,7 @@ #ifndef __EEPROM_LEGACY_H #define __EEPROM_LEGACY_H -#ifdef CONFIG_CMD_EEPROM +#if defined(CONFIG_CMD_EEPROM) || defined(CONFIG_ENV_IS_IN_EEPROM) void eeprom_init(int bus); int eeprom_read(uint dev_addr, uint offset, uchar *buffer, uint cnt); int eeprom_write(uint dev_addr, uint offset, uchar *buffer, uint cnt); @@ -17,8 +17,8 @@ int eeprom_write(uint dev_addr, uint offset, uchar *buffer, uint cnt); * some macros here so we don't have to touch every one of those uses */ #define eeprom_init(bus) -#define eeprom_read(dev_addr, offset, buffer, cnt) ((void)-ENOSYS) -#define eeprom_write(dev_addr, offset, buffer, cnt) ((void)-ENOSYS) +#define eeprom_read(dev_addr, offset, buffer, cnt) (-ENOSYS) +#define eeprom_write(dev_addr, offset, buffer, cnt) (-ENOSYS) #endif #if !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) From 7d6dae0dfb4b056850cde6ff91d06bb5cbda8fd3 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 27 Apr 2020 19:17:58 +0100 Subject: [PATCH 193/237] arm: juno: Fix Juno address variables The U-Boot documentation explains that variables ending with "_r" hold addresses in DRAM, while those without that ending point to flash/ROM. The default variables for the Juno board pointing to the kernel and DTB load addresses were not complying with this scheme: they lack the extension, but point to DRAM. This is particularly confusing since the Juno board features parallel NOR flash, so there *is* a memory mapped NOR address holding a DTB, for instance. Fix the variables to use the proper names, changing initrd_addr to ramdisk_addr_r on the way, which seems to be more prevelant and documented. On the way adjust the FDT load address to be situated *before* the kernel, since users happened to overwrite the DTB by the kernel clearing its .BSS section during initialisation. Also remove the fdt_high and initrd_high variables (which were set to -1), to allow U-Boot moving those images around. This should avoid many problems in the future, but breaks loading Linux kernels < v4.2, since they expect the DTB to be loaded in the same 512MB region as the kernel. If you need to load such an old kernel, please set fdt_high to either 0xffffffffffffffff or 0xa0000000 (if you load the kernel to the beginning of DRAM). That fixes loading debug kernels, which happened to overwrite the DTB on certain setups. Signed-off-by: Andre Przywara Reviewed-by: Simon Glass --- include/configs/vexpress_aemv8a.h | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 4f3a792f496..6f817606128 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -138,35 +138,33 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "kernel_name=norkern\0" \ "kernel_alt_name=Image\0" \ - "kernel_addr=0x80080000\0" \ - "initrd_name=ramdisk.img\0" \ - "initrd_addr=0x84000000\0" \ + "kernel_addr_r=0x80080000\0" \ + "ramdisk_name=ramdisk.img\0" \ + "ramdisk_addr_r=0x88000000\0" \ "fdtfile=board.dtb\0" \ "fdt_alt_name=juno\0" \ - "fdt_addr=0x83000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ + "fdt_addr_r=0x80000000\0" \ /* Copy the kernel and FDT to DRAM memory and boot */ -#define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \ +#define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr_r} ;"\ "if test $? -eq 1; then "\ " echo Loading ${kernel_alt_name} instead of "\ "${kernel_name}; "\ - " afs load ${kernel_alt_name} ${kernel_addr};"\ + " afs load ${kernel_alt_name} ${kernel_addr_r};"\ "fi ; "\ - "afs load ${fdtfile} ${fdt_addr} ; " \ + "afs load ${fdtfile} ${fdt_addr_r} ;"\ "if test $? -eq 1; then "\ " echo Loading ${fdt_alt_name} instead of "\ "${fdtfile}; "\ - " afs load ${fdt_alt_name} ${fdt_addr}; "\ + " afs load ${fdt_alt_name} ${fdt_addr_r}; "\ "fi ; "\ - "fdt addr ${fdt_addr}; fdt resize; " \ - "if afs load ${initrd_name} ${initrd_addr} ; "\ + "fdt addr ${fdt_addr_r}; fdt resize; " \ + "if afs load ${ramdisk_name} ${ramdisk_addr_r} ; "\ "then "\ - " setenv initrd_param ${initrd_addr}; "\ - " else setenv initrd_param -; "\ + " setenv ramdisk_param ${ramdisk_addr_r}; "\ + " else setenv ramdisk_param -; "\ "fi ; " \ - "booti ${kernel_addr} ${initrd_param} ${fdt_addr}" + "booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}" #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP From e3e2d662a273d5ac67998f390529966a8d8c8a3b Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 27 Apr 2020 19:17:59 +0100 Subject: [PATCH 194/237] uart: pl011: Add proper DM clock support Even though the PL011 UART driver claims to be DM compliant, it does not really a good job with parsing DT nodes. U-Boot seems to adhere to a non-standard binding, either requiring to have a "skip-init" property in the node, or to have an extra "clock" property holding the base *frequency* value for the baud rate generator. DTs in the U-Boot tree seem to have been hacked to match this requirement. The official binding does not mention any of these properties, instead recommends a standard "clocks" property to point to the baud base clock. Some boards use simple "fixed-clock" providers, which U-Boot readily supports, so let's add some simple DM clock code to the PL011 driver to learn the rate of the first clock, as described by the official binding. These clock nodes seem to be not ready very early in the boot process, so provide a fallback value, by re-using the already existing CONFIG_PL011_CLOCK variable. Signed-off-by: Andre Przywara [trini: Add for get_bus_freq() for layerscape platforms] Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- drivers/serial/serial_pl01x.c | 47 ++++++++++++++++++++++++----------- 1 file changed, 32 insertions(+), 15 deletions(-) diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 2a5f256184f..6e5d81ce34a 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -11,7 +11,10 @@ /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */ #include +/* For get_bus_freq() */ +#include #include +#include #include #include #include @@ -149,21 +152,24 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type, unsigned int remainder; unsigned int fraction; - /* - * Set baud rate - * - * IBRD = UART_CLK / (16 * BAUD_RATE) - * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) - * / (16 * BAUD_RATE)) - */ - temp = 16 * baudrate; - divider = clock / temp; - remainder = clock % temp; - temp = (8 * remainder) / baudrate; - fraction = (temp >> 1) + (temp & 1); + /* Without a valid clock rate we cannot set up the baudrate. */ + if (clock) { + /* + * Set baud rate + * + * IBRD = UART_CLK / (16 * BAUD_RATE) + * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) + * / (16 * BAUD_RATE)) + */ + temp = 16 * baudrate; + divider = clock / temp; + remainder = clock % temp; + temp = (8 * remainder) / baudrate; + fraction = (temp >> 1) + (temp & 1); - writel(divider, ®s->pl011_ibrd); - writel(fraction, ®s->pl011_fbrd); + writel(divider, ®s->pl011_ibrd); + writel(fraction, ®s->pl011_fbrd); + } pl011_set_line_control(regs); /* Finally, enable the UART */ @@ -337,17 +343,28 @@ static const struct udevice_id pl01x_serial_id[] ={ {} }; +#ifndef CONFIG_PL011_CLOCK +#define CONFIG_PL011_CLOCK 0 +#endif + int pl01x_serial_ofdata_to_platdata(struct udevice *dev) { struct pl01x_serial_platdata *plat = dev_get_platdata(dev); + struct clk clk; fdt_addr_t addr; + int ret; addr = devfdt_get_addr(dev); if (addr == FDT_ADDR_T_NONE) return -EINVAL; plat->base = addr; - plat->clock = dev_read_u32_default(dev, "clock", 1); + plat->clock = dev_read_u32_default(dev, "clock", CONFIG_PL011_CLOCK); + ret = clk_get_by_index(dev, 0, &clk); + if (!ret) { + clk_enable(&clk); + plat->clock = clk_get_rate(&clk); + } plat->type = dev_get_driver_data(dev); plat->skip_init = dev_read_bool(dev, "skip-init"); From deaa511d87e94c4e6274c0327333bdafd914e940 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 27 Apr 2020 19:18:00 +0100 Subject: [PATCH 195/237] arm: juno: Fix UART clock rate The UART base clock rate was typo-ed in the header file, probably because the reference (the Linux .dts) was also wrong[1]. Fix the number to make the baud rate more correct. Signed-off-by: Andre Przywara Reviewed-by: Linus Walleij [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=39a1a8941b2 Reviewed-by: Simon Glass --- include/configs/vexpress_aemv8a.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 6f817606128..3c85c93a5c6 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -102,7 +102,7 @@ /* PL011 Serial Configuration */ #ifdef CONFIG_TARGET_VEXPRESS64_JUNO -#define CONFIG_PL011_CLOCK 7273800 +#define CONFIG_PL011_CLOCK 7372800 #else #define CONFIG_PL011_CLOCK 24000000 #endif From b3270e91385111facdb7c79c30f2943d93e63280 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 27 Apr 2020 19:18:01 +0100 Subject: [PATCH 196/237] arm: juno: Enable OF_CONTROL The Arm Juno board was still somewhat stuck in "hardcoded land", even though there are stable DTs around, and one happens to actually be on the memory mapped NOR flash. Enable the configuration options to let the board use OF_CONTROL, and add a routine to find the address of the DTB partition in NOR flash, to use that for U-Boot's own purposes. This can also passed on via $fdtcontroladdr to any kernel or EFI application, removing the need to actually load a device tree. Since the existing "afs" command and its flash routines require flash_init() to be called before being usable, and this is done much later in the boot process, we introduce a stripped-down partition finder routine in vexpress64.c, to scan the NOR flash partitions for the DT partition. This location is then used for U-Boot to find and probe devices. The name of the partition can be configured, if needed, but defaults to "board.dtb", which is used by Linaro's firmware image provided. Signed-off-by: Andre Przywara Reviewed-by: Linus Walleij Reviewed-by: Simon Glass --- arch/arm/Kconfig | 5 +++ board/armltd/vexpress64/Kconfig | 7 ++++ board/armltd/vexpress64/vexpress64.c | 57 ++++++++++++++++++++++++++ configs/vexpress_aemv8a_juno_defconfig | 4 +- 4 files changed, 70 insertions(+), 3 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b494bcae954..27ae0a8b5d3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1162,6 +1162,11 @@ config TARGET_VEXPRESS64_JUNO bool "Support Versatile Express Juno Development Platform" select ARM64 select PL01X_SERIAL + select DM + select OF_CONTROL + select OF_BOARD + select CLK + select DM_SERIAL config TARGET_LS2080A_EMU bool "Support ls2080a_emu" diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index 90144184334..1d13f542e67 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -9,4 +9,11 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "vexpress_aemv8a" +config JUNO_DTB_PART + string "NOR flash partition holding DTB" + default "board.dtb" + help + The ARM partition name in the NOR flash memory holding the + device tree blob to configure U-Boot. + endif diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index dd0ebdd3030..ba49b32e58c 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -82,6 +82,63 @@ int dram_init_banksize(void) return 0; } +#ifdef CONFIG_OF_BOARD +#define JUNO_FLASH_SEC_SIZE (256 * 1024) +static phys_addr_t find_dtb_in_nor_flash(const char *partname) +{ + phys_addr_t sector = CONFIG_SYS_FLASH_BASE; + int i; + + for (i = 0; + i < CONFIG_SYS_MAX_FLASH_SECT; + i++, sector += JUNO_FLASH_SEC_SIZE) { + int len = strlen(partname) + 1; + int offs; + phys_addr_t imginfo; + u32 reg; + + reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x04); + /* This makes up the string "HSLFTOOF" flash footer */ + if (reg != 0x464F4F54U) + continue; + reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x08); + if (reg != 0x464C5348U) + continue; + + for (offs = 0; offs < 32; offs += 4, len -= 4) { + reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x30 + offs); + if (strncmp(partname + offs, (char *)®, + len > 4 ? 4 : len)) + break; + + if (len > 4) + continue; + + reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x10); + imginfo = sector + JUNO_FLASH_SEC_SIZE - 0x30 - reg; + reg = readl(imginfo + 0x54); + + return CONFIG_SYS_FLASH_BASE + + reg * JUNO_FLASH_SEC_SIZE; + } + } + + printf("No DTB found\n"); + + return ~0; +} + +void *board_fdt_blob_setup(void) +{ + phys_addr_t fdt_rom_addr = find_dtb_in_nor_flash(CONFIG_JUNO_DTB_PART); + + if (fdt_rom_addr == ~0UL) + return NULL; + + return (void *)fdt_rom_addr; +} +#endif + /* * Board specific reset that is system reset. */ diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index 8628d05e68b..6cb21e7a1bf 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -10,6 +10,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/sda2 rw rootwait earlycon=pl011,0x7ff80000 debug user_debug=31 androidboot.hardware=juno loglevel=9" +CONFIG_OF_BOARD=y # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set @@ -30,7 +31,6 @@ CONFIG_CMD_UBI=y # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xBFC0000 -CONFIG_DM=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -41,5 +41,3 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SMC911X=y CONFIG_SMC911X_BASE=0x018000000 CONFIG_SMC911X_32_BIT=y -CONFIG_DM_SERIAL=y -CONFIG_OF_LIBFDT=y From be0d09695d2bd689a3804eab82658d77eb495681 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 27 Apr 2020 19:18:02 +0100 Subject: [PATCH 197/237] arm: juno: Use PSCI based reset So far the Juno board wasn't implementing reset. Let's just use the already existing PSCI_RESET based method to avoid any extra code. Signed-off-by: Andre Przywara Acked-by: Liviu Dudau Reviewed-by: Simon Glass --- arch/arm/Kconfig | 2 ++ board/armltd/vexpress64/vexpress64.c | 4 +--- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 27ae0a8b5d3..7c589121a05 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1167,6 +1167,8 @@ config TARGET_VEXPRESS64_JUNO select OF_BOARD select CLK select DM_SERIAL + select ARM_PSCI_FW + select PSCI_RESET config TARGET_LS2080A_EMU bool "Support ls2080a_emu" diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index ba49b32e58c..5c7a8f55f03 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -139,9 +139,7 @@ void *board_fdt_blob_setup(void) } #endif -/* - * Board specific reset that is system reset. - */ +/* Actual reset is done via PSCI. */ void reset_cpu(ulong addr) { } From 56e403d95fc00304e87565712f34e0f2107a33c4 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 27 Apr 2020 19:18:03 +0100 Subject: [PATCH 198/237] arm: juno: enable USB The Juno board features a standard compliant EHCI/OHCI USB host controller pair, which we can just enable. The platform data is taken from the device tree. This allows to use USB mass storage (the only storage on a Juno r0) for loading. At least on my board USB seems a bit flaky, I need two "usb reset" sequences after the "usb start" to detect an USB hard drive. Signed-off-by: Andre Przywara Acked-by: Liviu Dudau Reviewed-by: Linus Walleij Reviewed-by: Simon Glass --- arch/arm/Kconfig | 4 ++++ configs/vexpress_aemv8a_juno_defconfig | 5 +++++ include/configs/vexpress_aemv8a.h | 5 +++++ 3 files changed, 14 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7c589121a05..0d463088a2e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1169,6 +1169,10 @@ config TARGET_VEXPRESS64_JUNO select DM_SERIAL select ARM_PSCI_FW select PSCI_RESET + select DM + select BLK + select USB + select DM_USB config TARGET_LS2080A_EMU bool "Support ls2080a_emu" diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index 6cb21e7a1bf..ca7aa5ab02b 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_ARMFLASH=y CONFIG_CMD_CACHE=y # CONFIG_CMD_MISC is not set CONFIG_CMD_UBI=y +CONFIG_CMD_USB=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_FLASH=y @@ -41,3 +42,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SMC911X=y CONFIG_SMC911X_BASE=0x018000000 CONFIG_SMC911X_32_BIT=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 3c85c93a5c6..08ad368dbb5 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -219,6 +219,11 @@ #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT #define CONFIG_SYS_MAX_FLASH_BANKS 1 +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 +#endif + #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ #define FLASH_MAX_SECTOR_SIZE 0x00040000 From af6d4c0567f71fd24879fdb26b712b59b6a25160 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 27 Apr 2020 19:18:04 +0100 Subject: [PATCH 199/237] arm: vexpress64: Remove unneeded CONFIG_ check CONFIG_SEMIHOSTING is selected for the VFP target by the means of Kconfig already, there is no need to check this in the header file. Signed-off-by: Andre Przywara Reviewed-by: Linus Walleij Reviewed-by: Simon Glass --- include/configs/vexpress_aemv8a.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 08ad368dbb5..3d638970540 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -7,12 +7,6 @@ #ifndef __VEXPRESS_AEMV8A_H #define __VEXPRESS_AEMV8A_H -#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP -#ifndef CONFIG_SEMIHOSTING -#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING -#endif -#endif - #define CONFIG_REMAKE_ELF /* Link Definitions */ From c2a2123e33371b2dc3406789764996d4fa73aac3 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 28 Apr 2020 11:38:03 +0200 Subject: [PATCH 200/237] cmd: cache: Fix non-cached memory cachability If dcache is switched OFF to ON state and if non-cached memory is used, this non-cached memory must be re-declared as uncached to mmu each time dcache is set ON. Introduce noncached_set_region() to set this non-cached region's mmu settings. Let architecture override it by defining it as a weak function. For ARM architecture, noncached_set_region() defines all noncached region as non-cacheable. Issue found on STM32MP1 platform using dwc_eth_qos ethernet driver, when going from dcache OFF to dcache ON state, ethernet driver issued TX timeout errors when performing dhcp or ping. It can be reproduced with the following sequence: dhcp while true ; do ping 192.168.1.300 ; dcache off ; ping 192.168.1.300 ; dcache on ; done Signed-off-by: Patrice Chotard Cc: Marek Vasut Cc: Joe Hershberger Cc: Ramon Fried Cc: Stephen Warren Reviewed-by: Marek Vasut --- arch/arm/lib/cache.c | 13 ++++++++++--- cmd/cache.c | 5 +++++ 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 44dde26065b..224f2aef14d 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -75,6 +75,15 @@ static unsigned long noncached_start; static unsigned long noncached_end; static unsigned long noncached_next; +void noncached_set_region(void) +{ +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) + mmu_set_region_dcache_behaviour(noncached_start, + noncached_end - noncached_start, + DCACHE_OFF); +#endif +} + void noncached_init(void) { phys_addr_t start, end; @@ -91,9 +100,7 @@ void noncached_init(void) noncached_end = end; noncached_next = start; -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) - mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF); -#endif + noncached_set_region(); } phys_addr_t noncached_alloc(size_t size, size_t align) diff --git a/cmd/cache.c b/cmd/cache.c index 27dcec09316..7678615dd83 100644 --- a/cmd/cache.c +++ b/cmd/cache.c @@ -20,6 +20,10 @@ void __weak invalidate_icache_all(void) puts("No arch specific invalidate_icache_all available!\n"); } +__weak void noncached_set_region(void) +{ +} + static int do_icache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { switch (argc) { @@ -64,6 +68,7 @@ static int do_dcache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) break; case 1: dcache_enable(); + noncached_set_region(); break; case 2: flush_dcache_all(); From fdf0819afb5b7a8757ba1b4fdfe14f3767ab7e87 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sun, 3 May 2020 13:26:34 +0200 Subject: [PATCH 201/237] rsa: fix alignment issue when getting public exponent To fill the exponent field of the rsa_public_key struct, rsa_mod_exp_sw did a cast to uint64_t of the key_prop->public_exponent field. But that alignment is not guaranteed in all cases. This came to light when in my spl-fit-signature the key-name exceeded a certain length and with it the verification then started failing. (naming it "integrity" worked fine, "integrity-uboot" failed) key_prop.public_exponent itself is actually a void-pointer, fdt_getprop() also just returns such a void-pointer and inside the devicetree the 64bit exponent is represented as 2 32bit numbers, so assuming a 64bit alignment can lead to false reads. So just use the already existing rsa_convert_big_endian() to do the actual conversion from the dt's big-endian to the needed uint64 value. Fixes: fc2f4246b4b3 ("rsa: Split the rsa-verify to separate the modular exponentiation") Signed-off-by: Heiko Stuebner Reviewed-by: Philipp Tomsich Reviewed-by: Simon Glass --- lib/rsa/rsa-mod-exp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/rsa/rsa-mod-exp.c b/lib/rsa/rsa-mod-exp.c index 420ab2eba05..62b2557cc28 100644 --- a/lib/rsa/rsa-mod-exp.c +++ b/lib/rsa/rsa-mod-exp.c @@ -262,8 +262,8 @@ int rsa_mod_exp_sw(const uint8_t *sig, uint32_t sig_len, if (!prop->public_exponent) key.exponent = RSA_DEFAULT_PUBEXP; else - key.exponent = - fdt64_to_cpu(*((uint64_t *)(prop->public_exponent))); + rsa_convert_big_endian((uint32_t *)&key.exponent, + prop->public_exponent, 2); if (!key.len || !prop->modulus || !prop->rr) { debug("%s: Missing RSA key info", __func__); From 5168d7a6264be30f82c1c074e43c24fcacbb4283 Mon Sep 17 00:00:00 2001 From: Thirupathaiah Annapureddy Date: Wed, 18 Mar 2020 11:38:42 -0700 Subject: [PATCH 202/237] menu: add support for client defined statusline function Currently displaying status line is done in a weak function menu_display_statusline(). bootmenu.c overrides the weak default function. It calls menu_default_choice() and interprets the data as struct bootmenu_entry. pxe boot also uses common menu code for pxe menus. If there is a system that enables both bootmenu and pxe, menu_display_statusline() defined in bootmenu.c will be called and it will interpret struct pxe_label as struct bootmenu_entry. This leads to data aborts and pxe menu corruptions. This patch adds support for client defined statusline function to resolve the above bug. Signed-off-by: Thirupathaiah Annapureddy --- cmd/bootmenu.c | 61 +++++++++++++++++++++++++------------------------ cmd/pxe_utils.c | 2 +- common/menu.c | 13 +++++++---- include/menu.h | 2 +- 4 files changed, 41 insertions(+), 37 deletions(-) diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c index 3dc2c854aca..f1562883f52 100644 --- a/cmd/bootmenu.c +++ b/cmd/bootmenu.c @@ -365,6 +365,34 @@ cleanup: return NULL; } +static void menu_display_statusline(struct menu *m) +{ + struct bootmenu_entry *entry; + struct bootmenu_data *menu; + + if (menu_default_choice(m, (void *)&entry) < 0) + return; + + menu = entry->menu; + + printf(ANSI_CURSOR_POSITION, 1, 1); + puts(ANSI_CLEAR_LINE); + printf(ANSI_CURSOR_POSITION, 2, 1); + puts(" *** U-Boot Boot Menu ***"); + puts(ANSI_CLEAR_LINE_TO_END); + printf(ANSI_CURSOR_POSITION, 3, 1); + puts(ANSI_CLEAR_LINE); + + /* First 3 lines are bootmenu header + 2 empty lines between entries */ + printf(ANSI_CURSOR_POSITION, menu->count + 5, 1); + puts(ANSI_CLEAR_LINE); + printf(ANSI_CURSOR_POSITION, menu->count + 6, 1); + puts(" Press UP/DOWN to move, ENTER to select"); + puts(ANSI_CLEAR_LINE_TO_END); + printf(ANSI_CURSOR_POSITION, menu->count + 7, 1); + puts(ANSI_CLEAR_LINE); +} + static void bootmenu_show(int delay) { int init = 0; @@ -396,8 +424,9 @@ static void bootmenu_show(int delay) if (!bootmenu) return; - menu = menu_create(NULL, bootmenu->delay, 1, bootmenu_print_entry, - bootmenu_choice_entry, bootmenu); + menu = menu_create(NULL, bootmenu->delay, 1, menu_display_statusline, + bootmenu_print_entry, bootmenu_choice_entry, + bootmenu); if (!menu) { bootmenu_destroy(bootmenu); return; @@ -445,34 +474,6 @@ cleanup: #endif } -void menu_display_statusline(struct menu *m) -{ - struct bootmenu_entry *entry; - struct bootmenu_data *menu; - - if (menu_default_choice(m, (void *)&entry) < 0) - return; - - menu = entry->menu; - - printf(ANSI_CURSOR_POSITION, 1, 1); - puts(ANSI_CLEAR_LINE); - printf(ANSI_CURSOR_POSITION, 2, 1); - puts(" *** U-Boot Boot Menu ***"); - puts(ANSI_CLEAR_LINE_TO_END); - printf(ANSI_CURSOR_POSITION, 3, 1); - puts(ANSI_CLEAR_LINE); - - /* First 3 lines are bootmenu header + 2 empty lines between entries */ - printf(ANSI_CURSOR_POSITION, menu->count + 5, 1); - puts(ANSI_CLEAR_LINE); - printf(ANSI_CURSOR_POSITION, menu->count + 6, 1); - puts(" Press UP/DOWN to move, ENTER to select"); - puts(ANSI_CLEAR_LINE_TO_END); - printf(ANSI_CURSOR_POSITION, menu->count + 7, 1); - puts(ANSI_CLEAR_LINE); -} - #ifdef CONFIG_AUTOBOOT_MENU_SHOW int menu_show(int bootdelay) { diff --git a/cmd/pxe_utils.c b/cmd/pxe_utils.c index 53af04d7dc7..c244bfb10d6 100644 --- a/cmd/pxe_utils.c +++ b/cmd/pxe_utils.c @@ -1237,7 +1237,7 @@ static struct menu *pxe_menu_to_menu(struct pxe_menu *cfg) * Create a menu and add items for all the labels. */ m = menu_create(cfg->title, DIV_ROUND_UP(cfg->timeout, 10), - cfg->prompt, label_print, NULL, NULL); + cfg->prompt, NULL, label_print, NULL, NULL); if (!m) return NULL; diff --git a/common/menu.c b/common/menu.c index 7b66d199a9b..5fb2ffbd065 100644 --- a/common/menu.c +++ b/common/menu.c @@ -36,6 +36,7 @@ struct menu { int timeout; char *title; int prompt; + void (*display_statusline)(struct menu *); void (*item_data_print)(void *); char *(*item_choice)(void *); void *item_choice_data; @@ -106,10 +107,6 @@ static inline void *menu_item_destroy(struct menu *m, return NULL; } -__weak void menu_display_statusline(struct menu *m) -{ -} - /* * Display a menu so the user can make a choice of an item. First display its * title, if any, and then each item in the menu. @@ -120,7 +117,8 @@ static inline void menu_display(struct menu *m) puts(m->title); putc('\n'); } - menu_display_statusline(m); + if (m->display_statusline) + m->display_statusline(m); menu_items_iter(m, menu_item_print, NULL); } @@ -344,6 +342,9 @@ int menu_item_add(struct menu *m, char *item_key, void *item_data) * timeout. If 1, the user will be prompted for input regardless of the value * of timeout. * + * display_statusline - If not NULL, will be called to show a statusline when + * the menu is displayed. + * * item_data_print - If not NULL, will be called for each item when the menu * is displayed, with the pointer to the item's data passed as the argument. * If NULL, each item's key will be printed instead. Since an item's key is @@ -360,6 +361,7 @@ int menu_item_add(struct menu *m, char *item_key, void *item_data) * insufficient memory available to create the menu. */ struct menu *menu_create(char *title, int timeout, int prompt, + void (*display_statusline)(struct menu *), void (*item_data_print)(void *), char *(*item_choice)(void *), void *item_choice_data) @@ -374,6 +376,7 @@ struct menu *menu_create(char *title, int timeout, int prompt, m->default_item = NULL; m->prompt = prompt; m->timeout = timeout; + m->display_statusline = display_statusline; m->item_data_print = item_data_print; m->item_choice = item_choice; m->item_choice_data = item_choice_data; diff --git a/include/menu.h b/include/menu.h index 2d227c20bd5..9ab9b21ebb9 100644 --- a/include/menu.h +++ b/include/menu.h @@ -9,6 +9,7 @@ struct menu; struct menu *menu_create(char *title, int timeout, int prompt, + void (*display_statusline)(struct menu *), void (*item_data_print)(void *), char *(*item_choice)(void *), void *item_choice_data); @@ -16,7 +17,6 @@ int menu_default_set(struct menu *m, char *item_key); int menu_get_choice(struct menu *m, void **choice); int menu_item_add(struct menu *m, char *item_key, void *item_data); int menu_destroy(struct menu *m); -void menu_display_statusline(struct menu *m); int menu_default_choice(struct menu *m, void **choice); /** From 4346df3392c0e795ce458bc86e9e8ed24a3afa0f Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 7 May 2020 00:11:48 +0200 Subject: [PATCH 203/237] phy: atheros: Make RGMII Tx delays actually configurable for AR8035 Delete the extraneous write to debug reg 5 that enables Tx delay When the driver was originally introduced in commit "6027384a phylib: Add Atheros AR8035 GETH PHY support", the Tx delay was being unconditionally enabled. Then during "2ec4d10b phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID", the author did not notice that code for enabling Tx delay code was already. Therefore, the if condition for Tx delay has always been useless for this PHY since this commit introduced it. Prior to this patch, every AR8035 PHY in U-boot had Tx delay enabled. After this patch, only those who define the interface as RGMII_TXID or RGMII_ID will. This is to be expected, but will nonetheless break the setups of those who didn't know they rely on Tx delay implicitly. Signed-off-by: Vladimir Oltean Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 3783d155e79..537c1a91251 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -63,10 +63,6 @@ static int ar8035_config(struct phy_device *phydev) regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018)); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100)); - if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { /* select debug reg 5 */ From 29602f9c4b8efd9afcb2212eda0e13483ca6ec5d Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 7 May 2020 00:11:49 +0200 Subject: [PATCH 204/237] phy: atheros: Use common functions for RGMII internal delays Signed-off-by: Vladimir Oltean Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 69 +++++++++++++++++++++++---------------- 1 file changed, 41 insertions(+), 28 deletions(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 537c1a91251..c0c2b4db396 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -12,16 +12,45 @@ #define AR803x_PHY_DEBUG_DATA_REG 0x1e #define AR803x_DEBUG_REG_5 0x5 -#define AR803x_RGMII_TX_CLK_DLY 0x100 +#define AR803x_RGMII_TX_CLK_DLY BIT(8) #define AR803x_DEBUG_REG_0 0x0 -#define AR803x_RGMII_RX_CLK_DLY 0x8000 +#define AR803x_RGMII_RX_CLK_DLY BIT(15) + +static void ar803x_enable_rx_delay(struct phy_device *phydev, bool on) +{ + int regval; + + phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, + AR803x_DEBUG_REG_0); + regval = phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG); + if (on) + regval |= AR803x_RGMII_RX_CLK_DLY; + else + regval &= ~AR803x_RGMII_RX_CLK_DLY; + phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, regval); +} + +static void ar803x_enable_tx_delay(struct phy_device *phydev, bool on) +{ + int regval; + + phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, + AR803x_DEBUG_REG_5); + regval = phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG); + if (on) + regval |= AR803x_RGMII_TX_CLK_DLY; + else + regval &= ~AR803x_RGMII_TX_CLK_DLY; + phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, regval); +} static int ar8021_config(struct phy_device *phydev) { phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); + phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, + AR803x_DEBUG_REG_5); + phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, 0x3D47); phydev->supported = phydev->drv->features; return 0; @@ -30,20 +59,12 @@ static int ar8021_config(struct phy_device *phydev) static int ar8031_config(struct phy_device *phydev) { if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || - phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { - phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, - AR803x_DEBUG_REG_5); - phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, - AR803x_RGMII_TX_CLK_DLY); - } + phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + ar803x_enable_tx_delay(phydev, true); if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || - phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { - phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, - AR803x_DEBUG_REG_0); - phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, - AR803x_RGMII_RX_CLK_DLY); - } + phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + ar803x_enable_rx_delay(phydev, true); phydev->supported = phydev->drv->features; @@ -64,20 +85,12 @@ static int ar8035_config(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018)); if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || - (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { - /* select debug reg 5 */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x5); - /* enable tx delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x0100); - } + (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) + ar803x_enable_tx_delay(phydev, true); if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || - (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) { - /* select debug reg 0 */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x0); - /* enable rx delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x8000); - } + (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) + ar803x_enable_rx_delay(phydev, true); phydev->supported = phydev->drv->features; From a234ae863a413d371a0abc36f9e0aa9c1726e331 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 7 May 2020 00:11:50 +0200 Subject: [PATCH 205/237] phy: atheros: Clarify the configuration of the CLK_25M output pin Also take the opportunity to use the phy_read_mmd and phy_write_mmd convenience functions. Signed-off-by: Vladimir Oltean Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index c0c2b4db396..1da18eb5d45 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -17,6 +17,15 @@ #define AR803x_DEBUG_REG_0 0x0 #define AR803x_RGMII_RX_CLK_DLY BIT(15) +/* CLK_25M register is at MMD 7, address 0x8016 */ +#define AR803x_CLK_25M_SEL_REG 0x8016 +/* AR8035: Select frequency on CLK_25M pin through bits 4:3 */ +#define AR8035_CLK_25M_FREQ_25M (0 | 0) +#define AR8035_CLK_25M_FREQ_50M (0 | BIT(3)) +#define AR8035_CLK_25M_FREQ_62M (BIT(4) | 0) +#define AR8035_CLK_25M_FREQ_125M (BIT(4) | BIT(3)) +#define AR8035_CLK_25M_MASK GENMASK(4, 3) + static void ar803x_enable_rx_delay(struct phy_device *phydev, bool on) { int regval; @@ -78,11 +87,11 @@ static int ar8035_config(struct phy_device *phydev) { int regval; - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); - regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018)); + /* Configure CLK_25M output clock at 125 MHz */ + regval = phy_read_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG); + regval &= ~AR8035_CLK_25M_MASK; /* No surprises */ + regval |= AR8035_CLK_25M_FREQ_125M; + phy_write_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG, regval); if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) From 13114f38e2ccea9386726d8b9831dfc310589548 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 7 May 2020 00:11:51 +0200 Subject: [PATCH 206/237] phy: atheros: Explicitly disable RGMII delays To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 1da18eb5d45..3e59c3f3915 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -70,10 +70,14 @@ static int ar8031_config(struct phy_device *phydev) if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ar803x_enable_tx_delay(phydev, true); + else + ar803x_enable_tx_delay(phydev, false); if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ar803x_enable_rx_delay(phydev, true); + else + ar803x_enable_rx_delay(phydev, false); phydev->supported = phydev->drv->features; @@ -96,10 +100,14 @@ static int ar8035_config(struct phy_device *phydev) if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) ar803x_enable_tx_delay(phydev, true); + else + ar803x_enable_tx_delay(phydev, false); if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) ar803x_enable_rx_delay(phydev, true); + else + ar803x_enable_rx_delay(phydev, false); phydev->supported = phydev->drv->features; From 4d4e4cf7798276bcb047b65cf80fde63fd347903 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 7 May 2020 00:11:52 +0200 Subject: [PATCH 207/237] phy: atheros: Clarify the intention of ar8021_config Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at the other bit positions, just like the other PHYs in the family do. Therefore, it is not necessary to hardcode the reserved values, but instead simply follow the read-modify-write procedure from the common function. Signed-off-by: Vladimir Oltean Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 3e59c3f3915..3cc162828ca 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -56,10 +56,10 @@ static void ar803x_enable_tx_delay(struct phy_device *phydev, bool on) static int ar8021_config(struct phy_device *phydev) { - phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200); - phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, - AR803x_DEBUG_REG_5); - phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, 0x3D47); + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); + + ar803x_enable_tx_delay(phydev, true); phydev->supported = phydev->drv->features; return 0; From f4d48f43b29756dac0f306eec3ca7ddf2821dd4e Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 7 May 2020 00:11:53 +0200 Subject: [PATCH 208/237] phy: atheros: fix AR8021 PHY ID mask The upper bits are all the OUI. Signed-off-by: Michael Walle Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 3cc162828ca..01953a13902 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -120,7 +120,7 @@ static int ar8035_config(struct phy_device *phydev) static struct phy_driver AR8021_driver = { .name = "AR8021", .uid = 0x4dd040, - .mask = 0x4ffff0, + .mask = 0xfffffff0, .features = PHY_GBIT_FEATURES, .config = ar8021_config, .startup = genphy_startup, From 30e3193128f95d7276311b50f4215f9a8625c3ba Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 7 May 2020 00:11:54 +0200 Subject: [PATCH 209/237] phy: atheros: use defines for PHY IDs Signed-off-by: Michael Walle Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 01953a13902..5ff5875d3df 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -26,6 +26,10 @@ #define AR8035_CLK_25M_FREQ_125M (BIT(4) | BIT(3)) #define AR8035_CLK_25M_MASK GENMASK(4, 3) +#define AR8021_PHY_ID 0x004dd040 +#define AR8031_PHY_ID 0x004dd074 +#define AR8035_PHY_ID 0x004dd072 + static void ar803x_enable_rx_delay(struct phy_device *phydev, bool on) { int regval; @@ -119,7 +123,7 @@ static int ar8035_config(struct phy_device *phydev) static struct phy_driver AR8021_driver = { .name = "AR8021", - .uid = 0x4dd040, + .uid = AR8021_PHY_ID, .mask = 0xfffffff0, .features = PHY_GBIT_FEATURES, .config = ar8021_config, @@ -129,7 +133,7 @@ static struct phy_driver AR8021_driver = { static struct phy_driver AR8031_driver = { .name = "AR8031/AR8033", - .uid = 0x4dd074, + .uid = AR8031_PHY_ID, .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, .config = ar8031_config, @@ -139,7 +143,7 @@ static struct phy_driver AR8031_driver = { static struct phy_driver AR8035_driver = { .name = "AR8035", - .uid = 0x4dd072, + .uid = AR8035_PHY_ID, .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, .config = ar8035_config, From f6ae47be1ac5f3b16ac2b702ffa89e5709711ce5 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 7 May 2020 00:11:55 +0200 Subject: [PATCH 210/237] phy: atheros: introduce debug read and write functions Provide functions to read and write the Atheros debug registers. Signed-off-by: Michael Walle Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 61 +++++++++++++++++++++++++++------------ 1 file changed, 43 insertions(+), 18 deletions(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 5ff5875d3df..660dcd9491d 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -30,32 +30,57 @@ #define AR8031_PHY_ID 0x004dd074 #define AR8035_PHY_ID 0x004dd072 -static void ar803x_enable_rx_delay(struct phy_device *phydev, bool on) +static int ar803x_debug_reg_read(struct phy_device *phydev, u16 reg) { - int regval; + int ret; - phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, - AR803x_DEBUG_REG_0); - regval = phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG); - if (on) - regval |= AR803x_RGMII_RX_CLK_DLY; - else - regval &= ~AR803x_RGMII_RX_CLK_DLY; - phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, regval); + ret = phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, + reg); + if (ret < 0) + return ret; + + return phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG); } -static void ar803x_enable_tx_delay(struct phy_device *phydev, bool on) +static int ar803x_debug_reg_mask(struct phy_device *phydev, u16 reg, + u16 clear, u16 set) { - int regval; + int val; + + val = ar803x_debug_reg_read(phydev, reg); + if (val < 0) + return val; + + val &= 0xffff; + val &= ~clear; + val |= set; + + return phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, + val); +} + +static int ar803x_enable_rx_delay(struct phy_device *phydev, bool on) +{ + u16 clear = 0, set = 0; - phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, - AR803x_DEBUG_REG_5); - regval = phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG); if (on) - regval |= AR803x_RGMII_TX_CLK_DLY; + set = AR803x_RGMII_RX_CLK_DLY; else - regval &= ~AR803x_RGMII_TX_CLK_DLY; - phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, regval); + clear = AR803x_RGMII_RX_CLK_DLY; + + return ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_0, clear, set); +} + +static int ar803x_enable_tx_delay(struct phy_device *phydev, bool on) +{ + u16 clear = 0, set = 0; + + if (on) + set = AR803x_RGMII_TX_CLK_DLY; + else + clear = AR803x_RGMII_TX_CLK_DLY; + + return ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_5, clear, set); } static int ar8021_config(struct phy_device *phydev) From 2b7721552a4cb4046a365a665fba3a3a848eb966 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 7 May 2020 00:11:56 +0200 Subject: [PATCH 211/237] phy: atheros: move delay config to common function Signed-off-by: Michael Walle Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 660dcd9491d..22035c2496d 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -94,19 +94,32 @@ static int ar8021_config(struct phy_device *phydev) return 0; } -static int ar8031_config(struct phy_device *phydev) +static int ar803x_delay_config(struct phy_device *phydev) { + int ret; + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) - ar803x_enable_tx_delay(phydev, true); + ret = ar803x_enable_tx_delay(phydev, true); else - ar803x_enable_tx_delay(phydev, false); + ret = ar803x_enable_tx_delay(phydev, false); if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) - ar803x_enable_rx_delay(phydev, true); + ret = ar803x_enable_rx_delay(phydev, true); else - ar803x_enable_rx_delay(phydev, false); + ret = ar803x_enable_rx_delay(phydev, false); + + return ret; +} + +static int ar8031_config(struct phy_device *phydev) +{ + int ret; + + ret = ar803x_delay_config(phydev); + if (ret < 0) + return ret; phydev->supported = phydev->drv->features; @@ -118,6 +131,7 @@ static int ar8031_config(struct phy_device *phydev) static int ar8035_config(struct phy_device *phydev) { + int ret; int regval; /* Configure CLK_25M output clock at 125 MHz */ @@ -126,17 +140,9 @@ static int ar8035_config(struct phy_device *phydev) regval |= AR8035_CLK_25M_FREQ_125M; phy_write_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG, regval); - if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || - (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) - ar803x_enable_tx_delay(phydev, true); - else - ar803x_enable_tx_delay(phydev, false); - - if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || - (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) - ar803x_enable_rx_delay(phydev, true); - else - ar803x_enable_rx_delay(phydev, false); + ret = ar803x_delay_config(phydev); + if (ret < 0) + return ret; phydev->supported = phydev->drv->features; From fe6293a8095998affd5e46e7968485fcc332e0fa Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 7 May 2020 00:11:57 +0200 Subject: [PATCH 212/237] phy: atheros: add device tree bindings and config Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. But this output can also be changed by software to other frequencies. This commit introduces a generic way to configure this output. Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V option needs an external supply voltage. This commit adds support to switch the internal LDO to 1.8V. Signed-off-by: Michael Walle Acked-by: Joe Hershberger --- doc/device-tree-bindings/net/phy/atheros.txt | 35 +++ drivers/net/phy/atheros.c | 226 ++++++++++++++++++- include/dt-bindings/net/qca-ar803x.h | 13 ++ 3 files changed, 271 insertions(+), 3 deletions(-) create mode 100644 doc/device-tree-bindings/net/phy/atheros.txt create mode 100644 include/dt-bindings/net/qca-ar803x.h diff --git a/doc/device-tree-bindings/net/phy/atheros.txt b/doc/device-tree-bindings/net/phy/atheros.txt new file mode 100644 index 00000000000..97e97b8c13d --- /dev/null +++ b/doc/device-tree-bindings/net/phy/atheros.txt @@ -0,0 +1,35 @@ +* Qualcomm Atheros PHY Device Tree binding + +Required properties: +- reg: PHY address + +Optional properties: +- qca,clk-out-frequency: Clock frequency of the CLK_25M pin in Hz. + Either 25000000, 50000000, 62500000 or 125000000. +- qca,clk-out-strength: Clock output buffer driver strength. + Supported values are defined in dt-bindings/net/qca-ar803x.h +- qca,keep-pll-enabled: Keep the PLL running if no link is present. + Don't go into hibernation mode. + Only supported on the AR8031/AR8033. +- vddio-supply: RGMII I/O voltage regulator + Only supported on the AR8031/AR8033. + +Optional subnodes: +- vddio-regulator: Initial data for the VDDIO regulator, as covered + doc/device-tree-bindings/regulator/regulator.txt + +Example: + #include + + ethernet-phy@0 { + reg = <0>; + qca-clk-out-frequency = <125000000>; + qca,keep-pll-enabled; + + vddio-supply = <&vddio>; + + vddio: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 22035c2496d..3cd301c50ed 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -4,21 +4,41 @@ * * Copyright 2011, 2013 Freescale Semiconductor, Inc. * author Andy Fleming + * Copyright (c) 2019 Michael Walle */ #include #include +#include +#include +#include #define AR803x_PHY_DEBUG_ADDR_REG 0x1d #define AR803x_PHY_DEBUG_DATA_REG 0x1e -#define AR803x_DEBUG_REG_5 0x5 -#define AR803x_RGMII_TX_CLK_DLY BIT(8) - +/* Debug registers */ #define AR803x_DEBUG_REG_0 0x0 #define AR803x_RGMII_RX_CLK_DLY BIT(15) +#define AR803x_DEBUG_REG_5 0x5 +#define AR803x_RGMII_TX_CLK_DLY BIT(8) + +#define AR803x_DEBUG_REG_1F 0x1f +#define AR803x_PLL_ON BIT(2) +#define AR803x_RGMII_1V8 BIT(3) + /* CLK_25M register is at MMD 7, address 0x8016 */ #define AR803x_CLK_25M_SEL_REG 0x8016 + +#define AR803x_CLK_25M_MASK GENMASK(4, 2) +#define AR803x_CLK_25M_25MHZ_XTAL 0 +#define AR803x_CLK_25M_25MHZ_DSP 1 +#define AR803x_CLK_25M_50MHZ_PLL 2 +#define AR803x_CLK_25M_50MHZ_DSP 3 +#define AR803x_CLK_25M_62_5MHZ_PLL 4 +#define AR803x_CLK_25M_62_5MHZ_DSP 5 +#define AR803x_CLK_25M_125MHZ_PLL 6 +#define AR803x_CLK_25M_125MHZ_DSP 7 + /* AR8035: Select frequency on CLK_25M pin through bits 4:3 */ #define AR8035_CLK_25M_FREQ_25M (0 | 0) #define AR8035_CLK_25M_FREQ_50M (0 | BIT(3)) @@ -26,10 +46,23 @@ #define AR8035_CLK_25M_FREQ_125M (BIT(4) | BIT(3)) #define AR8035_CLK_25M_MASK GENMASK(4, 3) +#define AR803x_CLK_25M_DR_MASK GENMASK(8, 7) +#define AR803x_CLK_25M_DR_FULL 0 +#define AR803x_CLK_25M_DR_HALF 1 +#define AR803x_CLK_25M_DR_QUARTER 2 + #define AR8021_PHY_ID 0x004dd040 #define AR8031_PHY_ID 0x004dd074 #define AR8035_PHY_ID 0x004dd072 +struct ar803x_priv { + int flags; +#define AR803x_FLAG_KEEP_PLL_ENABLED BIT(0) /* don't turn off internal PLL */ +#define AR803x_FLAG_RGMII_1V8 BIT(1) /* use 1.8V RGMII I/O voltage */ + u16 clk_25m_reg; + u16 clk_25m_mask; +}; + static int ar803x_debug_reg_read(struct phy_device *phydev, u16 reg) { int ret; @@ -113,14 +146,193 @@ static int ar803x_delay_config(struct phy_device *phydev) return ret; } +static int ar803x_regs_config(struct phy_device *phydev) +{ + struct ar803x_priv *priv = phydev->priv; + u16 set = 0, clear = 0; + int val; + int ret; + + /* no configuration available */ + if (!priv) + return 0; + + /* + * Only supported on the AR8031, AR8035 has strappings for the PLL mode + * as well as the RGMII voltage. + */ + if (phydev->drv->uid == AR8031_PHY_ID) { + if (priv->flags & AR803x_FLAG_KEEP_PLL_ENABLED) + set |= AR803x_PLL_ON; + else + clear |= AR803x_PLL_ON; + + if (priv->flags & AR803x_FLAG_RGMII_1V8) + set |= AR803x_RGMII_1V8; + else + clear |= AR803x_RGMII_1V8; + + ret = ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_1F, clear, + set); + if (ret < 0) + return ret; + } + + /* save the write access if the mask is empty */ + if (priv->clk_25m_mask) { + val = phy_read_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG); + if (val < 0) + return val; + val &= ~priv->clk_25m_mask; + val |= priv->clk_25m_reg; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, + AR803x_CLK_25M_SEL_REG, val); + if (ret < 0) + return ret; + } + + return 0; +} + +static int ar803x_of_init(struct phy_device *phydev) +{ +#if defined(CONFIG_DM_ETH) + struct ar803x_priv *priv; + ofnode node, vddio_reg_node; + u32 strength, freq, min_uV, max_uV; + int sel; + + node = phy_get_ofnode(phydev); + if (!ofnode_valid(node)) + return -EINVAL; + + priv = malloc(sizeof(*priv)); + if (!priv) + return -ENOMEM; + memset(priv, 0, sizeof(*priv)); + + phydev->priv = priv; + + debug("%s: found PHY node: %s\n", __func__, ofnode_get_name(node)); + + if (ofnode_read_bool(node, "qca,keep-pll-enabled")) + priv->flags |= AR803x_FLAG_KEEP_PLL_ENABLED; + + /* + * We can't use the regulator framework because the regulator is + * a subnode of the PHY. So just read the two properties we are + * interested in. + */ + vddio_reg_node = ofnode_find_subnode(node, "vddio-regulator"); + if (ofnode_valid(vddio_reg_node)) { + min_uV = ofnode_read_u32_default(vddio_reg_node, + "regulator-min-microvolt", 0); + max_uV = ofnode_read_u32_default(vddio_reg_node, + "regulator-max-microvolt", 0); + + if (min_uV != max_uV) { + free(priv); + return -EINVAL; + } + + switch (min_uV) { + case 1500000: + break; + case 1800000: + priv->flags |= AR803x_FLAG_RGMII_1V8; + break; + default: + free(priv); + return -EINVAL; + } + } + + /* + * Get the CLK_25M frequency from the device tree. Only XTAL and PLL + * sources are supported right now. There is also the possibilty to use + * the DSP as frequency reference, this is used for synchronous + * ethernet. + */ + if (!ofnode_read_u32(node, "qca,clk-out-frequency", &freq)) { + switch (freq) { + case 25000000: + sel = AR803x_CLK_25M_25MHZ_XTAL; + break; + case 50000000: + sel = AR803x_CLK_25M_50MHZ_PLL; + break; + case 62500000: + sel = AR803x_CLK_25M_62_5MHZ_PLL; + break; + case 125000000: + sel = AR803x_CLK_25M_125MHZ_PLL; + break; + default: + dev_err(phydev->dev, + "invalid qca,clk-out-frequency\n"); + free(priv); + return -EINVAL; + } + + priv->clk_25m_mask |= AR803x_CLK_25M_MASK; + priv->clk_25m_reg |= FIELD_PREP(AR803x_CLK_25M_MASK, sel); + /* + * Fixup for the AR8035 which only has two bits. The two + * remaining bits map to the same frequencies. + */ + if (phydev->drv->uid == AR8035_PHY_ID) { + u16 clear = AR803x_CLK_25M_MASK & AR8035_CLK_25M_MASK; + + priv->clk_25m_mask &= ~clear; + priv->clk_25m_reg &= ~clear; + } + } + + if (phydev->drv->uid == AR8031_PHY_ID && + !ofnode_read_u32(node, "qca,clk-out-strength", &strength)) { + switch (strength) { + case AR803X_STRENGTH_FULL: + sel = AR803x_CLK_25M_DR_FULL; + break; + case AR803X_STRENGTH_HALF: + sel = AR803x_CLK_25M_DR_HALF; + break; + case AR803X_STRENGTH_QUARTER: + sel = AR803x_CLK_25M_DR_QUARTER; + break; + default: + dev_err(phydev->dev, + "invalid qca,clk-out-strength\n"); + free(priv); + return -EINVAL; + } + priv->clk_25m_mask |= AR803x_CLK_25M_DR_MASK; + priv->clk_25m_reg |= FIELD_PREP(AR803x_CLK_25M_DR_MASK, sel); + } + + debug("%s: flags=%x clk_25m_reg=%04x clk_25m_mask=%04x\n", __func__, + priv->flags, priv->clk_25m_reg, priv->clk_25m_mask); +#endif + + return 0; +} + static int ar8031_config(struct phy_device *phydev) { int ret; + ret = ar803x_of_init(phydev); + if (ret < 0) + return ret; + ret = ar803x_delay_config(phydev); if (ret < 0) return ret; + ret = ar803x_regs_config(phydev); + if (ret < 0) + return ret; + phydev->supported = phydev->drv->features; genphy_config_aneg(phydev); @@ -134,6 +346,10 @@ static int ar8035_config(struct phy_device *phydev) int ret; int regval; + ret = ar803x_of_init(phydev); + if (ret < 0) + return ret; + /* Configure CLK_25M output clock at 125 MHz */ regval = phy_read_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG); regval &= ~AR8035_CLK_25M_MASK; /* No surprises */ @@ -144,6 +360,10 @@ static int ar8035_config(struct phy_device *phydev) if (ret < 0) return ret; + ret = ar803x_regs_config(phydev); + if (ret < 0) + return ret; + phydev->supported = phydev->drv->features; genphy_config_aneg(phydev); diff --git a/include/dt-bindings/net/qca-ar803x.h b/include/dt-bindings/net/qca-ar803x.h new file mode 100644 index 00000000000..9c046c7242e --- /dev/null +++ b/include/dt-bindings/net/qca-ar803x.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Device Tree constants for the Qualcomm Atheros AR803x PHYs + */ + +#ifndef _DT_BINDINGS_QCA_AR803X_H +#define _DT_BINDINGS_QCA_AR803X_H + +#define AR803X_STRENGTH_FULL 0 +#define AR803X_STRENGTH_HALF 1 +#define AR803X_STRENGTH_QUARTER 2 + +#endif From 6333cbb3817ed551cd7d4e92f7359c73ccc567fc Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 7 May 2020 00:11:58 +0200 Subject: [PATCH 213/237] phy: atheros: ar8035: remove static clock config We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 3cd301c50ed..31427331052 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -38,12 +38,6 @@ #define AR803x_CLK_25M_62_5MHZ_DSP 5 #define AR803x_CLK_25M_125MHZ_PLL 6 #define AR803x_CLK_25M_125MHZ_DSP 7 - -/* AR8035: Select frequency on CLK_25M pin through bits 4:3 */ -#define AR8035_CLK_25M_FREQ_25M (0 | 0) -#define AR8035_CLK_25M_FREQ_50M (0 | BIT(3)) -#define AR8035_CLK_25M_FREQ_62M (BIT(4) | 0) -#define AR8035_CLK_25M_FREQ_125M (BIT(4) | BIT(3)) #define AR8035_CLK_25M_MASK GENMASK(4, 3) #define AR803x_CLK_25M_DR_MASK GENMASK(8, 7) @@ -344,18 +338,11 @@ static int ar8031_config(struct phy_device *phydev) static int ar8035_config(struct phy_device *phydev) { int ret; - int regval; ret = ar803x_of_init(phydev); if (ret < 0) return ret; - /* Configure CLK_25M output clock at 125 MHz */ - regval = phy_read_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG); - regval &= ~AR8035_CLK_25M_MASK; /* No surprises */ - regval |= AR8035_CLK_25M_FREQ_125M; - phy_write_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG, regval); - ret = ar803x_delay_config(phydev); if (ret < 0) return ret; From 8737c65fe4e315af923efde05e5f30041944be08 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 7 May 2020 00:11:59 +0200 Subject: [PATCH 214/237] phy: atheros: consolidate {ar8031|ar8035}_config() The two functions are now exactly the same, remove one of them. Signed-off-by: Michael Walle Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 30 +++--------------------------- 1 file changed, 3 insertions(+), 27 deletions(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 31427331052..47ff9f8d44c 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -311,31 +311,7 @@ static int ar803x_of_init(struct phy_device *phydev) return 0; } -static int ar8031_config(struct phy_device *phydev) -{ - int ret; - - ret = ar803x_of_init(phydev); - if (ret < 0) - return ret; - - ret = ar803x_delay_config(phydev); - if (ret < 0) - return ret; - - ret = ar803x_regs_config(phydev); - if (ret < 0) - return ret; - - phydev->supported = phydev->drv->features; - - genphy_config_aneg(phydev); - genphy_restart_aneg(phydev); - - return 0; -} - -static int ar8035_config(struct phy_device *phydev) +static int ar803x_config(struct phy_device *phydev) { int ret; @@ -374,7 +350,7 @@ static struct phy_driver AR8031_driver = { .uid = AR8031_PHY_ID, .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, - .config = ar8031_config, + .config = ar803x_config, .startup = genphy_startup, .shutdown = genphy_shutdown, }; @@ -384,7 +360,7 @@ static struct phy_driver AR8035_driver = { .uid = AR8035_PHY_ID, .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, - .config = ar8035_config, + .config = ar803x_config, .startup = genphy_startup, .shutdown = genphy_shutdown, }; From b37a0b5c896f07958aa8c6759abe83c5a08a4de9 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Mon, 4 May 2020 14:38:29 +0200 Subject: [PATCH 215/237] kbuild: efi: Avoid rebuilding efi targets Add a couple of missing targets so that helloworld and other efi targets are not needlessly rebuilt. CC: Heinrich Schuchardt Signed-off-by: Jan Kiszka Tested-by: Heinrich Schuchardt --- lib/efi_loader/Makefile | 1 + scripts/Makefile.lib | 2 ++ 2 files changed, 3 insertions(+) diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index eff3c25ec30..84d61df55b9 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -17,6 +17,7 @@ CFLAGS_REMOVE_helloworld.o := $(CFLAGS_NON_EFI) ifneq ($(CONFIG_CMD_BOOTEFI_HELLO_COMPILE),) always += helloworld.efi +targets += helloworld.o endif obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 63fbadd757d..734001c952a 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -418,6 +418,8 @@ $(obj)/efi_reloc.o: $(srctree)/arch/$(ARCH)/lib/$(EFI_RELOC:.o=.c) $(recordmcoun $(obj)/%_efi.so: $(obj)/%.o $(obj)/efi_crt0.o $(obj)/efi_reloc.o $(obj)/efi_freestanding.o $(call cmd,efi_ld) +targets += $(obj)/efi_crt0.o $(obj)/efi_reloc.o $(obj)/efi_freestanding.o + # ACPI # --------------------------------------------------------------------------- # From 549b79e8e04930f515ace28556d1cea779a1086a Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 6 May 2020 01:28:08 +0200 Subject: [PATCH 216/237] efi_loader: remove redundant assignment in dp_fill() The value of dp is overwritten without being used. Signed-off-by: Heinrich Schuchardt --- lib/efi_loader/efi_device_path.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c index 73f1fe75a83..f9349484a66 100644 --- a/lib/efi_loader/efi_device_path.c +++ b/lib/efi_loader/efi_device_path.c @@ -530,7 +530,7 @@ __maybe_unused static void *dp_fill(void *buf, struct udevice *dev) #ifdef CONFIG_SANDBOX case UCLASS_ROOT: { /* stop traversing parents at this point: */ - struct efi_device_path_vendor *dp = buf; + struct efi_device_path_vendor *dp; struct blk_desc *desc = dev_get_uclass_platdata(dev); dp_fill(buf, dev->parent); From 3fdff6be40b01423aacf2c02eb3b4ef6d2186caf Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 6 May 2020 01:37:25 +0200 Subject: [PATCH 217/237] efi_loader: error handling in efi_set_variable_common(). Fix unreachable code. Free memory on error. Signed-off-by: Heinrich Schuchardt --- lib/efi_loader/efi_variable.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index 58f8fae358c..33df52e663e 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -981,7 +981,7 @@ static efi_status_t efi_set_variable_common(u16 *variable_name, if (append) { old_data = malloc(old_size); if (!old_data) { - return EFI_OUT_OF_RESOURCES; + ret = EFI_OUT_OF_RESOURCES; goto err; } ret = EFI_CALL(efi_get_variable(variable_name, vendor, From 306bf6e7ff9b267e4c38f8f38900cb93fa96b62b Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 6 May 2020 01:51:04 +0200 Subject: [PATCH 218/237] efi_loader: do not unnecessarily use EFI_CALL() There is no need to call efi_get_variable() instead of efi_get_variable_common(). So let's use the internal function. Move forward declarations to the top of the file. Signed-off-by: Heinrich Schuchardt --- lib/efi_loader/efi_variable.c | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index 33df52e663e..568bd3ccfdc 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -30,6 +30,18 @@ static u8 efi_vendor_keys; #define READ_ONLY BIT(31) +static efi_status_t efi_get_variable_common(u16 *variable_name, + const efi_guid_t *vendor, + u32 *attributes, + efi_uintn_t *data_size, void *data); + +static efi_status_t efi_set_variable_common(u16 *variable_name, + const efi_guid_t *vendor, + u32 attributes, + efi_uintn_t data_size, + const void *data, + bool ro_check); + /* * Mapping between EFI variables and u-boot variables: * @@ -169,13 +181,6 @@ static const char *parse_attr(const char *str, u32 *attrp, u64 *timep) return str; } -static efi_status_t efi_set_variable_common(u16 *variable_name, - const efi_guid_t *vendor, - u32 attributes, - efi_uintn_t data_size, - const void *data, - bool ro_check); - /** * efi_set_secure_state - modify secure boot state variables * @sec_boot: value of SecureBoot @@ -300,8 +305,8 @@ static efi_status_t efi_init_secure_state(void) */ size = 0; - ret = EFI_CALL(efi_get_variable(L"PK", &efi_global_variable_guid, - NULL, &size, NULL)); + ret = efi_get_variable_common(L"PK", &efi_global_variable_guid, + NULL, &size, NULL); if (ret == EFI_BUFFER_TOO_SMALL) { if (IS_ENABLED(CONFIG_EFI_SECURE_BOOT)) mode = EFI_MODE_USER; @@ -587,8 +592,7 @@ static efi_status_t efi_variable_authenticate(u16 *variable, } #endif /* CONFIG_EFI_SECURE_BOOT */ -static -efi_status_t EFIAPI efi_get_variable_common(u16 *variable_name, +static efi_status_t efi_get_variable_common(u16 *variable_name, const efi_guid_t *vendor, u32 *attributes, efi_uintn_t *data_size, void *data) @@ -893,8 +897,8 @@ static efi_status_t efi_set_variable_common(u16 *variable_name, /* check if a variable exists */ old_size = 0; attr = 0; - ret = EFI_CALL(efi_get_variable(variable_name, vendor, &attr, - &old_size, NULL)); + ret = efi_get_variable_common(variable_name, vendor, &attr, + &old_size, NULL); append = !!(attributes & EFI_VARIABLE_APPEND_WRITE); attributes &= ~(u32)EFI_VARIABLE_APPEND_WRITE; delete = !append && (!data_size || !attributes); @@ -984,8 +988,8 @@ static efi_status_t efi_set_variable_common(u16 *variable_name, ret = EFI_OUT_OF_RESOURCES; goto err; } - ret = EFI_CALL(efi_get_variable(variable_name, vendor, - &attr, &old_size, old_data)); + ret = efi_get_variable_common(variable_name, vendor, + &attr, &old_size, old_data); if (ret != EFI_SUCCESS) goto err; } else { From 9900e4623a9a826447b0467cabc29e09fdf29fb6 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 6 May 2020 02:01:34 +0200 Subject: [PATCH 219/237] efi_loader: use logical and in do_env_print_efi() If we want to check if two booleans are true, we should use a logical conjunction (&&) and not a bitwise and-operator (&). Signed-off-by: Heinrich Schuchardt --- cmd/nvedit_efi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/nvedit_efi.c b/cmd/nvedit_efi.c index 837e39e0217..6f69a84feaa 100644 --- a/cmd/nvedit_efi.c +++ b/cmd/nvedit_efi.c @@ -298,7 +298,7 @@ int do_env_print_efi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return CMD_RET_USAGE; /* -a already specified */ - if (!default_guid & guid_any) + if (!default_guid && guid_any) return CMD_RET_USAGE; argc--; From 42a426e027df472714e8d6209cafac291935c331 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 6 May 2020 20:32:31 +0200 Subject: [PATCH 220/237] efi_loader: put device tree into EfiACPIReclaimMemory According to the UEFI spec ACPI tables should be placed in EfiACPIReclaimMemory. Let's do the same with the device tree. Suggested-by: Ard Biesheuvel Cc: Grant Likely Signed-off-by: Heinrich Schuchardt --- cmd/bootefi.c | 4 ++-- lib/efi_selftest/efi_selftest_memory.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 54b4b8f9845..06573b14e9b 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -127,13 +127,13 @@ static efi_status_t copy_fdt(void **fdtp) new_fdt_addr = (uintptr_t)map_sysmem(fdt_ram_start + 0x7f00000 + fdt_size, 0); ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS, - EFI_BOOT_SERVICES_DATA, fdt_pages, + EFI_ACPI_RECLAIM_MEMORY, fdt_pages, &new_fdt_addr); if (ret != EFI_SUCCESS) { /* If we can't put it there, put it somewhere */ new_fdt_addr = (ulong)memalign(EFI_PAGE_SIZE, fdt_size); ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS, - EFI_BOOT_SERVICES_DATA, fdt_pages, + EFI_ACPI_RECLAIM_MEMORY, fdt_pages, &new_fdt_addr); if (ret != EFI_SUCCESS) { printf("ERROR: Failed to reserve space for FDT\n"); diff --git a/lib/efi_selftest/efi_selftest_memory.c b/lib/efi_selftest/efi_selftest_memory.c index e71732dc6db..4d32a280061 100644 --- a/lib/efi_selftest/efi_selftest_memory.c +++ b/lib/efi_selftest/efi_selftest_memory.c @@ -176,9 +176,9 @@ static int execute(void) /* Check memory reservation for the device tree */ if (fdt_addr && find_in_memory_map(map_size, memory_map, desc_size, fdt_addr, - EFI_BOOT_SERVICES_DATA) != EFI_ST_SUCCESS) { + EFI_ACPI_RECLAIM_MEMORY) != EFI_ST_SUCCESS) { efi_st_error - ("Device tree not marked as boot services data\n"); + ("Device tree not marked as ACPI reclaim memory\n"); return EFI_ST_FAILURE; } return EFI_ST_SUCCESS; From 9ad15227bb92acc2bf73c60da1bcf2ae3774246d Mon Sep 17 00:00:00 2001 From: Patrick Wildt Date: Thu, 7 May 2020 02:13:18 +0200 Subject: [PATCH 221/237] efi_loader: efi_variable_parse_signature() returns NULL on error efi_variable_parse_signature() returns NULL on error, so IS_ERR() is an incorrect check. The goto err leads to pkcs7_free_message(), which works fine on a NULL ptr. Signed-off-by: Patrick Wildt Reviewed-by: AKASHI Takahiro --- lib/efi_loader/efi_variable.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index 568bd3ccfdc..60c12017578 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -524,9 +524,8 @@ static efi_status_t efi_variable_authenticate(u16 *variable, var_sig = efi_variable_parse_signature(auth->auth_info.cert_data, auth->auth_info.hdr.dwLength - sizeof(auth->auth_info)); - if (IS_ERR(var_sig)) { + if (!var_sig) { debug("Parsing variable's signature failed\n"); - var_sig = NULL; goto err; } From 6f146155f879ff42d465f0cca8ec2a7f8cb0961e Mon Sep 17 00:00:00 2001 From: Patrick Wildt Date: Thu, 7 May 2020 02:17:14 +0200 Subject: [PATCH 222/237] efi_loader: pkcs7_parse_message() returns error pointer Since pkcs7_parse_message() returns an error pointer, we must not check for NULL. We have to explicitly set msg to NULL in the error case, otherwise the call to pkcs7_free_message() on the goto err path will assume it's a valid object. Signed-off-by: Patrick Wildt Add missing include linux/err.h Reviewed-by: Heinrich Schuchardt --- lib/efi_loader/efi_image_loader.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c index 5a9a6424cc1..ac4f65c9d82 100644 --- a/lib/efi_loader/efi_image_loader.c +++ b/lib/efi_loader/efi_image_loader.c @@ -14,6 +14,7 @@ #include #include #include "crypto/pkcs7_parser.h" +#include const efi_guid_t efi_global_variable_guid = EFI_GLOBAL_VARIABLE_GUID; const efi_guid_t efi_guid_device_path = EFI_DEVICE_PATH_PROTOCOL_GUID; @@ -538,8 +539,9 @@ static bool efi_image_authenticate(void *efi, size_t efi_size) } msg = pkcs7_parse_message((void *)wincert + sizeof(*wincert), wincert->dwLength - sizeof(*wincert)); - if (!msg) { + if (IS_ERR(msg)) { debug("Parsing image's signature failed\n"); + msg = NULL; goto err; } From d7ca3ce3d3b990503cb6e0bafad91aa2a7c96b9d Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 7 May 2020 17:57:43 +0200 Subject: [PATCH 223/237] efi_loader: crypto/pkcs7_parser.h is not a local include User <> and not "" for referencing a global include. Signed-off-by: Heinrich Schuchardt --- lib/efi_loader/efi_image_loader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c index ac4f65c9d82..4e075ae416e 100644 --- a/lib/efi_loader/efi_image_loader.c +++ b/lib/efi_loader/efi_image_loader.c @@ -13,7 +13,7 @@ #include #include #include -#include "crypto/pkcs7_parser.h" +#include #include const efi_guid_t efi_global_variable_guid = EFI_GLOBAL_VARIABLE_GUID; From b11dc33e361a84ca41604e49ec22635bf5d2eb4c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 8 May 2020 09:08:39 -0400 Subject: [PATCH 224/237] configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini --- configs/MPC8548CDS_36BIT_defconfig | 2 +- configs/MPC8548CDS_defconfig | 2 +- configs/MPC8548CDS_legacy_defconfig | 2 +- configs/P1010RDB-PA_36BIT_NAND_defconfig | 15 +++++++-------- configs/P1010RDB-PA_36BIT_NOR_defconfig | 17 ++++++++--------- configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 15 +++++++-------- configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 15 +++++++-------- configs/P1010RDB-PA_NAND_defconfig | 15 +++++++-------- configs/P1010RDB-PA_NOR_defconfig | 17 ++++++++--------- configs/P1010RDB-PA_SDCARD_defconfig | 15 +++++++-------- configs/P1010RDB-PA_SPIFLASH_defconfig | 15 +++++++-------- configs/P1010RDB-PB_36BIT_NAND_defconfig | 15 +++++++-------- configs/P1010RDB-PB_36BIT_NOR_defconfig | 17 ++++++++--------- configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 15 +++++++-------- configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 15 +++++++-------- configs/P1010RDB-PB_NAND_defconfig | 17 ++++++++--------- configs/P1010RDB-PB_NOR_defconfig | 19 +++++++++---------- configs/P1010RDB-PB_SDCARD_defconfig | 15 +++++++-------- configs/P1010RDB-PB_SPIFLASH_defconfig | 15 +++++++-------- configs/P1020RDB-PC_36BIT_NAND_defconfig | 5 ++--- configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 5 ++--- configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 5 ++--- configs/P1020RDB-PC_36BIT_defconfig | 5 ++--- configs/P1020RDB-PC_NAND_defconfig | 5 ++--- configs/P1020RDB-PC_SDCARD_defconfig | 5 ++--- configs/P1020RDB-PC_SPIFLASH_defconfig | 5 ++--- configs/P1020RDB-PC_defconfig | 5 ++--- configs/P1020RDB-PD_NAND_defconfig | 5 ++--- configs/P1020RDB-PD_SDCARD_defconfig | 5 ++--- configs/P1020RDB-PD_SPIFLASH_defconfig | 5 ++--- configs/P1020RDB-PD_defconfig | 5 ++--- configs/P2020RDB-PC_36BIT_NAND_defconfig | 5 ++--- configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 5 ++--- configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 5 ++--- configs/P2020RDB-PC_36BIT_defconfig | 5 ++--- configs/P2020RDB-PC_NAND_defconfig | 5 ++--- configs/P2020RDB-PC_SDCARD_defconfig | 5 ++--- configs/P2020RDB-PC_SPIFLASH_defconfig | 5 ++--- configs/P2020RDB-PC_defconfig | 5 ++--- configs/P2041RDB_NAND_defconfig | 2 +- configs/P2041RDB_SDCARD_defconfig | 2 +- configs/P2041RDB_SPIFLASH_defconfig | 2 +- configs/P2041RDB_defconfig | 2 +- configs/P3041DS_NAND_defconfig | 2 +- configs/P3041DS_SDCARD_defconfig | 2 +- configs/P3041DS_SPIFLASH_defconfig | 2 +- configs/P3041DS_defconfig | 2 +- configs/P4080DS_SDCARD_defconfig | 2 +- configs/P4080DS_SPIFLASH_defconfig | 2 +- configs/P4080DS_defconfig | 2 +- configs/P5040DS_NAND_defconfig | 2 +- configs/P5040DS_SDCARD_defconfig | 2 +- configs/P5040DS_SPIFLASH_defconfig | 2 +- configs/P5040DS_defconfig | 2 +- configs/T1024RDB_NAND_defconfig | 5 ++--- configs/T1024RDB_SDCARD_defconfig | 5 ++--- configs/T1024RDB_SPIFLASH_defconfig | 5 ++--- configs/T1024RDB_defconfig | 5 ++--- configs/T1042D4RDB_NAND_defconfig | 4 ++-- configs/T1042D4RDB_SDCARD_defconfig | 4 ++-- configs/T1042D4RDB_SPIFLASH_defconfig | 4 ++-- configs/T1042D4RDB_defconfig | 4 ++-- configs/T2080QDS_NAND_defconfig | 2 +- configs/T2080QDS_SDCARD_defconfig | 2 +- configs/T2080QDS_SECURE_BOOT_defconfig | 2 +- configs/T2080QDS_SPIFLASH_defconfig | 2 +- configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 2 +- configs/T2080QDS_defconfig | 2 +- configs/T2080RDB_NAND_defconfig | 2 +- configs/T2080RDB_SDCARD_defconfig | 2 +- configs/T2080RDB_SPIFLASH_defconfig | 2 +- configs/T2080RDB_defconfig | 2 +- configs/T4240RDB_SDCARD_defconfig | 2 +- configs/T4240RDB_defconfig | 2 +- configs/coreboot64_defconfig | 2 +- configs/imx8mq_phanbell_defconfig | 6 +++--- configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1028aqds_tfa_defconfig | 2 +- configs/ls1028aqds_tfa_lpuart_defconfig | 4 ++-- configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1028ardb_tfa_defconfig | 2 +- configs/ls1088aqds_defconfig | 2 +- configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1088aqds_qspi_defconfig | 2 +- configs/ls1088aqds_sdcard_ifc_defconfig | 2 +- configs/ls1088aqds_sdcard_qspi_defconfig | 2 +- configs/ls1088aqds_tfa_defconfig | 2 +- configs/ls2080aqds_SECURE_BOOT_defconfig | 2 +- configs/ls2080aqds_defconfig | 2 +- configs/ls2080aqds_nand_defconfig | 2 +- configs/ls2080aqds_qspi_defconfig | 2 +- configs/ls2080aqds_sdcard_defconfig | 2 +- configs/ls2080ardb_SECURE_BOOT_defconfig | 2 +- configs/ls2080ardb_defconfig | 2 +- configs/ls2080ardb_nand_defconfig | 2 +- configs/ls2081ardb_defconfig | 2 +- configs/ls2088aqds_tfa_defconfig | 2 +- configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls2088ardb_qspi_defconfig | 2 +- configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls2088ardb_tfa_defconfig | 2 +- configs/mt7623n_bpir2_defconfig | 6 ------ configs/nanopi-m4-2gb-rk3399_defconfig | 8 +++----- configs/roc-pc-mezzanine-rk3399_defconfig | 8 +++----- configs/vexpress_aemv8a_juno_defconfig | 4 ++-- 105 files changed, 242 insertions(+), 292 deletions(-) diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 84ba9422d61..010e375740c 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -23,6 +23,7 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b" CONFIG_ENV_ADDR=0xFFF60000 CONFIG_DM=y +CONFIG_DM_I2C=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y @@ -45,4 +46,3 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y -CONFIG_DM_I2C=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 242487524e5..deaa69d1349 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -22,6 +22,7 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds" CONFIG_ENV_ADDR=0xFFF60000 CONFIG_DM=y +CONFIG_DM_I2C=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y @@ -44,4 +45,3 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y -CONFIG_DM_I2C=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 43a1dff182b..ab6f6eacd66 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -22,6 +22,7 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds" CONFIG_ENV_ADDR=0xFFF60000 CONFIG_DM=y +CONFIG_DM_I2C=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y @@ -44,4 +45,3 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y -CONFIG_DM_I2C=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index 5280a1d070a..da04cab0142 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -10,8 +10,6 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" -CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" @@ -41,14 +39,17 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -71,16 +72,14 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_DM=y +CONFIG_MII=y +CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index b83e99f8f76..e6edd395e78 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -3,10 +3,8 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_MPC85xx=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P1010RDB_PA=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" -CONFIG_OF_CONTROL=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -24,14 +22,17 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 +CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -53,16 +54,14 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_DM=y +CONFIG_MII=y +CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index a1b08b17f92..dcd606b0c2e 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -11,8 +11,6 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" -CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -36,14 +34,17 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -65,16 +66,14 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_DM=y +CONFIG_MII=y +CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 2b336f4a92c..c0800c8d7dd 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -13,8 +13,6 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" -CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -38,14 +36,17 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -67,16 +68,14 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_DM=y +CONFIG_MII=y +CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index 6062fd8d0f6..29ba692ca16 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -10,8 +10,6 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" -CONFIG_OF_CONTROL=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_FIT=y @@ -40,14 +38,17 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -70,16 +71,14 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_DM=y +CONFIG_MII=y +CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index 4ee53e85f78..d8f87b5dacb 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -3,10 +3,8 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_MPC85xx=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P1010RDB_PA=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" -CONFIG_OF_CONTROL=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -23,14 +21,17 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 +CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -52,16 +53,14 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_DM=y +CONFIG_MII=y +CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index f4e89592b8a..97110825291 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -11,8 +11,6 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" -CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -35,14 +33,17 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -64,16 +65,14 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_DM=y +CONFIG_MII=y +CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index 6d4175e2d1d..de2ac2235f9 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -13,8 +13,6 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" -CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -37,14 +35,17 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -66,16 +67,14 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_DM=y +CONFIG_MII=y +CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 123c044cf78..9f4876dd13a 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -10,8 +10,6 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" -CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" @@ -41,14 +39,17 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -71,16 +72,14 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_DM=y +CONFIG_MII=y +CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 1e149f965db..e85af32e2c0 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -3,10 +3,8 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_MPC85xx=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P1010RDB_PB=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" -CONFIG_OF_CONTROL=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -24,14 +22,17 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 +CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -53,16 +54,14 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_DM=y +CONFIG_MII=y +CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index aeb7e16467a..45feab4ee4d 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -11,8 +11,6 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" -CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -36,14 +34,17 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -65,16 +66,14 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_DM=y +CONFIG_MII=y +CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 7b6aaf64cbe..3cd94f84ea5 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -13,8 +13,6 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" -CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -38,14 +36,17 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -67,16 +68,14 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_DM=y +CONFIG_MII=y +CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 0af9e1795aa..ddfe7b43a13 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -10,8 +10,6 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" -CONFIG_OF_CONTROL=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_FIT=y @@ -40,14 +38,17 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -69,17 +70,15 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y -CONFIG_DM=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 73fe54d13a3..6011f8a9d8e 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -3,10 +3,8 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_MPC85xx=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P1010RDB_PB=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" -CONFIG_OF_CONTROL=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -23,14 +21,17 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 +CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -51,17 +52,15 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y -CONFIG_DM=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index d373cd28902..65f86fff603 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -11,8 +11,6 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" -CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -35,14 +33,17 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -64,16 +65,14 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_DM=y +CONFIG_MII=y +CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index 88fc5fe5aee..f71ee19ba66 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -13,8 +13,6 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" -CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -37,14 +35,17 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -66,16 +67,14 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_DM=y +CONFIG_MII=y +CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index cdcdefd9899..6ee52fe5e7d 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -39,7 +39,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y @@ -49,6 +48,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -77,10 +77,9 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 0fb3507e495..489b91d8e7e 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y @@ -45,6 +44,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -72,10 +72,9 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 24fdda7656d..4a8e4e3726b 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -37,7 +37,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y @@ -47,6 +46,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -74,10 +74,9 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index b0a3e0f1884..f9a4b735ca0 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -24,7 +24,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y @@ -34,6 +33,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -61,10 +61,9 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index d94885dcbd6..5c8231cba20 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -38,7 +38,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y @@ -48,6 +47,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -76,10 +76,9 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index c324faff6dc..ad2bb90a49e 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -34,7 +34,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y @@ -44,6 +43,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -71,10 +71,9 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 4058e918958..b8055e49b0c 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -36,7 +36,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y @@ -46,6 +45,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -73,10 +73,9 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 58cb5845251..a71985374e0 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -23,7 +23,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y @@ -33,6 +32,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -60,10 +60,9 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 37b174623f6..0043fd5f66f 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -38,7 +38,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y @@ -51,6 +50,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -80,10 +80,9 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index df89dcfc76a..cb0a8aec657 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -34,7 +34,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y @@ -47,6 +46,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -75,10 +75,9 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 68e3970d6d2..35e60ca8569 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -36,7 +36,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y @@ -49,6 +48,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -77,10 +77,9 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index 6251ca268ad..d7f19c3d96f 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -23,7 +23,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y @@ -36,6 +35,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -64,10 +64,9 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 950fabef219..3e6ea64ee32 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -40,7 +40,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y @@ -53,6 +52,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -82,10 +82,9 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index e9b21d2d7b9..187cbee0d62 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -36,7 +36,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y @@ -49,6 +48,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -77,10 +77,9 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 6de28bd0c5b..88c92240014 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -38,7 +38,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y @@ -51,6 +50,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -79,10 +79,9 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index c48e993b71f..88e24c30bad 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -25,7 +25,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y @@ -38,6 +37,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -66,10 +66,9 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 8d7a7891fb0..dda34dd43ec 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -39,7 +39,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y @@ -52,6 +51,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -81,10 +81,9 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 280b190be40..c2b6ad5f322 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y @@ -48,6 +47,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -76,10 +76,9 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index e0ebe44cac7..3ec208ee00c 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -37,7 +37,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y @@ -50,6 +49,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -78,10 +78,9 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index dd5c14e4cba..0f0a6ad810e 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -24,7 +24,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y @@ -37,6 +36,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -65,10 +65,9 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 79dcf659549..13b20dd1c6c 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -32,6 +32,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -61,4 +62,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 8be3f7f0530..d99c15342df 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -32,6 +32,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -60,4 +61,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 973a37fdba7..78a2a97064f 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -33,6 +33,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -61,4 +62,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index 21db59492f6..0b9625e91e2 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -31,6 +31,7 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -59,4 +60,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig index bee937b65b9..55613ccacd0 100644 --- a/configs/P3041DS_NAND_defconfig +++ b/configs/P3041DS_NAND_defconfig @@ -32,6 +32,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -61,4 +62,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig index 74f1d0b3b6b..b52068d050d 100644 --- a/configs/P3041DS_SDCARD_defconfig +++ b/configs/P3041DS_SDCARD_defconfig @@ -32,6 +32,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -60,4 +61,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig index 9004e8eb5e3..3af52b90e83 100644 --- a/configs/P3041DS_SPIFLASH_defconfig +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -33,6 +33,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -61,4 +62,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig index 58f585c6c73..cc3234c6b1b 100644 --- a/configs/P3041DS_defconfig +++ b/configs/P3041DS_defconfig @@ -31,6 +31,7 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -59,4 +60,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index 02d92449583..18ad56ac8da 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -32,6 +32,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -59,4 +60,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index fa1b8d94465..81a513bec91 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -33,6 +33,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -60,4 +61,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig index 674eca65acb..52db2e06c7e 100644 --- a/configs/P4080DS_defconfig +++ b/configs/P4080DS_defconfig @@ -31,6 +31,7 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -58,4 +59,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index 79155e8a656..efffb706fbb 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -33,6 +33,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -62,4 +63,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index d5da79486c7..fdd39acbaf3 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -32,6 +32,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -60,4 +61,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index 359f7ca3d57..3f4642f4e08 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -33,6 +33,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -61,4 +62,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index ab64a547f3d..d2a2e02dcd0 100644 --- a/configs/P5040DS_defconfig +++ b/configs/P5040DS_defconfig @@ -31,6 +31,7 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -59,4 +60,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index f024d93da17..9230c01a681 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -41,7 +41,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y @@ -53,6 +52,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -76,10 +76,9 @@ CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index ebf42b40fe5..2e1954486fd 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -39,7 +39,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y @@ -51,6 +50,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -73,10 +73,9 @@ CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 9bc31496306..daf00b8fbd0 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -41,7 +41,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y @@ -54,6 +53,7 @@ CONFIG_ENV_ADDR=0xFFFC9000 CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -76,10 +76,9 @@ CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index f25fee0c8f6..84e8f3b3352 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -26,7 +26,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_MP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y @@ -39,6 +38,7 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -61,10 +61,9 @@ CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 26d342db761..1602fb890e8 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -51,6 +51,7 @@ CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -75,6 +76,7 @@ CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y @@ -82,5 +84,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 5c6ef3527b1..a4a31bfd623 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -49,6 +49,7 @@ CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -72,6 +73,7 @@ CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y @@ -79,5 +81,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 7b6e375ed92..697c08dbfac 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -52,6 +52,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0xFFFC9000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -75,6 +76,7 @@ CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y @@ -82,5 +84,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 3e2156b6ca7..70ddffb3a75 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -37,6 +37,7 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -60,6 +61,7 @@ CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y @@ -67,5 +69,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y -CONFIG_DM_I2C=y -CONFIG_DM_RTC=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index 0b2e01bb0eb..52255ed1204 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -47,6 +47,7 @@ CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -80,4 +81,3 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_DM_I2C=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 33eb4cdddbd..ba57ea33b1d 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -45,6 +45,7 @@ CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -77,4 +78,3 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_DM_I2C=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index 4119bfbd1f9..9b3f709c87f 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -32,6 +32,7 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -67,4 +68,3 @@ CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_DM_I2C=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 7183728251c..5aa45f5a892 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -48,6 +48,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0xFFFC9000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -80,4 +81,3 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_DM_I2C=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index aa0c4e3106f..4958435ef4b 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -30,6 +30,7 @@ CONFIG_ENV_IS_IN_REMOTE=y CONFIG_ENV_ADDR=0xFFE20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -57,4 +58,3 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_DM_I2C=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index 1f00e6ad7ce..602bf577e07 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -33,6 +33,7 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -65,4 +66,3 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_DM_I2C=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index f7206a9cbb6..4485529015b 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -49,6 +49,7 @@ CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -79,4 +80,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index af528c22fd5..7e0682438e9 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -47,6 +47,7 @@ CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -76,4 +77,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index d1dca225bcc..f1e875ba91b 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -50,6 +50,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0xFFFC9000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -79,4 +80,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index ebb6239fa66..2e3917614c3 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -35,6 +35,7 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -63,4 +64,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index 33432d14cff..14e366358bd 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -42,6 +42,7 @@ CONFIG_DEFAULT_DEVICE_TREE="t4240rdb" CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -71,4 +72,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index a47615e12f4..dfe8953af76 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -30,6 +30,7 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -59,4 +60,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index 80353b8eb36..39469b52037 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -3,10 +3,10 @@ CONFIG_SYS_TEXT_BASE=0x1120000 CONFIG_ENV_SIZE=0x1000 CONFIG_NR_DRAM_BANKS=8 CONFIG_PRE_CON_BUF_ADDR=0x100000 +CONFIG_SPL_TEXT_BASE=0x1110000 CONFIG_X86_RUN_64BIT=y CONFIG_VENDOR_COREBOOT=y CONFIG_TARGET_COREBOOT=y -CONFIG_SPL_TEXT_BASE=0x1110000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_SHOW_BOOT_PROGRESS=y diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig index 5be02a33829..d1e9cc40177 100644 --- a/configs/imx8mq_phanbell_defconfig +++ b/configs/imx8mq_phanbell_defconfig @@ -3,9 +3,9 @@ CONFIG_SPL_SYS_ICACHE_OFF=y CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_ARCH_IMX8M=y CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 -CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_DM_GPIO=y CONFIG_TARGET_IMX8MQ_PHANBELL=y CONFIG_SPL_SERIAL_SUPPORT=y @@ -17,6 +17,7 @@ CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg" +CONFIG_SD_BOOT=y CONFIG_SPL_BOARD_INIT=y CONFIG_HUSH_PARSER=y # CONFIG_BOOTM_NETBSD is not set @@ -28,6 +29,7 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y +# CONFIG_SPL_DOS_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx8mq-phanbell" CONFIG_ENV_IS_IN_MMC=y @@ -48,5 +50,3 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RESET=y CONFIG_DM_THERMAL=y -CONFIG_SD_BOOT=y -# CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index c19c66fa684..2b0e415c6f1 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS1028AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_F_LEN=0x6000 @@ -79,4 +80,3 @@ CONFIG_WDT_SP805=y CONFIG_RSA=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index 82b08a58ecd..a7ae482d84a 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS1028AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_F_LEN=0x6000 @@ -84,4 +85,3 @@ CONFIG_WDT=y CONFIG_WDT_SP805=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig index 417f29217a0..ee257fd65e7 100644 --- a/configs/ls1028aqds_tfa_lpuart_defconfig +++ b/configs/ls1028aqds_tfa_lpuart_defconfig @@ -3,8 +3,8 @@ CONFIG_TARGET_LS1028AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_ENV_OFFSET=0x500000 +CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_NR_DRAM_BANKS=2 @@ -15,10 +15,10 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="LPUART" CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" -CONFIG_SYS_EXTRA_OPTIONS="LPUART" CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DM=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index 947c4b46132..4b61e7864d8 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS1028ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_F_LEN=0x6000 @@ -76,4 +77,3 @@ CONFIG_WDT_SP805=y CONFIG_RSA=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index ad6de6ca011..26219daeeef 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS1028ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_F_LEN=0x6000 @@ -85,4 +86,3 @@ CONFIG_WDT=y CONFIG_WDT_SP805=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index 69e3a8fbbfc..a601b11defe 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS1088AQDS=y CONFIG_SYS_TEXT_BASE=0x30100000 CONFIG_ENV_SIZE=0x20000 @@ -64,4 +65,3 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index 3a363790d9b..f6b22731140 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS1088AQDS=y CONFIG_SYS_TEXT_BASE=0x20100000 CONFIG_ENV_SIZE=0x2000 @@ -66,4 +67,3 @@ CONFIG_USB_GADGET=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index 117fdd8588e..ff3610c0a11 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS1088AQDS=y CONFIG_SYS_TEXT_BASE=0x20100000 CONFIG_ENV_SIZE=0x2000 @@ -67,4 +68,3 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_GADGET=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index eedee1e88f8..c1bb88af8c0 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS1088AQDS=y CONFIG_SYS_TEXT_BASE=0x80400000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -72,4 +73,3 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index 621c411aca6..b22eb8400a8 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS1088AQDS=y CONFIG_SYS_TEXT_BASE=0x80400000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -76,4 +77,3 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_GADGET=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index 2bb84e158cd..034ceb3c8d3 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS1088AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 @@ -84,4 +85,3 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_GADGET=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index 4c85b1148f3..efbd5f75bd8 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS2080AQDS=y CONFIG_SYS_TEXT_BASE=0x30100000 CONFIG_ENV_SIZE=0x2000 @@ -66,4 +67,3 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index 0f8e22b304f..ad53671e6c5 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS2080AQDS=y CONFIG_SYS_TEXT_BASE=0x30100000 CONFIG_ENV_SIZE=0x2000 @@ -67,4 +68,3 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 044177088c9..590ca280000 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS2080AQDS=y CONFIG_SYS_TEXT_BASE=0x80400000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -74,4 +75,3 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index c159c153da6..b8fbb43eb3b 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS2080AQDS=y CONFIG_SYS_TEXT_BASE=0x20100000 CONFIG_ENV_SIZE=0x2000 @@ -66,4 +67,3 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index ac0b635191c..d493febf4b9 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS2080AQDS=y CONFIG_SYS_TEXT_BASE=0x80400000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -73,4 +74,3 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index 94087cee01a..21739f0f9ec 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS2080ARDB=y CONFIG_SYS_TEXT_BASE=0x30100000 CONFIG_ENV_SIZE=0x2000 @@ -64,4 +65,3 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index e9dfc3603ea..dc4564b318e 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS2080ARDB=y CONFIG_SYS_TEXT_BASE=0x30100000 CONFIG_ENV_SIZE=0x2000 @@ -65,4 +66,3 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index d1086f976c6..a3fa5c6bbf2 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS2080ARDB=y CONFIG_SYS_TEXT_BASE=0x80400000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -70,4 +71,3 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig index 032cb406338..9d08eb7af77 100644 --- a/configs/ls2081ardb_defconfig +++ b/configs/ls2081ardb_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS2081ARDB=y CONFIG_SYS_TEXT_BASE=0x20100000 CONFIG_ENV_SIZE=0x2000 @@ -62,4 +63,3 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 81bc489d19a..7c7bb345e17 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS2080AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 @@ -78,4 +79,3 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index 2d71baeced7..be073b6724e 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS2080ARDB=y CONFIG_SYS_TEXT_BASE=0x20100000 CONFIG_ENV_SIZE=0x2000 @@ -63,4 +64,3 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index 85b8dac9924..d312cc96289 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS2080ARDB=y CONFIG_SYS_TEXT_BASE=0x20100000 CONFIG_ENV_SIZE=0x2000 @@ -67,4 +68,3 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index 39a69734fea..a244af17bc1 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS2080ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 @@ -80,4 +81,3 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index 34b94394c7c..2a82fda0bfa 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS2080ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 @@ -85,4 +86,3 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig index fe28f37b9eb..6b9fbd7e221 100644 --- a/configs/mt7623n_bpir2_defconfig +++ b/configs/mt7623n_bpir2_defconfig @@ -14,7 +14,6 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_DEFAULT_FDT_FILE="mt7623n-bananapi-bpi-r2" # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTMENU=y # CONFIG_CMD_ELF is not set @@ -22,13 +21,9 @@ CONFIG_CMD_BOOTMENU=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_PART=y CONFIG_CMD_READ=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y CONFIG_DEFAULT_DEVICE_TREE="mt7623n-bananapi-bpi-r2" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -57,4 +52,3 @@ CONFIG_TIMER=y CONFIG_MTK_TIMER=y CONFIG_WDT_MTK=y CONFIG_LZMA=y -CONFIG_EFI_LOADER=y diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig index 93c8db979c3..4e559edd94d 100644 --- a/configs/nanopi-m4-2gb-rk3399_defconfig +++ b/configs/nanopi-m4-2gb-rk3399_defconfig @@ -46,18 +46,16 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_USB_KEYBOARD=y -CONFIG_SPL_TINY_MEMSET=y -CONFIG_ERRNO_STR=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 5a694edc03f..1879944bc5e 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -50,18 +50,16 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_USB_KEYBOARD=y -CONFIG_SPL_TINY_MEMSET=y -CONFIG_ERRNO_STR=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index ca7aa5ab02b..84f6d403285 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -10,7 +10,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/sda2 rw rootwait earlycon=pl011,0x7ff80000 debug user_debug=31 androidboot.hardware=juno loglevel=9" -CONFIG_OF_BOARD=y # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set @@ -21,15 +20,16 @@ CONFIG_SYS_PROMPT="VExpress64# " CONFIG_CMD_MEMTEST=y CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_LOADS is not set +CONFIG_CMD_USB=y # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_CMD_CACHE=y # CONFIG_CMD_MISC is not set CONFIG_CMD_UBI=y -CONFIG_CMD_USB=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set +CONFIG_OF_BOARD=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xBFC0000 # CONFIG_MMC is not set From 8cc28146f55340777a48c44e948a8ff1143e1c17 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 26 Feb 2020 10:28:41 +0100 Subject: [PATCH 225/237] configs: migrate CONFIG_SET_DFU_ALT_INFO to defconfigs Move CONFIG_SET_DFU_ALT_INFO into Kconfig done by moveconfig.py. Signed-off-by: Patrick Delaunay Acked-by: Lukasz Majewski Reviewed-by: Jaehoon Chung --- configs/odroid-xu3_defconfig | 1 + configs/odroid_defconfig | 1 + configs/stm32mp15_basic_defconfig | 1 + configs/stm32mp15_dhcom_basic_defconfig | 1 + configs/stm32mp15_optee_defconfig | 1 + configs/stm32mp15_trusted_defconfig | 1 + drivers/dfu/Kconfig | 5 +++++ include/configs/odroid.h | 1 - include/configs/odroid_xu3.h | 1 - include/configs/stm32mp1.h | 2 -- scripts/config_whitelist.txt | 1 - 11 files changed, 11 insertions(+), 5 deletions(-) diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index 2e982e1b533..1a2183ce195 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -39,6 +39,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_ADC=y CONFIG_ADC_EXYNOS=y CONFIG_DFU_MMC=y +CONFIG_SET_DFU_ALT_INFO=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_MTD=y diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig index e4392e477ed..345cc3b9400 100644 --- a/configs/odroid_defconfig +++ b/configs/odroid_defconfig @@ -40,6 +40,7 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DFU_MMC=y +CONFIG_SET_DFU_ALT_INFO=y CONFIG_SYS_I2C_S3C24X0=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 100f174a579..d42153a9566 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -68,6 +68,7 @@ CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_MTD=y CONFIG_DFU_VIRT=y +CONFIG_SET_DFU_ALT_INFO=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 CONFIG_FASTBOOT_BUF_SIZE=0x02000000 diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index 5f3813e515c..753b88463c5 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -67,6 +67,7 @@ CONFIG_SPL_BLOCK_CACHE=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_VIRT=y +CONFIG_SET_DFU_ALT_INFO=y CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_STM32=y CONFIG_DM_I2C=y diff --git a/configs/stm32mp15_optee_defconfig b/configs/stm32mp15_optee_defconfig index 596fe190af2..53175048431 100644 --- a/configs/stm32mp15_optee_defconfig +++ b/configs/stm32mp15_optee_defconfig @@ -59,6 +59,7 @@ CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_MTD=y CONFIG_DFU_VIRT=y +CONFIG_SET_DFU_ALT_INFO=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 CONFIG_FASTBOOT_BUF_SIZE=0x02000000 diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index f9df13a6c3b..cff11333481 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -55,6 +55,7 @@ CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_MTD=y CONFIG_DFU_VIRT=y +CONFIG_SET_DFU_ALT_INFO=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 CONFIG_FASTBOOT_BUF_SIZE=0x02000000 diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig index 174fb588a6e..5d45d7d7c2d 100644 --- a/drivers/dfu/Kconfig +++ b/drivers/dfu/Kconfig @@ -81,5 +81,10 @@ config DFU_VIRT used at board level to manage specific behavior (OTP update for example). +config SET_DFU_ALT_INFO + bool "Dynamic set of DFU alternate information" + help + This option allows to call the function set_dfu_alt_info to + dynamically build dfu_alt_info in board. endif endmenu diff --git a/include/configs/odroid.h b/include/configs/odroid.h index a7e2a3d9a23..4044365328f 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -64,7 +64,6 @@ ""PARTS_BOOT" part 0 1;" \ ""PARTS_ROOT" part 0 2\0" \ -#define CONFIG_SET_DFU_ALT_INFO #define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) #define CONFIG_DFU_ALT_BOOT_EMMC \ diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 47c30543f8f..564319c2311 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -76,7 +76,6 @@ /* Enable: board/samsung/common/misc.c to use set_dfu_alt_info() */ #define CONFIG_MISC_COMMON -#define CONFIG_SET_DFU_ALT_INFO #define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) /* Set soc_rev, soc_id, board_rev, board_name, fdtfile */ diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index 2ba4fb1305a..baec6d7e6f0 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -90,8 +90,6 @@ #define CONFIG_SYS_MTDPARTS_RUNTIME #endif -#define CONFIG_SET_DFU_ALT_INFO - #ifdef CONFIG_DM_VIDEO #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_BMP_16BPP diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 19c92180609..7c18b2481ce 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1523,7 +1523,6 @@ CONFIG_SETUP_MEMORY_TAGS CONFIG_SET_BIST CONFIG_SET_BOOTARGS CONFIG_SET_DFU_ALT_BUF_LEN -CONFIG_SET_DFU_ALT_INFO CONFIG_SFIO CONFIG_SF_DATAFLASH CONFIG_SGI_IP28 From c39e19a9b07807936b8df5925757e0a512effb92 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 26 Feb 2020 10:28:42 +0100 Subject: [PATCH 226/237] configs: migrate CONFIG_SYS_MTDPARTS_RUNTIME to defconfigs Move CONFIG_SYS_MTDPARTS_RUNTIME into Kconfig done by moveconfig.py. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- configs/igep00x0_defconfig | 1 + configs/stm32mp15_basic_defconfig | 1 + configs/stm32mp15_dhcom_basic_defconfig | 1 + configs/stm32mp15_optee_defconfig | 1 + configs/stm32mp15_trusted_defconfig | 1 + drivers/mtd/Kconfig | 7 +++++++ include/configs/omap3_igep00x0.h | 2 -- include/configs/stm32mp1.h | 5 ----- scripts/config_whitelist.txt | 1 - 9 files changed, 12 insertions(+), 8 deletions(-) diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig index e273f35e840..a5c301dbdbf 100644 --- a/configs/igep00x0_defconfig +++ b/configs/igep00x0_defconfig @@ -52,6 +52,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y +CONFIG_SYS_MTDPARTS_RUNTIME=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SPL_NAND_SIMPLE=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index d42153a9566..a9b996c0a3f 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -88,6 +88,7 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y CONFIG_MTD=y CONFIG_DM_MTD=y +CONFIG_SYS_MTDPARTS_RUNTIME=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_STM32_FMC2=y CONFIG_MTD_SPI_NAND=y diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index 753b88463c5..661c0544948 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -81,6 +81,7 @@ CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y CONFIG_MTD=y +CONFIG_SYS_MTDPARTS_RUNTIME=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/stm32mp15_optee_defconfig b/configs/stm32mp15_optee_defconfig index 53175048431..9f886fb0e7d 100644 --- a/configs/stm32mp15_optee_defconfig +++ b/configs/stm32mp15_optee_defconfig @@ -79,6 +79,7 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y CONFIG_MTD=y CONFIG_DM_MTD=y +CONFIG_SYS_MTDPARTS_RUNTIME=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_STM32_FMC2=y CONFIG_MTD_SPI_NAND=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index cff11333481..a4ea8c82297 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -75,6 +75,7 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y CONFIG_MTD=y CONFIG_DM_MTD=y +CONFIG_SYS_MTDPARTS_RUNTIME=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_STM32_FMC2=y CONFIG_MTD_SPI_NAND=y diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 5e7571cf3da..348b43e653f 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -22,6 +22,13 @@ config MTD_NOR_FLASH help Enable support for parallel NOR flash. +config SYS_MTDPARTS_RUNTIME + bool "Allow MTDPARTS to be configured at runtime" + depends on MTD + help + This option allows to call the function board_mtdparts_default to + dynamically build the variables mtdids and mtdparts at runtime. + config FLASH_CFI_DRIVER bool "Enable CFI Flash driver" help diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 4ad7dc18b10..8dc30be8b72 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -71,8 +71,6 @@ #endif -#define CONFIG_SYS_MTDPARTS_RUNTIME - /* OneNAND config */ #define CONFIG_USE_ONENAND_BOARD_INIT #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index baec6d7e6f0..ae9631ebccd 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -85,11 +85,6 @@ #define CONFIG_SYS_AUTOLOAD "no" #endif -/* Dynamic MTD partition support */ -#if defined(CONFIG_STM32_QSPI) || defined(CONFIG_NAND_STM32_FMC2) -#define CONFIG_SYS_MTDPARTS_RUNTIME -#endif - #ifdef CONFIG_DM_VIDEO #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_BMP_16BPP diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 7c18b2481ce..2678626b59d 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3191,7 +3191,6 @@ CONFIG_SYS_MRAM_SIZE CONFIG_SYS_MSC0_VAL CONFIG_SYS_MSC1_VAL CONFIG_SYS_MSC2_VAL -CONFIG_SYS_MTDPARTS_RUNTIME CONFIG_SYS_MX5_CLK32 CONFIG_SYS_MX5_HCLK CONFIG_SYS_MX6_CLK32 From e519f03a18464c1fe249bd7fcf7829fad31abc9a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 4 May 2020 13:54:40 +0200 Subject: [PATCH 227/237] cmd: mem: Remove CONFIG_SYS_MEMTEST_SCRATCH mapping There is no real need to exactly define space for saving patterns for alternate memory test. It is much easier to allocate space on the stack and use it instead of trying to find out space where pattern should be saved. For example if you want to test the whole DDR memory you can't save patter to DDR and you need to find it out. On Xilinx devices DDR or OCM addresses were chosen but that means that OCM needs to be mapped and U-Boot has access permission there. It is easier to remove this limitation and simply save it on stack because it is very clear that memory test can't rewrite U-Boot and U-Boot has also full access to memory where runs from. Signed-off-by: Michal Simek Reviewed-by: Simon Glass Reviewed-by: Stefan Roese Reviewed-by: Heiko Schocher --- README | 4 ---- cmd/mem.c | 9 ++------- include/configs/MigoR.h | 1 - include/configs/advantech_dms-ba16.h | 1 - include/configs/apalis_imx6.h | 1 - include/configs/aristainetos2.h | 1 - include/configs/armadillo-800eva.h | 1 - include/configs/blanche.h | 1 - include/configs/cgtqmx6eval.h | 1 - include/configs/colibri_imx6.h | 1 - include/configs/dh_imx6.h | 1 - include/configs/el6x_common.h | 1 - include/configs/embestmx6boards.h | 1 - include/configs/ge_bx50v3.h | 1 - include/configs/gw_ventana.h | 1 - include/configs/imx6_logic.h | 1 - include/configs/kzm9g.h | 1 - include/configs/mx6sabre_common.h | 1 - include/configs/nitrogen6x.h | 1 - include/configs/presidio_asic.h | 1 - include/configs/sh7752evb.h | 1 - include/configs/sh7753evb.h | 1 - include/configs/sh7757lcr.h | 1 - include/configs/stm32mp1.h | 1 - include/configs/tao3530.h | 1 - include/configs/tricorder.h | 1 - include/configs/xilinx_versal.h | 1 - include/configs/xilinx_versal_mini.h | 1 - include/configs/xilinx_zynqmp.h | 4 ---- include/configs/xilinx_zynqmp_mini.h | 1 - include/configs/xilinx_zynqmp_r5.h | 1 - scripts/config_whitelist.txt | 1 - 32 files changed, 2 insertions(+), 44 deletions(-) diff --git a/README b/README index 2e8ad3bc0cb..eb7892d4c15 100644 --- a/README +++ b/README @@ -2477,10 +2477,6 @@ Configuration Settings: Begin and End addresses of the area used by the simple memory test. -- CONFIG_SYS_MEMTEST_SCRATCH: - Scratch address used by the alternate memory test - You only need to set this if address zero isn't writeable - - CONFIG_SYS_MEM_RESERVE_SECURE Only implemented for ARMv8 for now. If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory diff --git a/cmd/mem.c b/cmd/mem.c index 009b7b58f32..18f0510098b 100644 --- a/cmd/mem.c +++ b/cmd/mem.c @@ -25,10 +25,6 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_SYS_MEMTEST_SCRATCH -#define CONFIG_SYS_MEMTEST_SCRATCH 0 -#endif - static int mod_mem(cmd_tbl_t *, int, int, int, char * const []); /* Display values from last command. @@ -922,7 +918,8 @@ static int do_mem_mtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong start, end; - vu_long *buf, *dummy; + vu_long scratch_space; + vu_long *buf, *dummy = &scratch_space; ulong iteration_limit = 0; ulong count = 0; ulong errs = 0; /* number of errors, or -1 if interrupted */ @@ -958,7 +955,6 @@ static int do_mem_mtest(cmd_tbl_t *cmdtp, int flag, int argc, start, end); buf = map_sysmem(start, end - start); - dummy = map_sysmem(CONFIG_SYS_MEMTEST_SCRATCH, sizeof(vu_long)); for (iteration = 0; !iteration_limit || iteration < iteration_limit; iteration++) { @@ -988,7 +984,6 @@ static int do_mem_mtest(cmd_tbl_t *cmdtp, int flag, int argc, } unmap_sysmem((void *)buf); - unmap_sysmem((void *)dummy); if (errs == -1UL) { /* Memory test was aborted - write a newline to finish off */ diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h index c58b7814ba9..2421300e1e1 100644 --- a/include/configs/MigoR.h +++ b/include/configs/MigoR.h @@ -32,7 +32,6 @@ /* Enable alternate, more extensive, memory test */ /* Scratch address used by the alternate memory test */ -#undef CONFIG_SYS_MEMTEST_SCRATCH /* Enable temporary baudrate change while serial download */ #undef CONFIG_SYS_LOADS_BAUD_CHANGE diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h index deb4374d1c4..b7b1ac2f89b 100644 --- a/include/configs/advantech_dms-ba16.h +++ b/include/configs/advantech_dms-ba16.h @@ -185,7 +185,6 @@ #define CONFIG_SYS_MEMTEST_START 0x10000000 #define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index fb0037444f4..49a28f5a3f5 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -212,7 +212,6 @@ #define CONFIG_SYS_MEMTEST_START 0x10000000 #define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 5f4a4f854f9..336cf1746ab 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -409,7 +409,6 @@ #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index e56929628bc..c089b9c27c6 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -43,7 +43,6 @@ #define CONFIG_SYS_MEMTEST_START (ARMADILLO_800EVA_SDRAM_BASE) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 504 * 1024 * 1024) -#undef CONFIG_SYS_MEMTEST_SCRATCH #undef CONFIG_SYS_LOADS_BAUD_CHANGE #define CONFIG_SYS_SDRAM_BASE (ARMADILLO_800EVA_SDRAM_BASE) diff --git a/include/configs/blanche.h b/include/configs/blanche.h index 7ee38a7ef9b..fd29c5d0f1e 100644 --- a/include/configs/blanche.h +++ b/include/configs/blanche.h @@ -22,7 +22,6 @@ #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) -#undef CONFIG_SYS_MEMTEST_SCRATCH #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* FLASH */ diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 797fcb14590..b6dfcdd08b9 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -189,7 +189,6 @@ #define CONFIG_SYS_MEMTEST_START 0x10000000 #define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 4cdd3c53afb..706665e37fc 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -191,7 +191,6 @@ #define CONFIG_SYS_MEMTEST_START 0x10000000 #define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 087d020cdd3..e16c9ee01d9 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -139,7 +139,6 @@ #define CONFIG_SYS_MEMTEST_START 0x10000000 #define CONFIG_SYS_MEMTEST_END 0x20000000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 /* Environment */ diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index 95c04c37970..bd42ad259d9 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -76,7 +76,6 @@ #define CONFIG_SYS_MEMTEST_START 0x10000000 #define CONFIG_SYS_MEMTEST_END 0x10800000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 62561116bbe..bf51afbd9cd 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_MEMTEST_START 0x10000000 #define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 3bf0cd518c1..2b55f51b8ba 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -146,7 +146,6 @@ #define CONFIG_SYS_MEMTEST_START 0x10000000 #define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index d169aa19de4..193c88e3da0 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -133,7 +133,6 @@ /* Memory configuration */ #define CONFIG_SYS_MEMTEST_START 0x10000000 #define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 2274db0e229..e77fb4a1b5e 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -118,7 +118,6 @@ #define CONFIG_SYS_MEMTEST_START 0x10000000 #define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index cceabdf6636..9ceb12f7e00 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -38,7 +38,6 @@ #define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE) #define CONFIG_SYS_MEMTEST_END \ (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) -#undef CONFIG_SYS_MEMTEST_SCRATCH #undef CONFIG_SYS_LOADS_BAUD_CHANGE #define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */ diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index ee3b754910c..b46367c8314 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -156,7 +156,6 @@ #define CONFIG_SYS_MEMTEST_START 0x10000000 #define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 9ef6ea90a3f..5e09a783df2 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -132,7 +132,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_MEMTEST_START 0x10000000 #define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h index 023092e486d..56f009ad4e3 100644 --- a/include/configs/presidio_asic.h +++ b/include/configs/presidio_asic.h @@ -27,7 +27,6 @@ #define GICD_BASE 0xf7011000 #define GICC_BASE 0xf7012000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x00100000 #define CONFIG_SYS_MEMTEST_START 0x05000000 #define CONFIG_SYS_MEMTEST_END 0x0D000000 diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h index c45b33a91a9..ff49b9c2171 100644 --- a/include/configs/sh7752evb.h +++ b/include/configs/sh7752evb.h @@ -25,7 +25,6 @@ #define CONFIG_SYS_MEMTEST_START (SH7752EVB_SDRAM_BASE) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 480 * 1024 * 1024) -#undef CONFIG_SYS_MEMTEST_SCRATCH #undef CONFIG_SYS_LOADS_BAUD_CHANGE #define CONFIG_SYS_SDRAM_BASE (SH7752EVB_SDRAM_BASE) diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h index 70e7fb93248..74fb528d2e9 100644 --- a/include/configs/sh7753evb.h +++ b/include/configs/sh7753evb.h @@ -25,7 +25,6 @@ #define CONFIG_SYS_MEMTEST_START (SH7753EVB_SDRAM_BASE) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 480 * 1024 * 1024) -#undef CONFIG_SYS_MEMTEST_SCRATCH #undef CONFIG_SYS_LOADS_BAUD_CHANGE #define CONFIG_SYS_SDRAM_BASE (SH7753EVB_SDRAM_BASE) diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h index 6a34dc7954b..8f5c84207fe 100644 --- a/include/configs/sh7757lcr.h +++ b/include/configs/sh7757lcr.h @@ -28,7 +28,6 @@ #define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 224 * 1024 * 1024) -#undef CONFIG_SYS_MEMTEST_SCRATCH #undef CONFIG_SYS_LOADS_BAUD_CHANGE #define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE) diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index ae9631ebccd..cf04662328f 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -68,7 +68,6 @@ #define CONFIG_SYS_MEMTEST_START STM32_DDR_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_64M) -#define CONFIG_SYS_MEMTEST_SCRATCH (CONFIG_SYS_MEMTEST_END + 4) /*MMC SD*/ #define CONFIG_SYS_MMC_MAX_DEVICE 3 diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index e95cd0087d3..c80776b4da0 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -134,7 +134,6 @@ #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ /* defaults */ #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ -#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ /* load address */ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 1e4459747d5..de6abb58377 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -248,5 +248,4 @@ #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 #endif /* __CONFIG_H */ diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 0c259a181f1..480afd993bc 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -18,7 +18,6 @@ #define GICD_BASE 0xF9000000 #define GICR_BASE 0xF9080000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000 #define CONFIG_SYS_MEMTEST_START 0 #define CONFIG_SYS_MEMTEST_END 1000 diff --git a/include/configs/xilinx_versal_mini.h b/include/configs/xilinx_versal_mini.h index ee305e0226b..ae7eca11553 100644 --- a/include/configs/xilinx_versal_mini.h +++ b/include/configs/xilinx_versal_mini.h @@ -10,7 +10,6 @@ #ifndef __CONFIG_VERSAL_MINI_H #define __CONFIG_VERSAL_MINI_H -#define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000 #define CONFIG_EXTRA_ENV_SETTINGS diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index eddc2b40200..01e05200dfe 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -19,10 +19,6 @@ #define GICD_BASE 0xF9010000 #define GICC_BASE 0xF9020000 -#ifndef CONFIG_SYS_MEMTEST_SCRATCH -# define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 -#endif - #define CONFIG_SYS_MEMTEST_START 0 #define CONFIG_SYS_MEMTEST_END 1000 diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h index a6922896e0e..3078b9c55b5 100644 --- a/include/configs/xilinx_zynqmp_mini.h +++ b/include/configs/xilinx_zynqmp_mini.h @@ -10,7 +10,6 @@ #ifndef __CONFIG_ZYNQMP_MINI_H #define __CONFIG_ZYNQMP_MINI_H -#define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000 #define CONFIG_EXTRA_ENV_SETTINGS diff --git a/include/configs/xilinx_zynqmp_r5.h b/include/configs/xilinx_zynqmp_r5.h index 155d7fe883f..327f0af3145 100644 --- a/include/configs/xilinx_zynqmp_r5.h +++ b/include/configs/xilinx_zynqmp_r5.h @@ -40,6 +40,5 @@ /* 0x0 - 0x40 is used for placing exception vectors */ #define CONFIG_SYS_MEMTEST_START 0x40 #define CONFIG_SYS_MEMTEST_END 0x100 -#define CONFIG_SYS_MEMTEST_SCRATCH 0 #endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 2678626b59d..cb401d3bec1 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3076,7 +3076,6 @@ CONFIG_SYS_MEMAC_LITTLE_ENDIAN CONFIG_SYS_MEMORY_BASE CONFIG_SYS_MEMORY_SIZE CONFIG_SYS_MEMTEST_END -CONFIG_SYS_MEMTEST_SCRATCH CONFIG_SYS_MEMTEST_START CONFIG_SYS_MEM_MAP CONFIG_SYS_MEM_RESERVE_SECURE From 475d89d94db1aa2a1e65ed440bdedeb6c3e61cad Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 4 May 2020 15:26:19 +0200 Subject: [PATCH 228/237] treewide: mem: Remove alternate memtest setup from Mox and x530 The commit e89f8aae3d67 ("treewide: Migrate CONFIG_SYS_ALT_MEMTEST to Kconfig") setup correct dependency on MEMTEST that's why there is no reason to enable enable alternate memtest without mtest command. Signed-off-by: Michal Simek --- include/configs/turris_mox.h | 2 -- include/configs/x530.h | 2 -- 2 files changed, 4 deletions(-) diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h index e414f90fe1e..49bd6b53d2e 100644 --- a/include/configs/turris_mox.h +++ b/include/configs/turris_mox.h @@ -50,8 +50,6 @@ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_ALT_MEMTEST - /* End of 16M scrubbed by training in bootrom */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000) diff --git a/include/configs/x530.h b/include/configs/x530.h index 290e13de007..9081f416605 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -83,8 +83,6 @@ */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ -#define CONFIG_SYS_ALT_MEMTEST - /* Keep device tree and initrd in low memory so the kernel can access them */ #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ From a389c9cd9363fb31007bcf76a889f2a42c510b7f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 4 May 2020 15:26:20 +0200 Subject: [PATCH 229/237] treewide: mem: Enable MEMTEST via defconfig There is no reason to enable MEMTEST from headers when was converted to Kconfig already. Signed-off-by: Michal Simek --- configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1012afrwy_qspi_defconfig | 1 + configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1012afrwy_tfa_defconfig | 1 + configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1028aqds_tfa_defconfig | 1 + configs/ls1028aqds_tfa_lpuart_defconfig | 1 + configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1028ardb_tfa_defconfig | 1 + include/configs/ls1012afrwy.h | 2 -- include/configs/ls1028a_common.h | 1 - 11 files changed, 9 insertions(+), 3 deletions(-) diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index addb31c1959..3dc3f9e77d1 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -20,6 +20,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index 2156f5eb971..61302697063 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -21,6 +21,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index a4fdd0c02ff..9f2c7ddb0ae 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -20,6 +20,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index 280dbd3b47c..ca0575e41b7 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -21,6 +21,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index 2b0e415c6f1..d2c6fbf03c5 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -20,6 +20,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index a7ae482d84a..23d1b28e51a 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -21,6 +21,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig index ee257fd65e7..e3aa3d3cfb8 100644 --- a/configs/ls1028aqds_tfa_lpuart_defconfig +++ b/configs/ls1028aqds_tfa_lpuart_defconfig @@ -21,6 +21,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index 4b61e7864d8..6fa7f8364a1 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -19,6 +19,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 26219daeeef..98ff99737a9 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -20,6 +20,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index 4d4c1a04f29..9e330582838 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -22,7 +22,6 @@ #define SYS_SDRAM_SIZE_1024 0x40000000 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_CMD_MEMINFO -#define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff @@ -121,7 +120,6 @@ "env exists secureboot && esbc_halt;" #endif #define CONFIG_CMD_MEMINFO -#define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 6905694d102..32065c2925f 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -26,7 +26,6 @@ #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 -#define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff From 702de89cc6a34c1c23dd3d987b0472b2cecdb63c Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Mon, 4 May 2020 15:26:21 +0200 Subject: [PATCH 230/237] treewide: mem: Move mtest related defines to Kconfig Move below defines which are used by mtest utility to Kconfig. CONFIG_SYS_MEMTEST_START CONFIG_SYS_MEMTEST_END Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek [trini: Fix kmcoge5ne board, re-run migration as well] Signed-off-by: Tom Rini --- README | 4 ---- board/keymile/km83xx/km83xx.c | 8 ++++++-- cmd/Kconfig | 16 ++++++++++++++++ configs/T1023RDB_NAND_defconfig | 2 ++ configs/T1023RDB_SDCARD_defconfig | 2 ++ configs/T1023RDB_SECURE_BOOT_defconfig | 2 ++ configs/T1023RDB_SPIFLASH_defconfig | 2 ++ configs/T1023RDB_defconfig | 2 ++ configs/T1024RDB_NAND_defconfig | 2 ++ configs/T1024RDB_SDCARD_defconfig | 2 ++ configs/T1024RDB_SECURE_BOOT_defconfig | 2 ++ configs/T1024RDB_SPIFLASH_defconfig | 2 ++ configs/T1024RDB_defconfig | 2 ++ configs/T2080RDB_NAND_defconfig | 2 ++ configs/T2080RDB_SDCARD_defconfig | 2 ++ configs/T2080RDB_SECURE_BOOT_defconfig | 2 ++ configs/T2080RDB_SPIFLASH_defconfig | 2 ++ configs/T2080RDB_SRIO_PCIE_BOOT_defconfig | 2 ++ configs/T2080RDB_defconfig | 2 ++ configs/ap121_defconfig | 2 ++ configs/ap143_defconfig | 2 ++ configs/ap152_defconfig | 2 ++ configs/apalis-imx8qm_defconfig | 2 ++ configs/apalis_imx6_defconfig | 2 ++ ...razedev_cc_v1_0_ultrazedev_som_v1_0_defconfig | 2 ++ configs/bk4r1_defconfig | 2 ++ configs/boston32r2_defconfig | 2 ++ configs/boston32r2el_defconfig | 2 ++ configs/boston32r6_defconfig | 2 ++ configs/boston32r6el_defconfig | 2 ++ configs/boston64r2_defconfig | 2 ++ configs/boston64r2el_defconfig | 2 ++ configs/boston64r6_defconfig | 2 ++ configs/boston64r6el_defconfig | 2 ++ configs/colibri-imx6ull_defconfig | 2 ++ configs/colibri-imx8qxp_defconfig | 2 ++ configs/colibri_imx6_defconfig | 2 ++ configs/colibri_imx7_defconfig | 2 ++ configs/colibri_imx7_emmc_defconfig | 2 ++ configs/colibri_vf_defconfig | 2 ++ configs/crs305-1g-4s_defconfig | 2 ++ configs/db-xc3-24g4xg_defconfig | 2 ++ configs/dh_imx6_defconfig | 2 ++ configs/gazerbeam_defconfig | 2 ++ configs/imx6dl_icore_nand_defconfig | 2 ++ configs/imx6dl_mamoj_defconfig | 2 ++ configs/imx6q_icore_nand_defconfig | 2 ++ configs/imx6q_logic_defconfig | 2 ++ configs/imx6qdl_icore_mipi_defconfig | 2 ++ configs/imx6qdl_icore_mmc_defconfig | 2 ++ configs/imx6qdl_icore_nand_defconfig | 2 ++ configs/imx6qdl_icore_rqs_defconfig | 2 ++ configs/imx6ul_geam_mmc_defconfig | 2 ++ configs/imx6ul_geam_nand_defconfig | 2 ++ configs/imx6ul_isiot_emmc_defconfig | 2 ++ configs/imx6ul_isiot_nand_defconfig | 2 ++ configs/liteboard_defconfig | 2 ++ configs/ls1012a2g5rdb_qspi_defconfig | 2 ++ configs/ls1012a2g5rdb_tfa_defconfig | 2 ++ configs/ls1012afrdm_qspi_defconfig | 2 ++ configs/ls1012afrdm_tfa_defconfig | 2 ++ configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1012afrwy_qspi_defconfig | 2 ++ configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1012afrwy_tfa_defconfig | 2 ++ configs/ls1012aqds_qspi_defconfig | 2 ++ configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1012aqds_tfa_defconfig | 2 ++ configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1012ardb_qspi_defconfig | 2 ++ configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1012ardb_tfa_defconfig | 2 ++ configs/ls1021aqds_ddr4_nor_defconfig | 2 ++ configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 2 ++ configs/ls1021aqds_nand_defconfig | 2 ++ configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 2 ++ configs/ls1021aqds_nor_defconfig | 2 ++ configs/ls1021aqds_nor_lpuart_defconfig | 2 ++ configs/ls1021aqds_qspi_defconfig | 2 ++ configs/ls1021aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1021aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 2 ++ configs/ls1021atwr_nor_defconfig | 2 ++ configs/ls1021atwr_nor_lpuart_defconfig | 2 ++ configs/ls1021atwr_qspi_defconfig | 2 ++ .../ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 ++ configs/ls1021atwr_sdcard_ifc_defconfig | 2 ++ configs/ls1021atwr_sdcard_qspi_defconfig | 2 ++ configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1028aqds_tfa_defconfig | 2 ++ configs/ls1028aqds_tfa_lpuart_defconfig | 2 ++ configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1028ardb_tfa_defconfig | 2 ++ configs/ls1043aqds_defconfig | 2 ++ configs/ls1043aqds_lpuart_defconfig | 2 ++ configs/ls1043aqds_nand_defconfig | 2 ++ configs/ls1043aqds_nor_ddr3_defconfig | 2 ++ configs/ls1043aqds_qspi_defconfig | 2 ++ configs/ls1043aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1043aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1043aqds_tfa_defconfig | 2 ++ configs/ls1046aqds_SECURE_BOOT_defconfig | 2 ++ configs/ls1046aqds_defconfig | 2 ++ configs/ls1046aqds_lpuart_defconfig | 2 ++ configs/ls1046aqds_nand_defconfig | 2 ++ configs/ls1046aqds_qspi_defconfig | 2 ++ configs/ls1046aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1046aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1046aqds_tfa_defconfig | 2 ++ configs/ls1088aqds_defconfig | 2 ++ configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1088aqds_qspi_defconfig | 2 ++ configs/ls1088aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1088aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1088aqds_tfa_defconfig | 2 ++ configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1088ardb_qspi_defconfig | 2 ++ .../ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1088ardb_sdcard_qspi_defconfig | 2 ++ configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1088ardb_tfa_defconfig | 2 ++ configs/meerkat96_defconfig | 2 ++ configs/mscc_jr2_defconfig | 2 ++ configs/mscc_luton_defconfig | 2 ++ configs/mscc_ocelot_defconfig | 2 ++ configs/mscc_serval_defconfig | 2 ++ configs/mscc_servalt_defconfig | 2 ++ configs/mx6memcal_defconfig | 2 ++ configs/mx6qsabrelite_defconfig | 2 ++ configs/mx6sllevk_defconfig | 2 ++ configs/mx6sllevk_plugin_defconfig | 2 ++ configs/mx6ul_14x14_evk_defconfig | 2 ++ configs/mx6ul_9x9_evk_defconfig | 2 ++ configs/mx6ull_14x14_evk_defconfig | 2 ++ configs/mx6ull_14x14_evk_plugin_defconfig | 2 ++ configs/mx6ulz_14x14_evk_defconfig | 2 ++ configs/mx7dsabresd_defconfig | 2 ++ configs/mx7dsabresd_qspi_defconfig | 2 ++ configs/mx7ulp_evk_defconfig | 2 ++ configs/mx7ulp_evk_plugin_defconfig | 2 ++ configs/nitrogen6dl2g_defconfig | 2 ++ configs/nitrogen6dl_defconfig | 2 ++ configs/nitrogen6q2g_defconfig | 2 ++ configs/nitrogen6q_defconfig | 2 ++ configs/nitrogen6s1g_defconfig | 2 ++ configs/nitrogen6s_defconfig | 2 ++ configs/pcm052_defconfig | 2 ++ configs/phycore_pcl063_defconfig | 2 ++ configs/pic32mzdask_defconfig | 2 ++ configs/pico-dwarf-imx6ul_defconfig | 2 ++ configs/pico-hobbit-imx6ul_defconfig | 2 ++ configs/pico-imx6ul_defconfig | 2 ++ configs/pico-imx7d_bl33_defconfig | 2 ++ configs/pico-pi-imx6ul_defconfig | 2 ++ configs/s32v234evb_defconfig | 2 ++ configs/sandbox64_defconfig | 2 ++ configs/sandbox_defconfig | 2 ++ configs/sandbox_flattree_defconfig | 2 ++ configs/sandbox_spl_defconfig | 2 ++ configs/sansa_fuze_plus_defconfig | 2 ++ configs/socfpga_agilex_defconfig | 2 ++ configs/socfpga_sr1500_defconfig | 2 ++ configs/socfpga_stratix10_defconfig | 2 ++ configs/somlabs_visionsom_6ull_defconfig | 2 ++ configs/stm32mp15_basic_defconfig | 2 ++ configs/stm32mp15_dhcom_basic_defconfig | 2 ++ configs/stm32mp15_optee_defconfig | 2 ++ configs/stm32mp15_trusted_defconfig | 2 ++ configs/strider_con_defconfig | 2 ++ configs/strider_con_dp_defconfig | 2 ++ configs/strider_cpu_defconfig | 2 ++ configs/strider_cpu_dp_defconfig | 2 ++ configs/stv0991_defconfig | 2 ++ configs/tbs2910_defconfig | 2 ++ configs/topic_miami_defconfig | 2 ++ configs/topic_miamilite_defconfig | 2 ++ configs/topic_miamiplus_defconfig | 2 ++ configs/tplink_wdr4300_defconfig | 2 ++ configs/turris_omnia_defconfig | 2 ++ configs/usbarmory_defconfig | 2 ++ configs/verdin-imx8mm_defconfig | 2 ++ configs/vexpress_aemv8a_juno_defconfig | 2 ++ configs/vexpress_aemv8a_semi_defconfig | 2 ++ configs/vf610twr_defconfig | 2 ++ configs/vf610twr_nand_defconfig | 2 ++ configs/warp7_bl33_defconfig | 2 ++ configs/warp7_defconfig | 2 ++ configs/wb45n_defconfig | 2 ++ configs/wb50n_defconfig | 2 ++ configs/xilinx_versal_mini_defconfig | 2 ++ configs/xilinx_versal_virt_defconfig | 2 ++ configs/xilinx_zynq_virt_defconfig | 2 ++ configs/xilinx_zynqmp_mini_defconfig | 2 ++ configs/xilinx_zynqmp_virt_defconfig | 2 ++ configs/xpress_defconfig | 2 ++ configs/xpress_spl_defconfig | 2 ++ configs/zc5202_defconfig | 2 ++ configs/zc5601_defconfig | 2 ++ doc/feature-removal-schedule.txt | 12 ------------ include/configs/10m50_devboard.h | 5 ----- include/configs/3c120_devboard.h | 5 ----- include/configs/B4860QDS.h | 2 -- include/configs/BSC9131RDB.h | 3 --- include/configs/BSC9132QDS.h | 3 --- include/configs/C29XPCIE.h | 3 --- include/configs/M5208EVBE.h | 3 --- include/configs/M52277EVB.h | 3 --- include/configs/M5235EVB.h | 3 --- include/configs/M5249EVB.h | 3 --- include/configs/M5253DEMO.h | 3 --- include/configs/M5272C3.h | 2 -- include/configs/M5275EVB.h | 2 -- include/configs/M5282EVB.h | 3 --- include/configs/M53017EVB.h | 3 --- include/configs/M5329EVB.h | 3 --- include/configs/M5373EVB.h | 3 --- include/configs/M54418TWR.h | 2 -- include/configs/M54451EVB.h | 3 --- include/configs/M54455EVB.h | 3 --- include/configs/M5475EVB.h | 3 --- include/configs/M5485EVB.h | 3 --- include/configs/MCR3000.h | 3 --- include/configs/MPC8308RDB.h | 2 -- include/configs/MPC8313ERDB_NAND.h | 3 --- include/configs/MPC8313ERDB_NOR.h | 3 --- include/configs/MPC8315ERDB.h | 2 -- include/configs/MPC8323ERDB.h | 2 -- include/configs/MPC832XEMDS.h | 2 -- include/configs/MPC8349EMDS.h | 2 -- include/configs/MPC8349EMDS_SDRAM.h | 2 -- include/configs/MPC8349ITX.h | 2 -- include/configs/MPC837XEMDS.h | 2 -- include/configs/MPC837XERDB.h | 2 -- include/configs/MPC8536DS.h | 3 --- include/configs/MPC8540ADS.h | 3 --- include/configs/MPC8541CDS.h | 3 --- include/configs/MPC8544DS.h | 3 --- include/configs/MPC8548CDS.h | 3 --- include/configs/MPC8555CDS.h | 3 --- include/configs/MPC8560ADS.h | 3 --- include/configs/MPC8568MDS.h | 3 --- include/configs/MPC8569MDS.h | 3 --- include/configs/MPC8572DS.h | 3 --- include/configs/MPC8610HPCD.h | 3 --- include/configs/MPC8641HPCN.h | 3 --- include/configs/MigoR.h | 3 --- include/configs/P1010RDB.h | 3 --- include/configs/P1022DS.h | 3 --- include/configs/P1023RDB.h | 3 --- include/configs/P2041RDB.h | 2 -- include/configs/SBx81LIFKW.h | 2 -- include/configs/SBx81LIFXCAT.h | 2 -- include/configs/T102xQDS.h | 3 --- include/configs/T102xRDB.h | 3 --- include/configs/T1040QDS.h | 3 --- include/configs/T104xRDB.h | 3 --- include/configs/T208xRDB.h | 3 --- include/configs/T4240RDB.h | 3 --- include/configs/TQM834x.h | 2 -- include/configs/UCP1020.h | 3 --- include/configs/adp-ae3xx.h | 2 -- include/configs/adp-ag101p.h | 2 -- include/configs/advantech_dms-ba16.h | 3 --- include/configs/am3517_crane.h | 3 --- include/configs/am3517_evm.h | 3 --- include/configs/amcore.h | 3 --- include/configs/ap121.h | 2 -- include/configs/ap143.h | 2 -- include/configs/ap152.h | 2 -- include/configs/apalis-imx8.h | 3 --- include/configs/apalis_imx6.h | 3 --- include/configs/apf27.h | 2 -- include/configs/aristainetos2.h | 3 --- include/configs/armadillo-800eva.h | 3 --- include/configs/astro_mcf5373l.h | 3 --- include/configs/at91rm9200ek.h | 4 ---- include/configs/at91sam9260ek.h | 3 --- include/configs/at91sam9261ek.h | 3 --- include/configs/at91sam9263ek.h | 3 --- include/configs/at91sam9m10g45ek.h | 3 --- include/configs/at91sam9n12ek.h | 3 --- include/configs/at91sam9rlek.h | 3 --- include/configs/at91sam9x5ek.h | 3 --- include/configs/ax25-ae350.h | 2 -- include/configs/bk4r1.h | 3 --- include/configs/boston.h | 3 --- include/configs/brppt2.h | 2 -- include/configs/caddy2.h | 2 -- include/configs/capricorn-common.h | 4 ---- include/configs/cgtqmx6eval.h | 3 --- include/configs/ci20.h | 2 -- include/configs/cl-som-imx7.h | 3 --- include/configs/cm_fx6.h | 2 -- include/configs/cm_t35.h | 3 --- include/configs/cobra5272.h | 3 --- include/configs/colibri-imx6ull.h | 3 --- include/configs/colibri-imx8x.h | 3 --- include/configs/colibri_imx6.h | 3 --- include/configs/colibri_imx7.h | 3 --- include/configs/colibri_pxa270.h | 3 --- include/configs/colibri_vf.h | 3 --- include/configs/controlcenterd.h | 3 --- include/configs/corenet_ds.h | 2 -- include/configs/cyrus.h | 2 -- include/configs/da850evm.h | 2 -- include/configs/dart_6ul.h | 2 -- include/configs/db-88f6281-bp.h | 2 -- include/configs/devkit3250.h | 2 -- include/configs/devkit8000.h | 3 --- include/configs/dh_imx6.h | 3 --- include/configs/eb_cpu5282.h | 2 -- include/configs/edison.h | 3 --- include/configs/edminiv2.h | 2 -- include/configs/el6x_common.h | 3 --- include/configs/embestmx6boards.h | 3 --- include/configs/ethernut5.h | 3 --- include/configs/evb_ast2500.h | 3 --- include/configs/exynos5-common.h | 2 -- include/configs/flea3.h | 3 --- include/configs/gardena-smart-gateway-mt7688.h | 2 -- include/configs/gazerbeam.h | 2 -- include/configs/ge_bx50v3.h | 3 --- include/configs/gw_ventana.h | 2 -- include/configs/highbank.h | 2 -- include/configs/hrcon.h | 2 -- include/configs/ids8313.h | 3 --- include/configs/imx27lite-common.h | 2 -- include/configs/imx6-engicam.h | 2 -- include/configs/imx6_logic.h | 3 --- include/configs/imx6dl-mamoj.h | 2 -- include/configs/imx8mm_evk.h | 3 --- include/configs/imx8mn_evk.h | 3 --- include/configs/imx8mp_evk.h | 4 ---- include/configs/imx8mq_evk.h | 4 ---- include/configs/imx8qm_rom7720.h | 3 --- include/configs/integrator-common.h | 2 -- include/configs/km/km-powerpc.h | 4 ---- include/configs/km/km_arm.h | 2 -- include/configs/kmcoge5ne.h | 2 +- include/configs/kzm9g.h | 3 --- include/configs/legoev3.h | 2 -- include/configs/linkit-smart-7688.h | 2 -- include/configs/liteboard.h | 2 -- include/configs/ls1012a2g5rdb.h | 4 ---- include/configs/ls1012afrdm.h | 4 ---- include/configs/ls1012afrwy.h | 4 ---- include/configs/ls1012aqds.h | 4 ---- include/configs/ls1012ardb.h | 4 ---- include/configs/ls1021aqds.h | 3 --- include/configs/ls1021atwr.h | 3 --- include/configs/ls1028a_common.h | 3 --- include/configs/ls1043aqds.h | 3 --- include/configs/ls1046aqds.h | 3 --- include/configs/ls1088aqds.h | 2 -- include/configs/ls1088ardb.h | 2 -- include/configs/m53menlo.h | 2 -- include/configs/malta.h | 2 -- include/configs/mccmon6.h | 3 --- include/configs/meerkat96.h | 3 --- include/configs/meesc.h | 2 -- include/configs/microchip_mpfs_icicle.h | 2 -- include/configs/mpc8308_p1m.h | 2 -- include/configs/mv-common.h | 2 -- include/configs/mvebu_armada-37xx.h | 2 -- include/configs/mvebu_armada-8k.h | 2 -- include/configs/mx25pdk.h | 2 -- include/configs/mx31pdk.h | 2 -- include/configs/mx35pdk.h | 3 --- include/configs/mx51evk.h | 3 --- include/configs/mx53ard.h | 3 --- include/configs/mx53cx9020.h | 3 --- include/configs/mx53evk.h | 3 --- include/configs/mx53loco.h | 3 --- include/configs/mx53ppd.h | 3 --- include/configs/mx53smd.h | 3 --- include/configs/mx6memcal.h | 2 -- include/configs/mx6qarm2.h | 2 -- include/configs/mx6sabre_common.h | 3 --- include/configs/mx6slevk.h | 2 -- include/configs/mx6sllevk.h | 2 -- include/configs/mx6sxsabreauto.h | 2 -- include/configs/mx6sxsabresd.h | 2 -- include/configs/mx6ul_14x14_evk.h | 2 -- include/configs/mx6ullevk.h | 2 -- include/configs/mx7dsabresd.h | 3 --- include/configs/mx7ulp_com.h | 3 --- include/configs/mx7ulp_evk.h | 3 --- include/configs/mxs.h | 2 -- include/configs/nitrogen6x.h | 2 -- include/configs/nokia_rx51.h | 3 --- include/configs/novena.h | 3 --- include/configs/odroid.h | 2 -- include/configs/omap3_logic.h | 3 --- include/configs/omap3_overo.h | 3 --- include/configs/omap3_pandora.h | 3 --- include/configs/omap3_zoom1.h | 3 --- include/configs/omapl138_lcdk.h | 2 -- include/configs/origen.h | 2 -- include/configs/p1_p2_rdb_pc.h | 3 --- include/configs/p1_twr.h | 3 --- include/configs/pcl063.h | 2 -- include/configs/pcl063_ull.h | 2 -- include/configs/pcm051.h | 3 --- include/configs/pcm052.h | 3 --- include/configs/pic32mzdask.h | 2 -- include/configs/pico-imx6.h | 3 --- include/configs/pico-imx6ul.h | 3 --- include/configs/pico-imx7d.h | 3 --- include/configs/picosam9g45.h | 3 --- include/configs/platinum.h | 4 ---- include/configs/pm9261.h | 3 --- include/configs/pm9263.h | 3 --- include/configs/pm9g45.h | 3 --- include/configs/presidio_asic.h | 3 --- include/configs/qemu-mips.h | 3 --- include/configs/qemu-mips64.h | 3 --- include/configs/qemu-ppce500.h | 3 --- include/configs/r2dplus.h | 3 --- include/configs/r7780mp.h | 3 --- include/configs/rpi.h | 2 -- include/configs/s32v234evb.h | 3 --- include/configs/s5p_goni.h | 2 -- include/configs/s5pc210_universal.h | 2 -- include/configs/sandbox.h | 2 -- include/configs/sbc8349.h | 2 -- include/configs/sbc8548.h | 2 -- include/configs/sbc8641d.h | 2 -- include/configs/secomx6quq7.h | 3 --- include/configs/sh7752evb.h | 3 --- include/configs/sh7753evb.h | 3 --- include/configs/sh7757lcr.h | 3 --- include/configs/sh7763rdp.h | 2 -- include/configs/siemens-am33x-common.h | 3 --- include/configs/smartweb.h | 2 -- include/configs/smdkc100.h | 2 -- include/configs/smdkv310.h | 2 -- include/configs/snapper9260.h | 2 -- include/configs/snapper9g45.h | 2 -- include/configs/socfpga_common.h | 2 -- include/configs/socfpga_soc64_common.h | 2 -- include/configs/socrates.h | 2 -- include/configs/somlabs_visionsom_6ull.h | 2 -- include/configs/spear-common.h | 2 -- include/configs/stm32mp1.h | 4 ---- include/configs/stmark2.h | 2 -- include/configs/strider.h | 2 -- include/configs/stv0991.h | 3 --- include/configs/t4qds.h | 3 --- include/configs/tam3517-common.h | 3 --- include/configs/tao3530.h | 2 -- include/configs/tbs2910.h | 4 ---- include/configs/tegra-common.h | 3 --- include/configs/thunderx_88xx.h | 3 --- include/configs/ti814x_evm.h | 4 ---- include/configs/titanium.h | 3 --- include/configs/topic_miami.h | 4 ---- include/configs/tplink_wdr4300.h | 2 -- include/configs/trats.h | 2 -- include/configs/trats2.h | 2 -- include/configs/tricorder.h | 4 ---- include/configs/turris_mox.h | 2 -- include/configs/udoo.h | 3 --- include/configs/udoo_neo.h | 2 -- include/configs/usb_a9263.h | 3 --- include/configs/usbarmory.h | 3 --- include/configs/vcoreiii.h | 4 ---- include/configs/ve8313.h | 2 -- include/configs/verdin-imx8mm.h | 4 ---- include/configs/vexpress_aemv8a.h | 2 -- include/configs/vexpress_common.h | 3 --- include/configs/vf610twr.h | 3 --- include/configs/vining_2000.h | 2 -- include/configs/vme8349.h | 2 -- include/configs/vocore2.h | 2 -- include/configs/wandboard.h | 3 --- include/configs/warp.h | 3 --- include/configs/warp7.h | 3 --- include/configs/wb45n.h | 2 -- include/configs/wb50n.h | 3 --- include/configs/work_92105.h | 2 -- include/configs/x600.h | 2 -- include/configs/x86-common.h | 2 -- include/configs/xilinx_versal.h | 3 --- include/configs/xilinx_zynqmp.h | 3 --- include/configs/xilinx_zynqmp_r5.h | 4 ---- include/configs/xpedite517x.h | 2 -- include/configs/xpedite520x.h | 2 -- include/configs/xpedite537x.h | 2 -- include/configs/xpedite550x.h | 2 -- include/configs/xpress.h | 2 -- include/configs/xtfpga.h | 2 -- include/configs/zmx25.h | 3 --- include/configs/zynq-common.h | 3 --- scripts/config_whitelist.txt | 2 -- 496 files changed, 417 insertions(+), 804 deletions(-) diff --git a/README b/README index eb7892d4c15..be9e6391d6b 100644 --- a/README +++ b/README @@ -2473,10 +2473,6 @@ Configuration Settings: - CONFIG_SYS_BAUDRATE_TABLE: List of legal baudrate settings for this board. -- CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END: - Begin and End addresses of the area used by the - simple memory test. - - CONFIG_SYS_MEM_RESERVE_SECURE Only implemented for ARMv8 for now. If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 23bbdcccacf..8f7e7f05d82 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -330,8 +330,12 @@ void post_word_store(ulong value) int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) { - *vstart = CONFIG_SYS_MEMTEST_START; - *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START; + /* + * These match CONFIG_SYS_MEMTEST_START and + * (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) + */ + *vstart = 0x00100000; + *size = 0xe00000; debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size); return 0; diff --git a/cmd/Kconfig b/cmd/Kconfig index 157a33081ff..f9be1988f65 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -750,6 +750,22 @@ config SYS_ALT_MEMTEST help Use a more complete alternative memory test. +config SYS_MEMTEST_START + hex "default start address for mtest" + default 0 + help + This is the default start address for mtest for simple read/write + test. If no arguments are given to mtest, default address is used + as start address. + +config SYS_MEMTEST_END + hex "default end address for mtest" + default 0x1000 + help + This is the default end address for mtest for simple read/write + test. If no arguments are given to mtest, default address is used + as end address. + endif config CMD_SHA1SUM diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig index ca74b8800d6..75604383c6c 100644 --- a/configs/T1023RDB_NAND_defconfig +++ b/configs/T1023RDB_NAND_defconfig @@ -31,6 +31,8 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig index 4edc69aac56..4471c83f3fd 100644 --- a/configs/T1023RDB_SDCARD_defconfig +++ b/configs/T1023RDB_SDCARD_defconfig @@ -29,6 +29,8 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig index 5ddaac6e2e2..34fe6e5e528 100644 --- a/configs/T1023RDB_SECURE_BOOT_defconfig +++ b/configs/T1023RDB_SECURE_BOOT_defconfig @@ -17,6 +17,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig index b489a802459..599aeec6886 100644 --- a/configs/T1023RDB_SPIFLASH_defconfig +++ b/configs/T1023RDB_SPIFLASH_defconfig @@ -31,6 +31,8 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig index b8ffebc45c0..62cc129a319 100644 --- a/configs/T1023RDB_defconfig +++ b/configs/T1023RDB_defconfig @@ -16,6 +16,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index 9230c01a681..9b116548a73 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -34,6 +34,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 2e1954486fd..5e087fe2f3b 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -32,6 +32,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig index 1d221dba9ec..f23f021143a 100644 --- a/configs/T1024RDB_SECURE_BOOT_defconfig +++ b/configs/T1024RDB_SECURE_BOOT_defconfig @@ -19,6 +19,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index daf00b8fbd0..39b4537e718 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -34,6 +34,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 84e8f3b3352..8ff2fe3f0cd 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -19,6 +19,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 4485529015b..81baa5dbdd0 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -30,6 +30,8 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index 7e0682438e9..a1d7d87b60f 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -28,6 +28,8 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig index a1f8d3d1fd9..7d04a941165 100644 --- a/configs/T2080RDB_SECURE_BOOT_defconfig +++ b/configs/T2080RDB_SECURE_BOOT_defconfig @@ -15,6 +15,8 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index f1e875ba91b..c433a922e63 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -30,6 +30,8 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig index 6c16bfa19f4..a8f0a965c13 100644 --- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig @@ -13,6 +13,8 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 2e3917614c3..85e3b64ad33 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -15,6 +15,8 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig index af83ef5e943..5d7a8de71d6 100644 --- a/configs/ap121_defconfig +++ b/configs/ap121_defconfig @@ -24,6 +24,8 @@ CONFIG_SYS_PROMPT="ap121 # " # CONFIG_CMD_EDITENV is not set # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80100000 +CONFIG_SYS_MEMTEST_END=0x83f00000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_SPI=y CONFIG_CMD_DHCP=y diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig index 3d5849dd0a5..68cc8e03bbd 100644 --- a/configs/ap143_defconfig +++ b/configs/ap143_defconfig @@ -25,6 +25,8 @@ CONFIG_SYS_PROMPT="ap143 # " # CONFIG_CMD_EDITENV is not set # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80100000 +CONFIG_SYS_MEMTEST_END=0x83f00000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_SPI=y CONFIG_CMD_MTDPARTS=y diff --git a/configs/ap152_defconfig b/configs/ap152_defconfig index 6ed89a2ea16..434e3c1406c 100644 --- a/configs/ap152_defconfig +++ b/configs/ap152_defconfig @@ -25,6 +25,8 @@ CONFIG_SYS_PROMPT="ap152 # " # CONFIG_CMD_EDITENV is not set # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80100000 +CONFIG_SYS_MEMTEST_END=0x83f00000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_SPI=y CONFIG_CMD_MTDPARTS=y diff --git a/configs/apalis-imx8qm_defconfig b/configs/apalis-imx8qm_defconfig index 84bc0bb929b..4c27c334591 100644 --- a/configs/apalis-imx8qm_defconfig +++ b/configs/apalis-imx8qm_defconfig @@ -18,6 +18,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x88000000 +CONFIG_SYS_MEMTEST_END=0x89000000 CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_FUSE=y diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index ea18ef908cb..4c6b1006546 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -40,6 +40,8 @@ CONFIG_CMD_ASKENV=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig index 2a72355c696..785283fbea8 100644 --- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig +++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig @@ -17,6 +17,8 @@ CONFIG_BOOTDELAY=0 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_OS_BOOT=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_MMC=y diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig index deec16e55cb..8c2bda6984a 100644 --- a/configs/bk4r1_defconfig +++ b/configs/bk4r1_defconfig @@ -20,6 +20,8 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_ELF is not set CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80010000 +CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_CMD_DM=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y diff --git a/configs/boston32r2_defconfig b/configs/boston32r2_defconfig index c1422613311..189b824544b 100644 --- a/configs/boston32r2_defconfig +++ b/configs/boston32r2_defconfig @@ -15,6 +15,8 @@ CONFIG_SYS_PROMPT="boston # " # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y diff --git a/configs/boston32r2el_defconfig b/configs/boston32r2el_defconfig index c6c7f00acd3..eb2454e296f 100644 --- a/configs/boston32r2el_defconfig +++ b/configs/boston32r2el_defconfig @@ -16,6 +16,8 @@ CONFIG_SYS_PROMPT="boston # " # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y diff --git a/configs/boston32r6_defconfig b/configs/boston32r6_defconfig index 0fffc46ae61..f3e0908d5bf 100644 --- a/configs/boston32r6_defconfig +++ b/configs/boston32r6_defconfig @@ -16,6 +16,8 @@ CONFIG_SYS_PROMPT="boston # " # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y diff --git a/configs/boston32r6el_defconfig b/configs/boston32r6el_defconfig index 1ecc06d4402..0d139d83072 100644 --- a/configs/boston32r6el_defconfig +++ b/configs/boston32r6el_defconfig @@ -17,6 +17,8 @@ CONFIG_SYS_PROMPT="boston # " # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y diff --git a/configs/boston64r2_defconfig b/configs/boston64r2_defconfig index 46e78c7fef2..8ba301f6bdb 100644 --- a/configs/boston64r2_defconfig +++ b/configs/boston64r2_defconfig @@ -16,6 +16,8 @@ CONFIG_SYS_PROMPT="boston # " # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y diff --git a/configs/boston64r2el_defconfig b/configs/boston64r2el_defconfig index aa075398e4c..6db2f2b887f 100644 --- a/configs/boston64r2el_defconfig +++ b/configs/boston64r2el_defconfig @@ -17,6 +17,8 @@ CONFIG_SYS_PROMPT="boston # " # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y diff --git a/configs/boston64r6_defconfig b/configs/boston64r6_defconfig index 216e61c8bfa..b0bbf51a527 100644 --- a/configs/boston64r6_defconfig +++ b/configs/boston64r6_defconfig @@ -16,6 +16,8 @@ CONFIG_SYS_PROMPT="boston # " # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y diff --git a/configs/boston64r6el_defconfig b/configs/boston64r6el_defconfig index 354ae8e53bd..030d708e559 100644 --- a/configs/boston64r6el_defconfig +++ b/configs/boston64r6el_defconfig @@ -17,6 +17,8 @@ CONFIG_SYS_PROMPT="boston # " # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index 7e997552e35..74a67a02000 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -26,6 +26,8 @@ CONFIG_SYS_PROMPT="Colibri iMX6ULL # " CONFIG_CMD_ASKENV=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_DFU=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/colibri-imx8qxp_defconfig b/configs/colibri-imx8qxp_defconfig index fa5bd4aca17..d86cefafc68 100644 --- a/configs/colibri-imx8qxp_defconfig +++ b/configs/colibri-imx8qxp_defconfig @@ -18,6 +18,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x88000000 +CONFIG_SYS_MEMTEST_END=0x89000000 CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 8fbd9fcf1fd..adb7c950195 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -39,6 +39,8 @@ CONFIG_CMD_ASKENV=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index e434a774002..7596478ee36 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -27,6 +27,8 @@ CONFIG_SYS_PROMPT="Colibri iMX7 # " # CONFIG_CMD_XIMG is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x8c000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index 814667adf9c..c23ff97daa1 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -29,6 +29,8 @@ CONFIG_SYS_PROMPT="Colibri iMX7 # " CONFIG_CMD_ASKENV=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x8c000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index 91afabe5438..c494fb40e94 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -29,6 +29,8 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80010000 +CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_CMD_DFU=y CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set diff --git a/configs/crs305-1g-4s_defconfig b/configs/crs305-1g-4s_defconfig index 3b513cc1582..7632fc4254b 100644 --- a/configs/crs305-1g-4s_defconfig +++ b/configs/crs305-1g-4s_defconfig @@ -13,6 +13,8 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00800000 +CONFIG_SYS_MEMTEST_END=0x00ffffff # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_SPI=y diff --git a/configs/db-xc3-24g4xg_defconfig b/configs/db-xc3-24g4xg_defconfig index 0d49d406cab..2bbff646653 100644 --- a/configs/db-xc3-24g4xg_defconfig +++ b/configs/db-xc3-24g4xg_defconfig @@ -15,6 +15,8 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00800000 +CONFIG_SYS_MEMTEST_END=0x00ffffff # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_SPI=y diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index dcfbbb6d5a5..e0dfffa4b57 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -33,6 +33,8 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x20000000 CONFIG_CMD_UNZIP=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index d125a6eb9db..7111905eeee 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -127,6 +127,8 @@ CONFIG_CMD_CPU=y CONFIG_CMD_BINOP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00001000 +CONFIG_SYS_MEMTEST_END=0x07e00000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig index fb18458cbe5..340718c572c 100644 --- a/configs/imx6dl_icore_nand_defconfig +++ b/configs/imx6dl_icore_nand_defconfig @@ -24,6 +24,8 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="icorem6qdl> " CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig index 8f03f2fc9ed..7c4913debd4 100644 --- a/configs/imx6dl_mamoj_defconfig +++ b/configs/imx6dl_mamoj_defconfig @@ -15,6 +15,8 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_SPL_OS_BOOT=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig index 4f42f7a8355..6b3cb8d8d3a 100644 --- a/configs/imx6q_icore_nand_defconfig +++ b/configs/imx6q_icore_nand_defconfig @@ -25,6 +25,8 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="icorem6qdl> " CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index f4ec96c6e6c..be704125a92 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -38,6 +38,8 @@ CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x1500000 CONFIG_CMD_SPL_WRITE_SIZE=0x00100000 CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10010000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/imx6qdl_icore_mipi_defconfig b/configs/imx6qdl_icore_mipi_defconfig index fe37760d7fb..7b13e1fd781 100644 --- a/configs/imx6qdl_icore_mipi_defconfig +++ b/configs/imx6qdl_icore_mipi_defconfig @@ -31,6 +31,8 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="icorem6qdl-mipi> " CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index 486268cee9f..4b2e1f4780f 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -34,6 +34,8 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="icorem6qdl> " CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig index 4f42f7a8355..6b3cb8d8d3a 100644 --- a/configs/imx6qdl_icore_nand_defconfig +++ b/configs/imx6qdl_icore_nand_defconfig @@ -25,6 +25,8 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="icorem6qdl> " CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig index f9a748d66c2..a224baf6398 100644 --- a/configs/imx6qdl_icore_rqs_defconfig +++ b/configs/imx6qdl_icore_rqs_defconfig @@ -28,6 +28,8 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="icorem6qdl-rqs> " CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig index 8ae72e7ee49..5e27fd6bd1c 100644 --- a/configs/imx6ul_geam_mmc_defconfig +++ b/configs/imx6ul_geam_mmc_defconfig @@ -26,6 +26,8 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="geam6ul> " CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig index 15201d2ef05..ce1c3ddeeef 100644 --- a/configs/imx6ul_geam_nand_defconfig +++ b/configs/imx6ul_geam_nand_defconfig @@ -26,6 +26,8 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="geam6ul> " CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig index 35c974ebef5..31404582821 100644 --- a/configs/imx6ul_isiot_emmc_defconfig +++ b/configs/imx6ul_isiot_emmc_defconfig @@ -26,6 +26,8 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="isiotmx6ul> " CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/imx6ul_isiot_nand_defconfig b/configs/imx6ul_isiot_nand_defconfig index bfa03a791d9..c9c2660d60f 100644 --- a/configs/imx6ul_isiot_nand_defconfig +++ b/configs/imx6ul_isiot_nand_defconfig @@ -26,6 +26,8 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="isiotmx6ul> " CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig index 7c94478e0a7..b1606e54c45 100644 --- a/configs/liteboard_defconfig +++ b/configs/liteboard_defconfig @@ -23,6 +23,8 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig index 9bf5b9c16b0..18b72b465ca 100644 --- a/configs/ls1012a2g5rdb_qspi_defconfig +++ b/configs/ls1012a2g5rdb_qspi_defconfig @@ -23,6 +23,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig index d9d4f8206c8..4ca57d1debc 100644 --- a/configs/ls1012a2g5rdb_tfa_defconfig +++ b/configs/ls1012a2g5rdb_tfa_defconfig @@ -23,6 +23,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index 02a80b1a596..1a4cc37555c 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -22,6 +22,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index ecc4c81eb3f..177fcd4ff63 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -22,6 +22,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index 3dc3f9e77d1..a702cc82b9a 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -21,6 +21,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index 61302697063..187015c2b2e 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -22,6 +22,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index 9f2c7ddb0ae..5071bb75dfb 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -21,6 +21,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index ca0575e41b7..c5ed91a7d3e 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -22,6 +22,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index 78266612398..1c3d7bcd756 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -26,6 +26,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index 8ab6cbc3f80..0833a2ae5ec 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -24,6 +24,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index 1b783c524f6..7fc9e15bc41 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -26,6 +26,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index 4031b9bbd75..b6110c022a3 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -23,6 +23,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index 01770b89d4d..9c2a308e73e 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -23,6 +23,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index 57e9dd9957c..736810d7735 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -23,6 +23,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index 06584ff1dca..fc3dc4a0e79 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -23,6 +23,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 203303b6e12..24e0316eb1d 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -21,6 +21,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index f77b6dbd9db..f0f3a747c6c 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -22,6 +22,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index dc45f8fbf46..8a88c5fd393 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -37,6 +37,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index aaf0f137853..547b6393ba9 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -22,6 +22,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index 9211f97a634..58d251b9086 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -21,6 +21,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index c27147e3435..f74a4c6b294 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -22,6 +22,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index c3b5627702f..f91534cfdd6 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -23,6 +23,8 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index e08f2839619..8d342138551 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -35,6 +35,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 605a3785845..9871c8edf44 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -34,6 +34,8 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index af8b8ffd7d3..0bf4aad1029 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -23,6 +23,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 3e63933ea27..5507dbe3c13 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -22,6 +22,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index 01b5205df41..cdf81957a84 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -24,6 +24,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 504b2d9afcb..4c82d668998 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -25,6 +25,8 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 82e62441036..9039ccc8f25 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -38,6 +38,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index ad05bc49a3e..478d3df1b80 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -37,6 +37,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 18fd5c36e26..de783a8d3da 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -36,6 +36,8 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index d2c6fbf03c5..4fd9ff8f3a7 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -21,6 +21,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index 23d1b28e51a..fc6344cd7ce 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -22,6 +22,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig index e3aa3d3cfb8..e0348279d9f 100644 --- a/configs/ls1028aqds_tfa_lpuart_defconfig +++ b/configs/ls1028aqds_tfa_lpuart_defconfig @@ -22,6 +22,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index 6fa7f8364a1..96f190d8595 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -20,6 +20,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 98ff99737a9..1f05ae57cc1 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -21,6 +21,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index cd01a8dc374..da56fce6938 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -20,6 +20,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index 1976e27d7fb..9d450b3d639 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -21,6 +21,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 1a1643eded3..a08ec2a7e45 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -36,6 +36,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index bd05cab3abc..fe025facdd8 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -20,6 +20,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 50af1a79ef5..9ea003e735e 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -22,6 +22,8 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index e5a91a3ab20..862458c7c77 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -36,6 +36,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 42d0642ff72..c5887cce447 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -35,6 +35,8 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index 9dccd1131d0..f10d4d9425a 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -22,6 +22,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 2be983f10fd..4fcdca83e7d 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -23,6 +23,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index d3521c37b5b..caa4221875a 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -20,6 +20,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index cf92386dc27..838d97cde49 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -20,6 +20,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index a75a523f54f..d89b7791b27 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -21,6 +21,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index 8f92af55b25..4aebca71088 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -29,6 +29,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index 239483f3142..b98101d0b53 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -21,6 +21,8 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index c5ef64a70a3..a68c43566db 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -37,6 +37,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index a4d714f801b..616e420e0d1 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -36,6 +36,8 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index ece7c19ce09..03cd17feb6d 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -22,6 +22,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index f1693e1f4cb..d50a8ebd7f8 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -23,6 +23,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index a601b11defe..61e05ceda67 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -19,6 +19,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index f6b22731140..e51fdcab203 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -21,6 +21,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index ff3610c0a11..f7d0c15707d 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -22,6 +22,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index c1bb88af8c0..57e706a4c48 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -30,6 +30,8 @@ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index b22eb8400a8..4ff7173369b 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -32,6 +32,8 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index 034ceb3c8d3..e66a61c0896 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -25,6 +25,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index 806d7705dea..f00307f964e 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -22,6 +22,8 @@ CONFIG_MISC_INIT_R=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index 9b66fd91017..0572c9c241d 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -23,6 +23,8 @@ CONFIG_MISC_INIT_R=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index 4a15f82e9e5..3e00a25857d 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -34,6 +34,8 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index 1ab1fa3a2f6..b6e21b27563 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -33,6 +33,8 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 4ad9a66333a..dba45267349 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -25,6 +25,8 @@ CONFIG_MISC_INIT_R=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index 7690292db4d..1c36801e654 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -26,6 +26,8 @@ CONFIG_MISC_INIT_R=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/meerkat96_defconfig b/configs/meerkat96_defconfig index 894ddc6c79a..191288f8360 100644 --- a/configs/meerkat96_defconfig +++ b/configs/meerkat96_defconfig @@ -19,6 +19,8 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y diff --git a/configs/mscc_jr2_defconfig b/configs/mscc_jr2_defconfig index c77b1c07c8c..9bd90ddc3d7 100644 --- a/configs/mscc_jr2_defconfig +++ b/configs/mscc_jr2_defconfig @@ -29,6 +29,8 @@ CONFIG_SYS_PROMPT="jr2 # " CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fc00000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_SPI=y diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig index b42b704e912..a57d033d30a 100644 --- a/configs/mscc_luton_defconfig +++ b/configs/mscc_luton_defconfig @@ -31,6 +31,8 @@ CONFIG_SYS_PROMPT="luton # " CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x87c00000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_SPI=y diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig index ecab4d0afdb..32f4148e755 100644 --- a/configs/mscc_ocelot_defconfig +++ b/configs/mscc_ocelot_defconfig @@ -28,6 +28,8 @@ CONFIG_SYS_PROMPT="ocelot # " CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fc00000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_MTD=y diff --git a/configs/mscc_serval_defconfig b/configs/mscc_serval_defconfig index ee12e7cd183..e35219e3ce4 100644 --- a/configs/mscc_serval_defconfig +++ b/configs/mscc_serval_defconfig @@ -26,6 +26,8 @@ CONFIG_SYS_PROMPT="serval # " CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x87c00000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_SPI=y diff --git a/configs/mscc_servalt_defconfig b/configs/mscc_servalt_defconfig index 5caef62a682..669d9f6c23f 100644 --- a/configs/mscc_servalt_defconfig +++ b/configs/mscc_servalt_defconfig @@ -25,6 +25,8 @@ CONFIG_SYS_PROMPT="servalt # " CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fc00000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_SPI=y diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig index 5063049fdc3..8b5e0ff9b13 100644 --- a/configs/mx6memcal_defconfig +++ b/configs/mx6memcal_defconfig @@ -31,6 +31,8 @@ CONFIG_HUSH_PARSER=y # CONFIG_CMD_ENV_EXISTS is not set CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x20000000 # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_CACHE=y diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index 510b8d721ae..ea338c1b53a 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -20,6 +20,8 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10010000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig index 064684a68bd..48cace51011 100644 --- a/configs/mx6sllevk_defconfig +++ b/configs/mx6sllevk_defconfig @@ -14,6 +14,8 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig index ae06ad4535c..a32b19851dd 100644 --- a/configs/mx6sllevk_plugin_defconfig +++ b/configs/mx6sllevk_plugin_defconfig @@ -15,6 +15,8 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index 6498f024b8c..94b36d26157 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -26,6 +26,8 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index ce87cc1b269..9bb11f580ef 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -26,6 +26,8 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index 357932ae62d..344e03a8de8 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -13,6 +13,8 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index a5451fc9418..2811d868aca 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -14,6 +14,8 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig index ae81e10b3b6..37b518a763b 100644 --- a/configs/mx6ulz_14x14_evk_defconfig +++ b/configs/mx6ulz_14x14_evk_defconfig @@ -13,6 +13,8 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index e948091a920..df87e2d1710 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -24,6 +24,8 @@ CONFIG_BOUNCE_BUFFER=y # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig index 23a1c458378..3a07b704b5b 100644 --- a/configs/mx7dsabresd_qspi_defconfig +++ b/configs/mx7dsabresd_qspi_defconfig @@ -24,6 +24,8 @@ CONFIG_BOUNCE_BUFFER=y # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig index 62d37b33696..680445bea75 100644 --- a/configs/mx7ulp_evk_defconfig +++ b/configs/mx7ulp_evk_defconfig @@ -12,6 +12,8 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x9e000000 CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig index 8d24fe7ac12..b70c36c7c95 100644 --- a/configs/mx7ulp_evk_plugin_defconfig +++ b/configs/mx7ulp_evk_plugin_defconfig @@ -10,6 +10,8 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" CONFIG_BOUNCE_BUFFER=y CONFIG_HUSH_PARSER=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x9e000000 CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index 57d7ca9d174..f6b0655f0fe 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -22,6 +22,8 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10010000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index b0f28c527e7..0de09d4a09c 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -22,6 +22,8 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10010000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index 02632dcde65..0757aa01c62 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -22,6 +22,8 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10010000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index 8e041999839..d9e0760ead7 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -22,6 +22,8 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10010000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index 592fb4a7393..f5396b6cb77 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -22,6 +22,8 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10010000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index 3a4572ad080..a9aa8ad59be 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -22,6 +22,8 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10010000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig index 61928948136..4f77026212a 100644 --- a/configs/pcm052_defconfig +++ b/configs/pcm052_defconfig @@ -14,6 +14,8 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80010000 +CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig index 760f62a4239..15e4fbb7afb 100644 --- a/configs/phycore_pcl063_defconfig +++ b/configs/phycore_pcl063_defconfig @@ -18,6 +18,8 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig index bb09a9a5a2f..b2ed1879314 100644 --- a/configs/pic32mzdask_defconfig +++ b/configs/pic32mzdask_defconfig @@ -13,6 +13,8 @@ CONFIG_SYS_PROMPT="dask # " CONFIG_LOOPW=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x88000000 +CONFIG_SYS_MEMTEST_END=0x88080000 CONFIG_CMD_CLK=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y diff --git a/configs/pico-dwarf-imx6ul_defconfig b/configs/pico-dwarf-imx6ul_defconfig index bb0281395e3..66fad2a8235 100644 --- a/configs/pico-dwarf-imx6ul_defconfig +++ b/configs/pico-dwarf-imx6ul_defconfig @@ -25,6 +25,8 @@ CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig index ffa5cc8d07d..a33555e04a2 100644 --- a/configs/pico-hobbit-imx6ul_defconfig +++ b/configs/pico-hobbit-imx6ul_defconfig @@ -26,6 +26,8 @@ CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig index 24948ddd55e..8113bd0074e 100644 --- a/configs/pico-imx6ul_defconfig +++ b/configs/pico-imx6ul_defconfig @@ -28,6 +28,8 @@ CONFIG_CMD_BOOTMENU=y CONFIG_CMD_SPL=y CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index 2836edc64b0..ea9caa75cf7 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -27,6 +27,8 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_SPL=y CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig index 5eb6fe2ec59..046acfc4557 100644 --- a/configs/pico-pi-imx6ul_defconfig +++ b/configs/pico-pi-imx6ul_defconfig @@ -26,6 +26,8 @@ CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/s32v234evb_defconfig b/configs/s32v234evb_defconfig index 1fb25ee2ba1..99720a9193a 100644 --- a/configs/s32v234evb_defconfig +++ b/configs/s32v234evb_defconfig @@ -11,6 +11,8 @@ CONFIG_BOOTARGS="console=ttyLF0 root=/dev/ram rw" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0xc0000000 +CONFIG_SYS_MEMTEST_END=0xc7c00000 CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index d69b185aa8b..c1237ea2964 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -35,6 +35,8 @@ CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00100000 +CONFIG_SYS_MEMTEST_END=0x00101000 CONFIG_CMD_DEMO=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 781238763a5..9445d781182 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -39,6 +39,8 @@ CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00100000 +CONFIG_SYS_MEMTEST_END=0x00101000 CONFIG_CMD_BIND=y CONFIG_CMD_DEMO=y CONFIG_CMD_GPIO=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index 00d9359f197..a4a7ae83795 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -29,6 +29,8 @@ CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00100000 +CONFIG_SYS_MEMTEST_END=0x00101000 CONFIG_CMD_DEMO=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 18c6a476029..945fe54d20d 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -39,6 +39,8 @@ CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00100000 +CONFIG_SYS_MEMTEST_END=0x00101000 CONFIG_CMD_DEMO=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig index b207592ee8e..188b0eec65a 100644 --- a/configs/sansa_fuze_plus_defconfig +++ b/configs/sansa_fuze_plus_defconfig @@ -22,6 +22,8 @@ CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_SPL_FRAMEWORK is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x40400000 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 4bca53aebba..35316d7c252 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -17,6 +17,8 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x3fe00000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 099ed7e9cb2..c95a7fc5e07 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -25,6 +25,8 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x40000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 155de1a6439..21014f9f8cd 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -16,6 +16,8 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x3fe00000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/somlabs_visionsom_6ull_defconfig b/configs/somlabs_visionsom_6ull_defconfig index 03e37afb5c2..08469d68b62 100644 --- a/configs/somlabs_visionsom_6ull_defconfig +++ b/configs/somlabs_visionsom_6ull_defconfig @@ -13,6 +13,8 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index a9b996c0a3f..c9289934ac5 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -26,6 +26,8 @@ CONFIG_SYS_PROMPT="STM32MP> " # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0xc0000000 +CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_CMD_ADC=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index 661c0544948..c2f3a5ebc15 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -24,6 +24,8 @@ CONFIG_SYS_PROMPT="STM32MP> " CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0xc0000000 +CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_CMD_ADC=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y diff --git a/configs/stm32mp15_optee_defconfig b/configs/stm32mp15_optee_defconfig index 9f886fb0e7d..443e2c40b78 100644 --- a/configs/stm32mp15_optee_defconfig +++ b/configs/stm32mp15_optee_defconfig @@ -19,6 +19,8 @@ CONFIG_SYS_PROMPT="STM32MP> " # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0xc0000000 +CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_CMD_ADC=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index a4ea8c82297..33f6926fa9e 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -15,6 +15,8 @@ CONFIG_SYS_PROMPT="STM32MP> " # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0xc0000000 +CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_CMD_ADC=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 0790c76a701..599438232de 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -109,6 +109,8 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00001000 +CONFIG_SYS_MEMTEST_END=0x07f00000 CONFIG_CMD_FPGAD=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index f203f404645..bf52ae701b6 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -109,6 +109,8 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00001000 +CONFIG_SYS_MEMTEST_END=0x07f00000 CONFIG_CMD_FPGAD=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index c2875c51a7a..d34ca9edd2b 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -109,6 +109,8 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00001000 +CONFIG_SYS_MEMTEST_END=0x07f00000 CONFIG_CMD_FPGAD=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index 7647fd800b1..01cdf0c43fd 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -109,6 +109,8 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00001000 +CONFIG_SYS_MEMTEST_END=0x07f00000 CONFIG_CMD_FPGAD=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig index 0b52b007332..54f1cd2bfdc 100644 --- a/configs/stv0991_defconfig +++ b/configs/stv0991_defconfig @@ -18,6 +18,8 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x00100000 CONFIG_CMD_SPI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index f4fdd38c3f5..2ff0e160f73 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -24,6 +24,8 @@ CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_VXWORKS is not set # CONFIG_CMD_FDT is not set CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x2f400000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index 5c244b49991..f50d12d154e 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -23,6 +23,8 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="zynq-uboot> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x18000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index 068b5bcdc14..d2fe64ed9ee 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -23,6 +23,8 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="zynq-uboot> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x18000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index 86980774e5f..9afd7f6bcad 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -23,6 +23,8 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="zynq-uboot> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x18000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig index 6d59ba4e669..f9d37b1365f 100644 --- a/configs/tplink_wdr4300_defconfig +++ b/configs/tplink_wdr4300_defconfig @@ -14,6 +14,8 @@ CONFIG_HUSH_PARSER=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80100000 +CONFIG_SYS_MEMTEST_END=0x83f00000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_SPI=y CONFIG_CMD_USB=y diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index 07d86127409..fff98733bff 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -33,6 +33,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00800000 +CONFIG_SYS_MEMTEST_END=0x00ffffff CONFIG_CMD_SHA1SUM=y CONFIG_CMD_LZMADEC=y CONFIG_CMD_GPIO=y diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig index da14fb02873..0564bdcce11 100644 --- a/configs/usbarmory_defconfig +++ b/configs/usbarmory_defconfig @@ -9,6 +9,8 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_DISTRO_DEFAULTS=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x70000000 +CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_CMD_FUSE=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index c852ad26237..c68b299a959 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -44,6 +44,8 @@ CONFIG_CMD_ASKENV=y # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index 84f6d403285..49acb343106 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -18,6 +18,8 @@ CONFIG_SYS_PROMPT="VExpress64# " # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EDITENV is not set CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xff000000 CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_USB=y diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig index c9093260f3d..f0ac2f9da34 100644 --- a/configs/vexpress_aemv8a_semi_defconfig +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -20,6 +20,8 @@ CONFIG_CMD_ABOOTIMG=y # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EDITENV is not set CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xff000000 CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_LOADS is not set # CONFIG_CMD_ITEST is not set diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig index 84828c91f02..2849ddd9a8e 100644 --- a/configs/vf610twr_defconfig +++ b/configs/vf610twr_defconfig @@ -15,6 +15,8 @@ CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80010000 +CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig index 27fb40e2972..9bf8ea2091f 100644 --- a/configs/vf610twr_nand_defconfig +++ b/configs/vf610twr_nand_defconfig @@ -15,6 +15,8 @@ CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80010000 +CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig index e731d6ff58d..38aeab69f89 100644 --- a/configs/warp7_bl33_defconfig +++ b/configs/warp7_bl33_defconfig @@ -15,6 +15,8 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index a5fb48ff1fb..70fa486e9ea 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -21,6 +21,8 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y diff --git a/configs/wb45n_defconfig b/configs/wb45n_defconfig index fbb039dec9d..d2de463aaa1 100644 --- a/configs/wb45n_defconfig +++ b/configs/wb45n_defconfig @@ -20,6 +20,8 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x20000000 +CONFIG_SYS_MEMTEST_END=0x23e00000 # CONFIG_CMD_FLASH is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_NAND=y diff --git a/configs/wb50n_defconfig b/configs/wb50n_defconfig index 25a6edd1d87..86a8549406b 100644 --- a/configs/wb50n_defconfig +++ b/configs/wb50n_defconfig @@ -20,6 +20,8 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x21000000 +CONFIG_SYS_MEMTEST_END=0x22000000 # CONFIG_CMD_FLASH is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_NAND=y diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig index 0743592285f..a3b71ccc3e1 100644 --- a/configs/xilinx_versal_mini_defconfig +++ b/configs/xilinx_versal_mini_defconfig @@ -38,6 +38,8 @@ CONFIG_SYS_PROMPT="Versal> " # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x00001000 # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_ECHO is not set diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index e8c34926120..b629f8ba698 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -15,6 +15,8 @@ CONFIG_SYS_PROMPT="Versal> " CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y CONFIG_CMD_DM=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 7441e10d325..375d54cbad6 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -24,6 +24,8 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_IMLS=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_CMD_DFU=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig index 2d9a3b3a5f3..c28efa3582a 100644 --- a/configs/xilinx_zynqmp_mini_defconfig +++ b/configs/xilinx_zynqmp_mini_defconfig @@ -33,6 +33,8 @@ CONFIG_ZYNQMP_PSU_INIT_ENABLED=y # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x00001000 # CONFIG_CMD_DM is not set # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 73e8d84b888..57be5a49f65 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -25,6 +25,8 @@ CONFIG_CMD_BOOTMENU=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig index 3c18dea65b9..04b0a14f9da 100644 --- a/configs/xpress_defconfig +++ b/configs/xpress_defconfig @@ -14,6 +14,8 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig index aae7f6d29b3..7cae6666769 100644 --- a/configs/xpress_spl_defconfig +++ b/configs/xpress_spl_defconfig @@ -25,6 +25,8 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/zc5202_defconfig b/configs/zc5202_defconfig index ce40145ea4e..4c298cb4da9 100644 --- a/configs/zc5202_defconfig +++ b/configs/zc5202_defconfig @@ -28,6 +28,8 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10800000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/zc5601_defconfig b/configs/zc5601_defconfig index c1b7fb131c7..e8f4736541e 100644 --- a/configs/zc5601_defconfig +++ b/configs/zc5601_defconfig @@ -28,6 +28,8 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MEMTEST_END=0x10800000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/doc/feature-removal-schedule.txt b/doc/feature-removal-schedule.txt index b5a70da2962..546d2da17d9 100644 --- a/doc/feature-removal-schedule.txt +++ b/doc/feature-removal-schedule.txt @@ -7,18 +7,6 @@ file. --------------------------- -What: Remove unused CONFIG_SYS_MEMTEST_START/END -When: Release v2013.10 - -Why: As the 'mtest' command is no longer default, a number of platforms - have not opted to turn the command back on and thus provide unused - defines (which are likely to be propagated to new platforms from - copy/paste). Remove these defines when unused. - -Who: Tom Rini - ---------------------------- - What: Users of the legacy miiphy_* code When: undetermined diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index 3948d68014a..6abfe393fc0 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -69,10 +69,5 @@ */ #define CONFIG_SYS_LOAD_ADDR 0xcc000000 /* Half of RAM */ #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \ - CONFIG_ENV_SIZE - \ - CONFIG_SYS_MALLOC_LEN - \ - 0x10000) #endif /* __CONFIG_H */ diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h index 97bce43ce43..445eef8b150 100644 --- a/include/configs/3c120_devboard.h +++ b/include/configs/3c120_devboard.h @@ -69,10 +69,5 @@ */ #define CONFIG_SYS_LOAD_ADDR 0xd4000000 /* Half of RAM */ #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \ - CONFIG_ENV_SIZE - \ - CONFIG_SYS_MALLOC_LEN - \ - 0x10000) #endif /* __CONFIG_H */ diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index abecf90c743..67639458b41 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -128,8 +128,6 @@ unsigned long get_board_ddr_clk(void); #if 0 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ #endif -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 /* * Config the L3 Cache as L3 SRAM diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 31879f86e59..879173f6f2e 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -56,9 +56,6 @@ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* enable branch predition */ -#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01ffffff - /* DDR Setup */ #undef CONFIG_SYS_DDR_RAW_TIMING #undef CONFIG_DDR_SPD diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 4fc64a8f187..ac37ae7cb8f 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -94,9 +94,6 @@ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* enable branch predition */ -#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01ffffff - /* DDR Setup */ #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index d21537c7735..62ad50bad54 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -105,9 +105,6 @@ #define CONFIG_ADDR_MAP 1 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 -#define CONFIG_SYS_MEMTEST_END 0x00400000 - /* DDR Setup */ #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index d1cb003ff53..fc389b8e87f 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -104,9 +104,6 @@ #define CONFIG_SYS_SDRAM_EMOD 0x80010000 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) - #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index 884ed11dbab..f110cac2741 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -144,9 +144,6 @@ #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) - #ifdef CONFIG_CF_SBF # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) #else diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 2a905252560..4ab3d4831c7 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -112,9 +112,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) - #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index 97c09f94c7b..065e1e92818 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -39,9 +39,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ -#define CONFIG_SYS_MEMTEST_START 0x400 -#define CONFIG_SYS_MEMTEST_END 0x380000 - /* * Clock configuration: enable only one of the following options */ diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 9fc0f5f4d19..e79a7e98dc2 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -84,9 +84,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x00100000 -#define CONFIG_SYS_MEMTEST_START 0x400 -#define CONFIG_SYS_MEMTEST_END 0x380000 - #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ #define CONFIG_SYS_FAST_CLK #ifdef CONFIG_SYS_FAST_CLK diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 4f5e6092554..50566290438 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -79,8 +79,6 @@ "" #define CONFIG_SYS_LOAD_ADDR 0x20000 -#define CONFIG_SYS_MEMTEST_START 0x400 -#define CONFIG_SYS_MEMTEST_END 0x380000 #define CONFIG_SYS_CLK 66000000 /* diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 3efed0fb37b..ed93f4ad78a 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -72,8 +72,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x800000 #define CONFIG_BOOTCOMMAND "bootm ffe40000" -#define CONFIG_SYS_MEMTEST_START 0x400 -#define CONFIG_SYS_MEMTEST_END 0x380000 #ifdef CONFIG_MCFFEC # define CONFIG_NET_RETRY_COUNT 5 diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 62b3d3183d0..e7859f334ad 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -77,9 +77,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x20000 -#define CONFIG_SYS_MEMTEST_START 0x400 -#define CONFIG_SYS_MEMTEST_END 0x380000 - #define CONFIG_SYS_CLK 64000000 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 9ae38ff3cf0..b934dc13889 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -120,9 +120,6 @@ #define CONFIG_SYS_SDRAM_EMOD 0x80010000 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) - #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index d0ddd089af8..5c88f09f64f 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -116,9 +116,6 @@ #define CONFIG_SYS_SDRAM_EMOD 0x40010000 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) - #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index fe0f5b84fd2..6297aea143d 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -116,9 +116,6 @@ #define CONFIG_SYS_SDRAM_EMOD 0x40010000 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) - #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h index 62e34538606..cdf169f6a79 100644 --- a/include/configs/M54418TWR.h +++ b/include/configs/M54418TWR.h @@ -178,8 +178,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) #define CONFIG_SYS_DRAM_TEST #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index 7b48c662be6..8d0b1db73e5 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -152,9 +152,6 @@ #define CONFIG_SYS_SDRAM_MODE 0x008D0000 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44 -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) - #ifdef CONFIG_CF_SBF # define CONFIG_SERIAL_BOOT # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 34653f7a464..6e43522fda3 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -201,9 +201,6 @@ #define CONFIG_SYS_SDRAM_MODE 0x00010033 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) - #ifdef CONFIG_CF_SBF # define CONFIG_SERIAL_BOOT # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h index f5c007127ef..406830c98d5 100644 --- a/include/configs/M5475EVB.h +++ b/include/configs/M5475EVB.h @@ -159,9 +159,6 @@ # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ #endif -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) - #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h index ccc88ac316d..cd8dd67043f 100644 --- a/include/configs/M5485EVB.h +++ b/include/configs/M5485EVB.h @@ -147,9 +147,6 @@ # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ #endif -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) - #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index 72533bc8072..557c2ebcdb4 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -60,9 +60,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x00002000 -#define CONFIG_SYS_MEMTEST_END 0x00800000 - #define CONFIG_SYS_LOAD_ADDR 0x200000 #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 29561c41016..f55e9a09950 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -101,8 +101,6 @@ /* * Memory test */ -#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x07f00000 /* * The reserved memory diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index ea5762a5ef8..68298533430 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -57,9 +57,6 @@ #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR #endif -#define CONFIG_SYS_MEMTEST_START 0x00001000 -#define CONFIG_SYS_MEMTEST_END 0x07f00000 - /* Early revs of this board will lock up hard when attempting * to access the PMC registers, unless a JTAG debugger is * connected, or some resistor modifications are made. diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 9d4a6716c76..382c39ccb4c 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -29,9 +29,6 @@ #define CONFIG_VSC7385_ENET #define CONFIG_TSEC2 -#define CONFIG_SYS_MEMTEST_START 0x00001000 -#define CONFIG_SYS_MEMTEST_END 0x07f00000 - /* Early revs of this board will lock up hard when attempting * to access the PMC registers, unless a JTAG debugger is * connected, or some resistor modifications are made. diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 5085a95635e..2c352238682 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -98,8 +98,6 @@ * Memory test */ #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00140000 /* * The reserved memory diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index d39ba8f5d95..289cd9a8600 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -85,8 +85,6 @@ * Memory test */ #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x03f00000 /* * The reserved memory diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index f410763a7ec..bfcff2e4f88 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -85,8 +85,6 @@ * Memory test */ #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00100000 /* * The reserved memory diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 295cb169903..0a80a60d301 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -18,8 +18,6 @@ #define CONFIG_E300 1 /* E300 Family */ #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00100000 /* * DDR Setup diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 79f2e38e952..79dd9561741 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -18,8 +18,6 @@ #define CONFIG_E300 1 /* E300 Family */ #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00100000 /* * DDR Setup diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index d0ae923ec3e..90046fd1ee3 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -144,8 +144,6 @@ */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CONFIG_SYS_83XX_DDR_USES_CS0 -#define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x2000 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index e5b411b12cb..1254b4fc10e 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -107,8 +107,6 @@ * Memory test */ #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00140000 /* * The reserved memory diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 2ceb123a078..21bd9f09c17 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -132,8 +132,6 @@ * Memory test */ #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x0ef70010 /* * The reserved memory diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 8fc8dfd2b2f..fb115e23457 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -58,9 +58,6 @@ #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ #endif -#define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ -#define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ - /* * Config the L2 Cache as L2 SRAM */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index a5483dabaf8..2ba73220211 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -58,9 +58,6 @@ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - #define CONFIG_SYS_CCSRBAR 0xe0000000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index f81f4b0e646..b2a32010720 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -32,9 +32,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - #define CONFIG_SYS_CCSRBAR 0xe0000000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 4eb2888caea..2092e3da159 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -37,9 +37,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CONFIG_ENABLE_36BIT_PHYS 1 -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - #define CONFIG_SYS_CCSRBAR 0xe0000000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index b7796236fd4..6e44a072db8 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -47,9 +47,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ #endif -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - #define CONFIG_SYS_CCSRBAR 0xe0000000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index d53e156f308..d964b4e1217 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -32,9 +32,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - #define CONFIG_SYS_CCSRBAR 0xe0000000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index e61c9786c0b..866049febf2 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -57,9 +57,6 @@ #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - #define CONFIG_SYS_CCSRBAR 0xe0000000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 3a078a363c3..a0bd5f4d40f 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -35,9 +35,6 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_ENABLE_36BIT_PHYS 1 -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - #define CONFIG_SYS_CCSRBAR 0xe0000000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index da86f94e544..beba848214e 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -47,9 +47,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_HWCONFIG -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - /* * Config the L2 Cache as L2 SRAM */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 0f4c7e6f488..65da3d7009b 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -48,9 +48,6 @@ #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ #endif -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x7fffffff - /* * Config the L2 Cache as L2 SRAM */ diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 8b10a6cfef9..f3d603c6348 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -56,9 +56,6 @@ #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) #endif -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index db05a6cb077..e97d780cea0 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -63,9 +63,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) #endif -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - /* * With the exception of PCI Memory and Rapid IO, most devices will simply * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h index 2421300e1e1..b6f315a47b9 100644 --- a/include/configs/MigoR.h +++ b/include/configs/MigoR.h @@ -27,9 +27,6 @@ /* SCIF */ #define CONFIG_CONS_SCIF0 1 -#define CONFIG_SYS_MEMTEST_START (MIGO_R_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) - /* Enable alternate, more extensive, memory test */ /* Scratch address used by the alternate memory test */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index ce48ae1ef90..f578e0bd875 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -199,9 +199,6 @@ #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ #endif -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x1fffffff - /* DDR Setup */ #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_DDR_SPD diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index f8b035fb794..e99d509a36b 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -100,9 +100,6 @@ #define CONFIG_L2_CACHE #define CONFIG_BTB -#define CONFIG_SYS_MEMTEST_START 0x00000000 -#define CONFIG_SYS_MEMTEST_END 0x7fffffff - #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index 8ed351c5dc7..2f3831e2599 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -42,9 +42,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 - /* Implement conversion of addresses in the LBC */ #define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index dfc84583970..09427776e28 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -75,8 +75,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #endif #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 /* * Config the L3 Cache as L3 SRAM diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index b17113ab9a8..8f31fc4c745 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -80,8 +80,6 @@ /* * Other required minimal configurations */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ -#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ /* diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index 462e62c7c20..f4440e57646 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -80,8 +80,6 @@ /* * Other required minimal configurations */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ -#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ /* diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 7f9e0c84bb2..5f358c13eae 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -148,9 +148,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - /* * Config the L3 Cache as L3 SRAM */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 2b43b812b34..c96d6e5f35e 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -163,9 +163,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - /* * Config the L3 Cache as L3 SRAM */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index ad8efb3503d..ca6ae776fa4 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -91,9 +91,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ADDR_MAP #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - /* * Config the L3 Cache as L3 SRAM */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 7d15910f659..aa7bf7d1193 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -187,9 +187,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_ADDR_MAP #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - /* * Config the L3 Cache as L3 SRAM */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index e0ef2b25a19..619b287258f 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -100,9 +100,6 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - #if defined(CONFIG_SPIFLASH) #elif defined(CONFIG_SDCARD) #define CONFIG_SYS_MMC_ENV_DEV 0 diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index ce7634f4ea9..f051998b0ff 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -81,9 +81,6 @@ #define CONFIG_ADDR_MAP #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - /* * Config the L3 Cache as L3 SRAM */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index f557a3c9362..40fe62fdf0b 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -30,8 +30,6 @@ #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00100000 /* * FLASH on the Local Bus diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index 68276a15a74..5086077afb5 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -164,9 +164,6 @@ #define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x1fffffff - #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/adp-ae3xx.h b/include/configs/adp-ae3xx.h index 5b035c7ec5a..48dfe68ff9e 100644 --- a/include/configs/adp-ae3xx.h +++ b/include/configs/adp-ae3xx.h @@ -112,8 +112,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x300000 /* memtest works on 63 MB in DRAM */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) /* * Static memory controller configuration diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h index 71c7fe929d3..2c316a76e1c 100644 --- a/include/configs/adp-ag101p.h +++ b/include/configs/adp-ag101p.h @@ -224,8 +224,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x300000 /* memtest works on 63 MB in DRAM */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) /* * Static memory controller configuration diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h index b7b1ac2f89b..d44028d510c 100644 --- a/include/configs/advantech_dms-ba16.h +++ b/include/configs/advantech_dms-ba16.h @@ -183,9 +183,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Physical Memory Map */ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 6087a29ef4c..5c00191f4d4 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -145,9 +145,6 @@ #define CONFIG_SYS_MAXARGS 32 /* max number of command */ /* args */ /* memtest works on */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ /* address */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 89c82cee07e..cc5e8314c71 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -153,9 +153,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* memtest works on */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ /* Physical Memory Map */ #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) diff --git a/include/configs/amcore.h b/include/configs/amcore.h index bc1fc8c7b01..641d8fdbd53 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -32,9 +32,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */ -#define CONFIG_SYS_MEMTEST_START 0x0 -#define CONFIG_SYS_MEMTEST_END 0x1000000 - #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK 45000000 diff --git a/include/configs/ap121.h b/include/configs/ap121.h index 07ba195a126..4902d07247e 100644 --- a/include/configs/ap121.h +++ b/include/configs/ap121.h @@ -35,7 +35,5 @@ /* * Diagnostics */ -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x83f00000 #endif /* __CONFIG_H */ diff --git a/include/configs/ap143.h b/include/configs/ap143.h index d6c22d54893..c79e050dc9c 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -39,7 +39,5 @@ /* * Diagnostics */ -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x83f00000 #endif /* __CONFIG_H */ diff --git a/include/configs/ap152.h b/include/configs/ap152.h index 73378b95f3f..0d2c484bb9c 100644 --- a/include/configs/ap152.h +++ b/include/configs/ap152.h @@ -41,7 +41,5 @@ /* * Diagnostics */ -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x83f00000 #endif /* __CONFIG_H */ diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index 40037157339..08d34db1061 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -83,9 +83,6 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 -#define CONFIG_SYS_MEMTEST_START 0x88000000 -#define CONFIG_SYS_MEMTEST_END 0x89000000 - /* Environment in eMMC, before config block at the end of 1st "boot sector" */ #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 eMMC */ #define CONFIG_SYS_MMC_ENV_PART 1 diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 49a28f5a3f5..034eb07eaa9 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -210,9 +210,6 @@ #undef CONFIG_SYS_MAXARGS #define CONFIG_SYS_MAXARGS 48 -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Physical Memory Map */ diff --git a/include/configs/apf27.h b/include/configs/apf27.h index 351b27094a6..c26cf89f5ff 100644 --- a/include/configs/apf27.h +++ b/include/configs/apf27.h @@ -54,8 +54,6 @@ #define PHYS_SDRAM_2 0xB0000000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10)) -#define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */ -#define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \ + PHYS_SDRAM_1_SIZE - 0x0100000) diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 336cf1746ab..2674cb8b76b 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -407,9 +407,6 @@ #define CONFIG_ARP_TIMEOUT 200UL -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index c089b9c27c6..f85cd981409 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -40,9 +40,6 @@ #define SCIF4_BASE 0xe6c80000 #define CONFIG_SCIF_A -#define CONFIG_SYS_MEMTEST_START (ARMADILLO_800EVA_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - 504 * 1024 * 1024) #undef CONFIG_SYS_LOADS_BAUD_CHANGE #define CONFIG_SYS_SDRAM_BASE (ARMADILLO_800EVA_SDRAM_BASE) diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index e1128043b02..7eec226173e 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -171,9 +171,6 @@ /* Defines memory range for test */ -#define CONFIG_SYS_MEMTEST_START 0x40020000 -#define CONFIG_SYS_MEMTEST_END 0x41ffffff - /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index e52f7e440bb..37b9cc3b6fc 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -57,10 +57,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE SZ_32M -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END \ - (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K) - /* * LowLevel Init */ diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 3156118e963..e27c276a460 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -108,9 +108,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 39b879b3b1b..c3fe41636bf 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -95,9 +95,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index c08845b3c8d..85bfacb7acc 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -208,9 +208,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - #ifdef CONFIG_SYS_USE_DATAFLASH /* bootstrap + u-boot + env + linux in dataflash on CS0 */ diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index ee207cfcca2..8e2a7631f41 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -69,9 +69,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - #ifdef CONFIG_NAND_BOOT /* bootstrap + u-boot + env in nandflash */ diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index caa487b038b..7ee569521e6 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -68,9 +68,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x26e00000 - /* USB host */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_ATMEL diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 1da26049fd9..92b87a2b492 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -66,9 +66,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - #ifdef CONFIG_SYS_USE_DATAFLASH /* bootstrap + u-boot + env + linux in dataflash on CS0 */ diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index d85a4867648..eb94a190728 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -67,9 +67,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x26e00000 - #ifdef CONFIG_NAND_BOOT /* bootstrap + u-boot + env + linux in nandflash */ #define CONFIG_BOOTCOMMAND "nand read " \ diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index 45049621710..34fc6b616e7 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -91,8 +91,6 @@ /* * memtest works on 512 MB in DRAM */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* * FLASH and environment organization diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index 0566892e157..f88172a05c5 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -241,9 +241,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80010000 -#define CONFIG_SYS_MEMTEST_END 0x87C00000 - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Physical memory map */ diff --git a/include/configs/boston.h b/include/configs/boston.h index e5dc0c8e328..b9a9965eec3 100644 --- a/include/configs/boston.h +++ b/include/configs/boston.h @@ -35,9 +35,6 @@ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000) -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x10000000) - #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 6c073ab383d..e95769b2d72 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -90,8 +90,6 @@ BUR_COMMON_ENV \ /* RAM */ #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE #define CONFIG_SYS_INIT_SP_OFFSET \ diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index 63a7581d682..459712190a0 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -26,8 +26,6 @@ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00100000 /* * DDR Setup diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 254b3a5a760..2ad54f49072 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -167,10 +167,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ -#define CONFIG_SYS_MEMTEST_START 0xA0000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - (PHYS_SDRAM_1_SIZE >> 2)) - /* Console buffer and boot args */ #define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index b6dfcdd08b9..bd4456aa02e 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -187,9 +187,6 @@ "fi; " \ "else run netboot; fi" -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/ci20.h b/include/configs/ci20.h index 0f9c2ac53a3..e6b4e233d62 100644 --- a/include/configs/ci20.h +++ b/include/configs/ci20.h @@ -25,8 +25,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 #define CONFIG_SYS_LOAD_ADDR 0x81000000 #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x88000000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index d47bdd228d6..b923bae9b28 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -111,9 +111,6 @@ "echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; " \ "echo USB boot attempt ...; run usbbootscript; " -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index e62130f8ec0..302907dcfb4 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -24,8 +24,6 @@ #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE #define CONFIG_SYS_INIT_SP_OFFSET \ diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 5bd9a49f4d0..fffea0da183 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -148,10 +148,7 @@ #define CONFIG_TIMESTAMP #define CONFIG_SYS_AUTOLOAD "no" -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ /* works on */ -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ /* load address */ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index a9f5e5e8a55..fe23c2396c9 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -155,9 +155,6 @@ from which user programs will be started */ * --- */ -#define CONFIG_SYS_MEMTEST_START 0x400 -#define CONFIG_SYS_MEMTEST_END 0x380000 - /* --- * Low Level Configuration Settings * (address mappings, register initial values, etc.) diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 2a76f576a87..2d3b4c18177 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -113,9 +113,6 @@ "videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \ "vidargs=video=mxsfb:640x480M-16@60" -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x08000000) - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Physical Memory Map */ diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index 311ed439f61..03bb1701f9d 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -114,9 +114,6 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 -#define CONFIG_SYS_MEMTEST_START 0x88000000 -#define CONFIG_SYS_MEMTEST_END 0x89000000 - /* Environment in eMMC, before config block at the end of 1st "boot sector" */ #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 eMMC */ #define CONFIG_SYS_MMC_ENV_PART 1 diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 706665e37fc..2d649e6e219 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -189,9 +189,6 @@ #undef CONFIG_SYS_MAXARGS #define CONFIG_SYS_MAXARGS 48 -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Physical Memory Map */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 7c00f78ef19..09722f47e78 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -194,9 +194,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x0c000000) - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 111bb27126a..29827f1ee84 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -86,9 +86,6 @@ #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index b03ccaf0941..7d17bd8e6a0 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -138,9 +138,6 @@ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_MEMTEST_START 0x80010000 -#define CONFIG_SYS_MEMTEST_END 0x87C00000 - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index d62c784e5b7..5fbe7732018 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -121,9 +121,6 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_SYS_MEMTEST_START 0x00000000 -#define CONFIG_SYS_MEMTEST_END 0x3fffffff - #ifdef CONFIG_TRAILBLAZER #define CONFIG_SPD_EEPROM #define SPD_EEPROM_ADDRESS 0x52 diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 26f534a90ab..091f3c07d1d 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -88,8 +88,6 @@ #endif #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 /* * Config the L3 Cache as L3 SRAM diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 49fee9249bf..9ab92e699dc 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -75,8 +75,6 @@ /* test POST memory test */ #undef CONFIG_POST -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 /* * Config the L3 Cache as L3 SRAM diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 5bd5cd85c84..4d651264dd2 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -42,10 +42,8 @@ #define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE #define CONFIG_SPL_BSS_MAX_SIZE 0x1080000 /* memtest start addr */ -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) /* memtest will be run on 16MB */ -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index 894a8d7973f..15d6884ca5d 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -62,8 +62,6 @@ #endif /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/db-88f6281-bp.h b/include/configs/db-88f6281-bp.h index 749adb29075..cc51e6646ee 100644 --- a/include/configs/db-88f6281-bp.h +++ b/include/configs/db-88f6281-bp.h @@ -69,8 +69,6 @@ /* * Other required minimal configurations */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ -#define CONFIG_SYS_MEMTEST_END 0x007fffff /* (_8M - 1) */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ /* diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 4c0229e4cc8..f1f2be0797b 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -24,8 +24,6 @@ #define CONFIG_SYS_MALLOC_LEN SZ_1M #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_64M -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index baf1a73b956..21af126c4bd 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -138,9 +138,6 @@ #define CONFIG_BOOTCOMMAND "run autoboot" /* Boot Argument Buffer Size */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - 0x01000000) /* 16MB */ /* SRAM config */ #define CONFIG_SYS_SRAM_START 0x40200000 diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index e16c9ee01d9..efb3cfee352 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -137,9 +137,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x20000000 - /* Environment */ #endif /* __DH_IMX6_CONFIG_H */ diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 61c321c1320..d441f28d4af 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -54,8 +54,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x20000 -#define CONFIG_SYS_MEMTEST_START 0x100000 -#define CONFIG_SYS_MEMTEST_END 0x400000 /*#define CONFIG_SYS_DRAM_TEST 1 */ #undef CONFIG_SYS_DRAM_TEST diff --git a/include/configs/edison.h b/include/configs/edison.h index 3e174e9aa53..3918a9fc1c3 100644 --- a/include/configs/edison.h +++ b/include/configs/edison.h @@ -25,9 +25,6 @@ #define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x01000000 - /* Environment */ #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_MMC_ENV_PART 0 diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 60dfee81b71..cfee9740452 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -182,8 +182,6 @@ */ #define CONFIG_SYS_LOAD_ADDR 0x00800000 -#define CONFIG_SYS_MEMTEST_START 0x00400000 -#define CONFIG_SYS_MEMTEST_END 0x007fffff #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Enable command line editing */ diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index bd42ad259d9..fe63bcaaa62 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -74,9 +74,6 @@ #define CONFIG_ARP_TIMEOUT 200UL -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10800000 - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index bf51afbd9cd..24a0025eda3 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -49,9 +49,6 @@ #define CONFIG_ARP_TIMEOUT 200UL -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 39a4a066ad0..d121b395dfe 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -37,9 +37,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \ - - CONFIG_SYS_MALLOC_LEN) /* 512kB on-chip NOR flash */ # define CONFIG_SYS_MAX_FLASH_BANKS 1 diff --git a/include/configs/evb_ast2500.h b/include/configs/evb_ast2500.h index 7a0ea753be0..0ff01af833b 100644 --- a/include/configs/evb_ast2500.h +++ b/include/configs/evb_ast2500.h @@ -11,9 +11,6 @@ #include -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000) - #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE /* Memory Info */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 5911a8a6399..dff6a26f3b9 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -49,8 +49,6 @@ /* Boot Argument Buffer Size */ /* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) #define CONFIG_RD_LVL diff --git a/include/configs/flea3.h b/include/configs/flea3.h index fded5a11dac..02fedb1823f 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -79,9 +79,6 @@ /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x10000 - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index 6412efcbf88..261749db8d3 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -44,8 +44,6 @@ 230400, 460800, 921600 } /* RAM */ -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x80400000 /* Memory usage */ #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h index 6a7a93144bf..f8df0c8ceb4 100644 --- a/include/configs/gazerbeam.h +++ b/include/configs/gazerbeam.h @@ -20,8 +20,6 @@ * Memory test * TODO: Migrate! */ -#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x07e00000 /* * The reserved memory diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 2b55f51b8ba..e40be93ca78 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -144,9 +144,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Physical Memory Map */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 193c88e3da0..bf4b3b297ee 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -131,8 +131,6 @@ #define CONFIG_HWCONFIG /* Memory configuration */ -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 8d16e18d8b6..76add4eba8e 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -51,8 +51,6 @@ * The DRAM is already setup, so do not touch the DT node later. */ #define PHYS_SDRAM_1_SIZE (4089 << 20) -#define CONFIG_SYS_MEMTEST_START 0x100000 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1_SIZE - 0x100000) /* Environment data setup */ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 5d850929db0..bf1feb8708c 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -90,8 +90,6 @@ /* * Memory test */ -#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x07f00000 /* * The reserved memory diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index b96d4e82adf..3274ff64377 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -240,9 +240,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_MEMTEST_START 0x00001000 -#define CONFIG_SYS_MEMTEST_END 0x00C00000 - #define CONFIG_SYS_LOAD_ADDR 0x100000 #define CONFIG_LOADS_ECHO #define CONFIG_TIMESTAMP diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 82ac4242bbf..67fa4a5a09f 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -70,8 +70,6 @@ /* malloc() len */ #define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024) /* memtest start address */ -#define CONFIG_SYS_MEMTEST_START 0xA0000000 -#define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */ #define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index 18327fb4c3d..69b7f3378eb 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -104,8 +104,6 @@ #define CONFIG_BOOTCOMMAND "run $modeboot" /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index e77fb4a1b5e..63662dd18d4 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -116,9 +116,6 @@ #define CONFIG_ARP_TIMEOUT 200UL -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index b6e336a33d9..d4a613d0ada 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -70,8 +70,6 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 7da2b900529..5982522ecaf 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -123,9 +123,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) - #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR /* Monitor Command Prompt */ diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index ce73ca6b0ae..395ddf5816b 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -126,9 +126,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) - #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR /* Monitor Command Prompt */ diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index e91c71036d7..80e57389614 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -139,10 +139,6 @@ #define PHYS_SDRAM_2 0x100000000 #define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - (PHYS_SDRAM_SIZE >> 1)) - #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR /* Monitor Command Prompt */ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index ecf4c2e46b7..724d572c228 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -184,10 +184,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - (PHYS_SDRAM_SIZE >> 1)) - #define CONFIG_BAUDRATE 115200 #define CONFIG_MXC_UART diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index ac25549a183..b59641e37fc 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -163,9 +163,6 @@ /* LPDDR4 board total DDR is 6GB, DDR4 board total DDR is 4 GB */ #define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */ -#define CONFIG_SYS_MEMTEST_START 0xA0000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2)) - /* Serial */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h index 9223fc2cde9..89ab0da50cd 100644 --- a/include/configs/integrator-common.h +++ b/include/configs/integrator-common.h @@ -6,8 +6,6 @@ * Common ARM Integrator configuration settings */ -#define CONFIG_SYS_MEMTEST_START 0x100000 -#define CONFIG_SYS_MEMTEST_END 0x10000000 #define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ #define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */ diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index 84594874b88..fde84871787 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -16,10 +16,6 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 Byte write page */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ - -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ /* Reserve 4 MB for malloc */ diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 156edfba226..fa9d7b5dfa0 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -37,8 +37,6 @@ #include "asm/arch/config.h" -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ -#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ /* architecture specific default bootargs */ diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index cdfb280aeee..4d01f236c31 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -51,7 +51,7 @@ /* enable POST tests */ #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ -#define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END +#define CPM_POST_WORD_ADDR 0x00f00000 #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 9ceb12f7e00..0724df154e9 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -35,9 +35,6 @@ /* SCIF */ #define CONFIG_CONS_SCIF4 -#define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END \ - (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) #undef CONFIG_SYS_LOADS_BAUD_CHANGE #define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */ diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index 0bfa67a7c09..a5f7fab15e2 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -33,10 +33,8 @@ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ /* memtest start addr */ -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) /* memtest will be run on 16MB */ -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) /* * Serial Driver info diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index 4276e95dee2..d7ebfeda4c5 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -45,8 +45,6 @@ 230400, 460800, 921600 } /* RAM */ -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x80400000 /* Memory usage */ #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 6aba6a616ea..fa7d5896f58 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -104,8 +104,6 @@ "else run netboot; fi" /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_128M) #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index 5943b69716e..869e0ad6b82 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -13,8 +13,6 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 #define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff /* MMC */ #ifdef CONFIG_MMC @@ -33,8 +31,6 @@ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) #define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index 8a3ebf06f2d..54ea43420ff 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -14,8 +14,6 @@ #define CONFIG_SYS_SDRAM_SIZE 0x20000000 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff #ifndef CONFIG_SPL_BUILD #undef BOOT_TARGET_DEVICES @@ -73,7 +71,5 @@ #endif #define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff #endif /* __LS1012ARDB_H__ */ diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index 9e330582838..97d3eb2f3d3 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -22,8 +22,6 @@ #define SYS_SDRAM_SIZE_1024 0x40000000 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff /* ENV */ #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 @@ -120,8 +118,6 @@ "env exists secureboot && esbc_halt;" #endif #define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff #include diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index fb0d1ba6b27..99840dcfc4f 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -13,8 +13,6 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 #define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff /* * QIXIS Definitions @@ -107,8 +105,6 @@ #define CONFIG_PCI_SCAN_SHOW #define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff #include #endif /* __LS1012AQDS_H__ */ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 0738b243c43..c9d116d4d56 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -14,8 +14,6 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 #define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff /* ENV */ @@ -55,8 +53,6 @@ #define CONFIG_PCI_SCAN_SHOW #define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 0e1eff71d22..031bc6f172f 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -472,9 +472,6 @@ unsigned long get_board_ddr_clk(void); */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - #define CONFIG_SYS_LOAD_ADDR 0x82000000 #define CONFIG_LS102XA_STREAM_ID diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 45ce460dca2..cb56037a412 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -441,9 +441,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - #define CONFIG_SYS_LOAD_ADDR 0x82000000 #define CONFIG_LS102XA_STREAM_ID diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 32065c2925f..f9040e661d0 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -26,9 +26,6 @@ #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - /* * SMP Definitinos */ diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 5769dc43a93..95bf5fa1024 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -390,9 +390,6 @@ unsigned long get_board_ddr_clk(void); * Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_INIT_SP_OFFSET \ diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 9ff248cefad..ff0d5fad9c2 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -409,9 +409,6 @@ unsigned long get_board_ddr_clk(void); * Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_INIT_SP_OFFSET \ diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 301945fc8c7..3bfd1d2a86a 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -376,8 +376,6 @@ unsigned long get_board_ddr_clk(void); #endif #define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 7cb07048498..dec1ff9d7d4 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -278,8 +278,6 @@ #endif #define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index af6fc3ae7ae..6be88831f04 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -25,8 +25,6 @@ #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) -#define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x8ff00000 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) diff --git a/include/configs/malta.h b/include/configs/malta.h index d41b80c7dc2..773d7c23ed8 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -41,8 +41,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x01000000) -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x00800000) #define CONFIG_SYS_MALLOC_LEN (128 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 0aee1e1cf6b..ee942a48fc8 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -31,9 +31,6 @@ #define CONFIG_BOARD_LATE_INIT #define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) - /* MMC Configuration */ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h index 2dc3156b266..33172a6b97a 100644 --- a/include/configs/meerkat96.h +++ b/include/configs/meerkat96.h @@ -17,9 +17,6 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 9d6c3b83006..bd4bac7aab3 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -58,8 +58,6 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000) #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000) /* diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h index 2f90ab31757..8ddfc6f14d9 100644 --- a/include/configs/microchip_mpfs_icicle.h +++ b/include/configs/microchip_mpfs_icicle.h @@ -54,8 +54,6 @@ /* * memtest works on DRAM */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* When we use RAM as ENV */ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index cc58e806def..97578cdb823 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -105,8 +105,6 @@ /* * Memory test */ -#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x07f00000 /* * The reserved memory diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index a041ddb79bb..e3a00ed1cf4 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -59,8 +59,6 @@ * Other required minimal configurations */ #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ -#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ -#define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 024a9717087..24a83fdbbe0 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -38,8 +38,6 @@ * Other required minimal configurations */ #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ -#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ -#define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index b72a0a5b9ed..19b5b5b386e 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -39,8 +39,6 @@ * Other required minimal configurations */ #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ -#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ -#define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index 174f038be8e..683d442e75b 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -41,8 +41,6 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* Memory Test */ -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE/2) -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) /* Serial Info */ #define CONFIG_MXC_UART diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 4082a0bd642..f910d6199b2 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -71,8 +71,6 @@ */ /* memtest works on */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x80010000 /* default load address */ #define CONFIG_SYS_LOAD_ADDR 0x81000000 diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 222d13eb1fd..8f1213fd8af 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -93,9 +93,6 @@ * Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x10000 - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 10aa1bcd87c..182648a0f19 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -155,9 +155,6 @@ * Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x90000000 -#define CONFIG_SYS_MEMTEST_END 0x90010000 - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /*----------------------------------------------------------------------- diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index ff71435776a..b43be1c55c7 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -146,9 +146,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x70010000 - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Physical Memory Map */ diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index 0ebff26ba09..e0210047ff5 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -75,9 +75,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x70010000 - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Physical Memory Map */ diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index 2e687b9bdc0..ab02aa072ff 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -100,9 +100,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x70010000 - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Physical Memory Map */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 1798a92efc5..2e015ad9f89 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -142,9 +142,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x70010000 - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Physical Memory Map */ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 196eab05c26..c32f02635b6 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -121,9 +121,6 @@ #define CONFIG_SYS_MAXARGS 48 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x70010000 - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index 610e6e8a11f..b3322c639ce 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -92,9 +92,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x70010000 - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Physical Memory Map */ diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index 6fd87c2abcd..3d79a7e4376 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -18,8 +18,6 @@ #undef CONFIG_GENERIC_MMC #undef CONFIG_CMD_FUSE -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x20000000 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) #define CONFIG_MXC_UART diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index 7e6917b9670..ec2ac695158 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -102,8 +102,6 @@ #define CONFIG_ARP_TIMEOUT 200UL /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index b46367c8314..cb0253c306c 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -154,9 +154,6 @@ #define CONFIG_ARP_TIMEOUT 200UL -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 193931b91ba..d889c99d512 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -108,8 +108,6 @@ "else run netboot; fi" /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_512M) /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index 8ae1e0a2e63..03c0c88e505 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -103,8 +103,6 @@ "else run netboot; fi" /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_128M) /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index dc5e8184431..2c7db39c296 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -91,8 +91,6 @@ "else run netboot; fi" /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 3bff496bad2..8633756dd0e 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -123,8 +123,6 @@ "else run netboot; fi" /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 1bdd5779403..7927779cc84 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -134,8 +134,6 @@ "else run netboot; fi" /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 3d42d26aa49..7e3a5c7cf3b 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -131,8 +131,6 @@ "else run netboot; fi" /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index fa59748776d..7e1e8b02cb7 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -94,9 +94,6 @@ #include -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index f6e173d7d53..f7f94044794 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -49,13 +49,10 @@ /* Physical Memory Map */ #define PHYS_SDRAM 0x60000000 -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_LOADADDR 0x60800000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_512M) - #define CONFIG_EXTRA_ENV_SETTINGS \ "image=zImage\0" \ "console=ttyLP0\0" \ diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index c1b379bdeaf..9216b0948c0 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -53,13 +53,10 @@ #define PHYS_SDRAM 0x60000000 #define PHYS_SDRAM_SIZE SZ_1G -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_LOADADDR 0x60800000 -#define CONFIG_SYS_MEMTEST_END 0x9E000000 - #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ diff --git a/include/configs/mxs.h b/include/configs/mxs.h index e079f8035b8..325c3ee00ce 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -51,8 +51,6 @@ /* Memory sizes */ #define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ -#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ -#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ /* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */ #define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 5e09a783df2..a5ca5f9c4b2 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -130,8 +130,6 @@ BOOTENV /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index fd755bbceae..5d1c7bf8353 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -274,9 +274,6 @@ int rx51_kp_getc(struct stdio_dev *sdev); * Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000)/*31MB*/ - /* default load address */ #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) diff --git a/include/configs/novena.h b/include/configs/novena.h index 2b8419563c2..6f964e43076 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -44,9 +44,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x20000000 - #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) /* SPL */ diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 4044365328f..03229910b2f 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -29,8 +29,6 @@ #define CONFIG_TZSW_RESERVED_DRAM_SIZE CONFIG_SYS_MEM_TOP_HIDE /* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) #include diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index ddf6d790ab3..dd0ea2dbde2 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -178,9 +178,6 @@ /* Miscellaneous configurable options */ /* memtest works on */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ /* FLASH and environment organization */ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 04f37559cc9..9a5b9f297c6 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -140,9 +140,6 @@ "run nanddtsboot; " \ /* memtest works on */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ /* FLASH and environment organization */ #if defined(CONFIG_MTD_RAW_NAND) diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 211078464d9..ecf308e3819 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -48,9 +48,6 @@ BOOTENV \ /* memtest works on */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ #if defined(CONFIG_MTD_RAW_NAND) #define CONFIG_SYS_FLASH_BASE NAND_BASE diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index a4ba7dbcc56..24884b26fb9 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -110,9 +110,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1) /* memtest */ -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_2 + \ - 0x01F00000) /* 31MB */ /*----------------------------------------------------------------------- * FLASH and environment organization diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index aac7f182f25..58fa5ccfa3e 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -37,10 +37,8 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x1080000 /* memtest start addr */ -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) /* memtest will be run on 16MB */ -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ diff --git a/include/configs/origen.h b/include/configs/origen.h index ff9318a81b8..3bedc4784b7 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -20,8 +20,6 @@ #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ /* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) #define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index d59fd033bda..af278ded9a4 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -236,9 +236,6 @@ #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ #endif -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x1fffffff - #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index 6dc5039560e..e99b41cc884 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -54,9 +54,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_L2_CACHE #define CONFIG_BTB -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x1fffffff - #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 238b03f600e..2156da671b2 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -35,8 +35,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000) #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index d2459874706..6aa77f1f5e9 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -43,8 +43,6 @@ #endif /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000) #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index 290e652ec98..706a8a2a876 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -94,9 +94,6 @@ * memtest works on 8 MB in DRAM after skipping 32MB from * start addr of ram disk */ -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (64 << 20)) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ - + (8 * 1024 * 1024)) /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index d4d6ad2143f..0bfaaf784a6 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -141,9 +141,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80010000 -#define CONFIG_SYS_MEMTEST_END 0x87C00000 - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Physical memory map */ diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index 1a89c56f41a..73edd28f1a6 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -42,8 +42,6 @@ #define CONFIG_SYS_FDT_ADDR 0x89d00000 /* Memory Test */ -#define CONFIG_SYS_MEMTEST_START 0x88000000 -#define CONFIG_SYS_MEMTEST_END 0x88080000 /*---------------------------------------------------------------------- * Commands diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index 7cc55cb8d5f..27cbfe276da 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -30,9 +30,6 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) - /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR #define CONFIG_SUPPORT_EMMC_BOOT diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 27e83b47cd6..b0e2f6ce33a 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -112,9 +112,6 @@ #include -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + SZ_128M - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 4dc206566ef..9a987f41500 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -109,9 +109,6 @@ #include -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h index cb8338f3847..771fd8db97f 100644 --- a/include/configs/picosam9g45.h +++ b/include/configs/picosam9g45.h @@ -86,9 +86,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - #ifdef CONFIG_SYS_USE_MMC /* bootstrap + u-boot + env + linux in mmc */ diff --git a/include/configs/platinum.h b/include/configs/platinum.h index 210927f4de0..5e81c4568a1 100644 --- a/include/configs/platinum.h +++ b/include/configs/platinum.h @@ -88,10 +88,6 @@ /* Board startup config */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - PHYS_SDRAM_SIZE - (12 << 20)) - #define CONFIG_BOOTCOMMAND "run bootubi_scr" /* Miscellaneous configurable options */ diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index f958ceb3053..9a4bfd1e0ec 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -193,9 +193,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x22000000 -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - #undef CONFIG_SYS_USE_DATAFLASH_CS0 #undef CONFIG_SYS_USE_NANDFLASH #define CONFIG_SYS_USE_FLASH 1 diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 50d953a8e89..7f87edb42d3 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -222,9 +222,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - #define CONFIG_SYS_USE_FLASH 1 #undef CONFIG_SYS_USE_DATAFLASH #undef CONFIG_SYS_USE_NANDFLASH diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index 8c181e64afd..b0511beb8f9 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -59,9 +59,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - #ifdef CONFIG_NAND_BOOT /* bootstrap + u-boot + env in nandflash */ diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h index 56f009ad4e3..51177f44fee 100644 --- a/include/configs/presidio_asic.h +++ b/include/configs/presidio_asic.h @@ -27,9 +27,6 @@ #define GICD_BASE 0xf7011000 #define GICC_BASE 0xf7012000 -#define CONFIG_SYS_MEMTEST_START 0x05000000 -#define CONFIG_SYS_MEMTEST_END 0x0D000000 - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index 42a25623c37..4227a280c75 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -73,9 +73,6 @@ /* default load address */ #define CONFIG_SYS_LOAD_ADDR 0x81000000 -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x80800000 - /*----------------------------------------------------------------------- * FLASH and environment organization */ diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h index e4a78fbddad..801ba76b3ec 100644 --- a/include/configs/qemu-mips64.h +++ b/include/configs/qemu-mips64.h @@ -73,9 +73,6 @@ /* default load address */ #define CONFIG_SYS_LOAD_ADDR 0xffffffff81000000 -#define CONFIG_SYS_MEMTEST_START 0xffffffff80100000 -#define CONFIG_SYS_MEMTEST_END 0xffffffff80800000 - /*----------------------------------------------------------------------- * FLASH and environment organization */ diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 47fb1816932..cfbd472c821 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -24,9 +24,6 @@ #define CONFIG_ADDR_MAP #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - /* Needed to fill the ccsrbar pointer */ /* Virtual address to CCSRBAR */ diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index afa446f53a4..a8886251e01 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -17,9 +17,6 @@ #define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) - #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) /* Address of u-boot image in Flash */ #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h index b562308db8b..e32ab9d7aee 100644 --- a/include/configs/r7780mp.h +++ b/include/configs/r7780mp.h @@ -25,9 +25,6 @@ #define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) - /* Flash board support */ #define CONFIG_SYS_FLASH_BASE (0xA0000000) #ifdef CONFIG_SYS_R7780MP_OLD_FLASH diff --git a/include/configs/rpi.h b/include/configs/rpi.h index b53a4b65d0b..834f1cd2364 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -55,8 +55,6 @@ CONFIG_SYS_SDRAM_SIZE - \ GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MALLOC_LEN SZ_4M -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x00200000 #define CONFIG_LOADADDR 0x00200000 #ifdef CONFIG_ARM64 diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h index 53c94ed70e6..5b1504d2dfe 100644 --- a/include/configs/s32v234evb.h +++ b/include/configs/s32v234evb.h @@ -148,9 +148,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_MEMTEST_START (DDR_BASE_ADDR) -#define CONFIG_SYS_MEMTEST_END (DDR_BASE_ADDR + 0x7C00000) - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 20538df0252..620217f5288 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -147,8 +147,6 @@ #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ /* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000000) /* Goni has 3 banks of DRAM, but swap the bank */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index ec9abaf584e..5a80958739d 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -37,8 +37,6 @@ #define CONFIG_SYS_MONITOR_BASE 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) /* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */ diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 1c13055cdc0..7fda63f71a5 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -43,8 +43,6 @@ /* Memory things - we don't really want a memory test */ #define CONFIG_SYS_LOAD_ADDR 0x00000000 -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1000) #define CONFIG_SYS_FDT_LOAD_ADDR 0x100 #define CONFIG_PHYSMEM diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 9d655848388..55b9a3c1822 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -23,8 +23,6 @@ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00100000 /* * DDR Setup diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index ae2c0033d06..f5462549a52 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -73,8 +73,6 @@ #define CONFIG_ENABLE_36BIT_PHYS 1 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 #define CONFIG_SYS_CCSRBAR 0xe0000000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 011e5736e27..4ab364ae9a2 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -69,8 +69,6 @@ #endif #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 /* * Base addresses -- Note these are effective addresses where the diff --git a/include/configs/secomx6quq7.h b/include/configs/secomx6quq7.h index 20acc403634..b390c2fc52e 100644 --- a/include/configs/secomx6quq7.h +++ b/include/configs/secomx6quq7.h @@ -18,9 +18,6 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART2_BASE -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) - /* MMC Configuration */ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h index ff49b9c2171..7211a2afa68 100644 --- a/include/configs/sh7752evb.h +++ b/include/configs/sh7752evb.h @@ -22,9 +22,6 @@ /* SCIF */ #define CONFIG_CONS_SCIF2 1 -#define CONFIG_SYS_MEMTEST_START (SH7752EVB_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - 480 * 1024 * 1024) #undef CONFIG_SYS_LOADS_BAUD_CHANGE #define CONFIG_SYS_SDRAM_BASE (SH7752EVB_SDRAM_BASE) diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h index 74fb528d2e9..464a5524809 100644 --- a/include/configs/sh7753evb.h +++ b/include/configs/sh7753evb.h @@ -22,9 +22,6 @@ /* SCIF */ #define CONFIG_CONS_SCIF2 1 -#define CONFIG_SYS_MEMTEST_START (SH7753EVB_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - 480 * 1024 * 1024) #undef CONFIG_SYS_LOADS_BAUD_CHANGE #define CONFIG_SYS_SDRAM_BASE (SH7753EVB_SDRAM_BASE) diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h index 8f5c84207fe..ac6338cec1c 100644 --- a/include/configs/sh7757lcr.h +++ b/include/configs/sh7757lcr.h @@ -25,9 +25,6 @@ /* SCIF */ #define CONFIG_CONS_SCIF2 1 -#define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - 224 * 1024 * 1024) #undef CONFIG_SYS_LOADS_BAUD_CHANGE #define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE) diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h index 5122c8bf44f..b6644288063 100644 --- a/include/configs/sh7763rdp.h +++ b/include/configs/sh7763rdp.h @@ -26,8 +26,6 @@ /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE (0x8C000000) #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) /* Flash(NOR) */ #define CONFIG_SYS_FLASH_BASE (0xA0000000) diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index cab28766518..ed931176504 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -54,9 +54,6 @@ * memtest works on 8 MB in DRAM after skipping 32MB from * start addr of ram disk */ -#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024)) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ - + (8 * 1024 * 1024)) #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 624ad3b7688..aacdd1263e7 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -69,8 +69,6 @@ * Perform a SDRAM Memtest from the start of SDRAM * till the beginning of the U-Boot position in RAM. */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN \ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index dbdb9a4a07a..20d60636767 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -110,8 +110,6 @@ */ #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ /* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5e00000) #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */ diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 13e81ee2ffe..336571d4c4e 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -42,8 +42,6 @@ /* Miscellaneous configurable options */ #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" /* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) /* SMDKV310 has 4 bank of DRAM */ diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index b0408a55925..35cd7f69c1d 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -32,8 +32,6 @@ GENERATED_GBL_DATA_SIZE) /* Mem test settings */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024)) /* NAND Flash */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index ffcfdcaafcd..9b950543084 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -31,8 +31,6 @@ GENERATED_GBL_DATA_SIZE) /* Mem test settings */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024)) /* NAND Flash */ #define CONFIG_SYS_NAND_ECC_BASE ATMEL_BASE_ECC diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 410ec80618f..0579a00d40a 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -17,8 +17,6 @@ */ #define PHYS_SDRAM_1 0x0 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE #if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 87c73457a0a..61f7b254b59 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -117,8 +117,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define PHYS_SDRAM_1 0x0 #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) #define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_MEMTEST_START 0 -#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - 0x200000 /* * Serial / UART configurations diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 4fe67dced85..da60546966c 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -51,8 +51,6 @@ #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 -#define CONFIG_SYS_MEMTEST_END 0x00C00000 #define CONFIG_SYS_CCSRBAR 0xE0000000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index 6759f24c083..85c68cdee65 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -73,8 +73,6 @@ "fi" /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 85e498dc668..e74ba6cc34c 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -147,8 +147,6 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_SYS_MEMTEST_START 0x00800000 -#define CONFIG_SYS_MEMTEST_END 0x04000000 #define CONFIG_SYS_MALLOC_LEN (1024*1024) #define CONFIG_SYS_LOAD_ADDR 0x00800000 diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index cf04662328f..be5afe9c6fa 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -65,10 +65,6 @@ #define CONFIG_SPL_STACK (STM32_SYSRAM_BASE + \ STM32_SYSRAM_SIZE) #endif /* #ifdef CONFIG_SPL */ - -#define CONFIG_SYS_MEMTEST_START STM32_DDR_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_64M) - /*MMC SD*/ #define CONFIG_SYS_MMC_MAX_DEVICE 3 diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index 4df2750a896..b5bfac77f1b 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -103,8 +103,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) #define CONFIG_SYS_DRAM_TEST #if defined(CONFIG_CF_SBF) diff --git a/include/configs/strider.h b/include/configs/strider.h index 06a86bbc208..d5f710be592 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -90,8 +90,6 @@ /* * Memory test */ -#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x07f00000 /* * The reserved memory diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index 81e1e49c928..0058dcd4bba 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -35,9 +35,6 @@ /* Command support defines */ #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ -#define CONFIG_SYS_MEMTEST_START 0x0000 -#define CONFIG_SYS_MEMTEST_END 1024*1024 - /* Misc configuration */ #define CONFIG_BOOTCOMMAND "go 0x40040000" diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 5d087caf31e..976d527a088 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -45,9 +45,6 @@ #define CONFIG_ADDR_MAP #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - /* * Config the L3 Cache as L3 SRAM */ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index a2bb1b55eb1..c13e9979219 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -81,9 +81,6 @@ #define CONFIG_SYS_MAXARGS 32 /* max number of command */ /* args */ /* memtest works on */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ /* address */ diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index c80776b4da0..a283e1e0290 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -131,9 +131,7 @@ /* turn on command-line edit/hist/auto */ -#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ /* defaults */ -#define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ /* load address */ diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index b598fca1ecb..7376b91f550 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -30,10 +30,6 @@ #define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END \ - (CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024) - #define CONFIG_SYS_BOOTMAPSZ 0x10000000 /* Serial console */ diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index f2cdd9c0194..175c55c6138 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -52,9 +52,6 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) -#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) - /*----------------------------------------------------------------------- * Physical Memory Map */ diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index dac7e4ad959..4d3c58d1e8f 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -25,9 +25,6 @@ /* Generic Timer Definitions */ #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ -#define CONFIG_SYS_MEMTEST_START MEM_BASE -#define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE) - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index cc32729496f..99ddc3e923c 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -87,10 +87,6 @@ /* Console I/O Buffer Size */ #define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ - + PHYS_DRAM_1_SIZE - (8 << 12)) - #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default */ /** diff --git a/include/configs/titanium.h b/include/configs/titanium.h index d6ab5e4393e..ec316f325cf 100644 --- a/include/configs/titanium.h +++ b/include/configs/titanium.h @@ -47,9 +47,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (500 << 20)) - #define CONFIG_HOSTNAME "titanium" #define CONFIG_UBI_PART ubi #define CONFIG_UBIFS_VOLUME rootfs0 diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h index 73fdfae4610..0e4a824c424 100644 --- a/include/configs/topic_miami.h +++ b/include/configs/topic_miami.h @@ -36,10 +36,6 @@ /* FPGA commands that we don't use */ /* Extras */ -#undef CONFIG_SYS_MEMTEST_START -#define CONFIG_SYS_MEMTEST_START 0 -#undef CONFIG_SYS_MEMTEST_END -#define CONFIG_SYS_MEMTEST_END 0x18000000 /* Faster flash, ours may run at 108 MHz */ #undef CONFIG_SPI_FLASH_WINBOND diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index 8f13744c322..75e74580675 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -51,8 +51,6 @@ /* * Diagnostics */ -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x83f00000 #define CONFIG_CMD_MII diff --git a/include/configs/trats.h b/include/configs/trats.h index 37fadc52102..f39a7c726a2 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -27,8 +27,6 @@ #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ /* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) /* select serial console configuration */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 8b71c257573..f6593e227b9 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -25,8 +25,6 @@ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ /* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) /* select serial console configuration */ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index de6abb58377..83aa3cd4689 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -176,10 +176,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - 0x07000000) /* 112 MB */ - #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) /* diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h index 49bd6b53d2e..49279fca404 100644 --- a/include/configs/turris_mox.h +++ b/include/configs/turris_mox.h @@ -45,8 +45,6 @@ * Other required minimal configurations */ #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ -#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ -#define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ diff --git a/include/configs/udoo.h b/include/configs/udoo.h index bf9106e239f..163cbbb54ed 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -38,9 +38,6 @@ #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 6 -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) - /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index f4a2837b391..4b3df0451a9 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -60,8 +60,6 @@ #include /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index c0ba647d094..73bf2d19da6 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -73,9 +73,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x22000000 -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - /* bootstrap + u-boot + env + linux in dataflash on CS0 */ #define CONFIG_BOOTCOMMAND "nboot 21000000 0" #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 91c8b478b3a..fcf5c67dc89 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -91,9 +91,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -#define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x90000000 - #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) #endif /* __CONFIG_H */ diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index 6a2f80c2fb4..d5b2a785bcf 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -38,10 +38,6 @@ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_SDRAM_SIZE - SZ_4M) - #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_BOARD_EARLY_INIT_R diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 34726b94253..bdacd818853 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -23,8 +23,6 @@ * On-board devices * */ -#define CONFIG_SYS_MEMTEST_START 0x00001000 -#define CONFIG_SYS_MEMTEST_END 0x07000000 /* * Device configurations diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 82bff3608c5..ca528598f2f 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -102,10 +102,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - (PHYS_SDRAM_SIZE >> 1)) - /* UART */ #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 3d638970540..09cdd3dab5b 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -120,8 +120,6 @@ #endif /* Enable memtest */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) /* Initial environment variables */ #ifdef CONFIG_TARGET_VEXPRESS64_JUNO diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index e73658a9e6e..ca765579e82 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -111,9 +111,6 @@ #define SYS_ID V2M_SYSREGS #define CONFIG_REVISION_TAG 1 -#define CONFIG_SYS_MEMTEST_START V2M_BASE -#define CONFIG_SYS_MEMTEST_END 0x20000000 - #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_SYS_L2CACHE_OFF 1 diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index d52a5a7e833..739219e8f8b 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -162,9 +162,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80010000 -#define CONFIG_SYS_MEMTEST_END 0x87C00000 - /* Physical memory map */ #define PHYS_SDRAM (0x80000000) #define PHYS_SDRAM_SIZE (128 * 1024 * 1024) diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 7120aa64df6..c4db6f4b3c1 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -26,8 +26,6 @@ #include /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index f40c9002e59..c11507e5502 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -26,8 +26,6 @@ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00100000 /* * DDR Setup diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index 8100e4dca7b..5aa3ad8ddf2 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -37,8 +37,6 @@ #define CONFIG_CONS_INDEX 3 /* RAM */ -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x80400000 /* Memory usage */ #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index a65d23bbe80..9d2bd7b2782 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -29,9 +29,6 @@ #define CONFIG_LBA48 #endif -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) - /* MMC Configuration */ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/warp.h b/include/configs/warp.h index 68361a6199e..654f8349f4d 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -26,9 +26,6 @@ /* Watchdog */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_256M) - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 39c00480bd9..60a902b2c74 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -107,9 +107,6 @@ "fi; " \ "fi" -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/wb45n.h b/include/configs/wb45n.h index 36060975c10..fea07056b06 100644 --- a/include/configs/wb45n.h +++ b/include/configs/wb45n.h @@ -61,8 +61,6 @@ /* System */ #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x23e00000 #ifdef CONFIG_SYS_USE_NANDFLASH /* bootstrap + u-boot + env + linux in nandflash */ diff --git a/include/configs/wb50n.h b/include/configs/wb50n.h index ca1619f2511..bb4deeac9b7 100644 --- a/include/configs/wb50n.h +++ b/include/configs/wb50n.h @@ -44,9 +44,6 @@ (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) #endif -#define CONFIG_SYS_MEMTEST_START 0x21000000 -#define CONFIG_SYS_MEMTEST_END 0x22000000 - /* NAND flash */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 54d211ab664..421384d9ba5 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -29,8 +29,6 @@ #define CONFIG_SYS_MALLOC_LEN SZ_1M #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_128M -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) diff --git a/include/configs/x600.h b/include/configs/x600.h index 8b6caae7be7..0dd57227948 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -92,8 +92,6 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_SYS_MEMTEST_START 0x00800000 -#define CONFIG_SYS_MEMTEST_END 0x04000000 #define CONFIG_SYS_MALLOC_LEN (8 << 20) #define CONFIG_SYS_LOAD_ADDR 0x00800000 diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 329b270467e..016b797a534 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -61,8 +61,6 @@ */ #define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x01000000 #define CONFIG_SYS_LOAD_ADDR 0x20000000 /*----------------------------------------------------------------------- diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 480afd993bc..da640d6f14d 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -19,9 +19,6 @@ #define GICR_BASE 0xF9080000 -#define CONFIG_SYS_MEMTEST_START 0 -#define CONFIG_SYS_MEMTEST_END 1000 - #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 01e05200dfe..b744a91fa60 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -19,9 +19,6 @@ #define GICD_BASE 0xF9010000 #define GICC_BASE 0xF9020000 -#define CONFIG_SYS_MEMTEST_START 0 -#define CONFIG_SYS_MEMTEST_END 1000 - #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ diff --git a/include/configs/xilinx_zynqmp_r5.h b/include/configs/xilinx_zynqmp_r5.h index 327f0af3145..c6cf82e2445 100644 --- a/include/configs/xilinx_zynqmp_r5.h +++ b/include/configs/xilinx_zynqmp_r5.h @@ -37,8 +37,4 @@ #define CONFIG_SKIP_LOWLEVEL_INIT -/* 0x0 - 0x40 is used for placing exception vectors */ -#define CONFIG_SYS_MEMTEST_START 0x40 -#define CONFIG_SYS_MEMTEST_END 0x100 - #endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */ diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 634ee424099..6c9991fa039 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -76,8 +76,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * Diagnostics */ -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x20000000 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\ CONFIG_SYS_POST_I2C) /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */ diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index 0186aaa1027..c9bd369029d 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -52,8 +52,6 @@ /* * Diagnostics */ -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x20000000 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ CONFIG_SYS_POST_I2C) #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \ diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 5e027bebcab..6d847cb7939 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -67,8 +67,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* * Diagnostics */ -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x20000000 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ CONFIG_SYS_POST_I2C) /* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */ diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 611089cbb93..106269bae08 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -66,8 +66,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* * Diagnostics */ -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x20000000 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ CONFIG_SYS_POST_I2C) #define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 1bc46f6fb28..ba7fc84bf2f 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -31,8 +31,6 @@ #define CONFIG_SYS_I2C_SPEED 100000 /* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000) #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 8b73900130d..516a6089f6d 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -71,8 +71,6 @@ #define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10) /* Memory test is destructive so default must not overlap vectors or U-Boot*/ -#define CONFIG_SYS_MEMTEST_START MEMADDR(0x01000000) -#define CONFIG_SYS_MEMTEST_END MEMADDR(0x02000000) /* Load address for stand-alone applications. * MEMADDR cannot be used here, because the definition needs to be diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h index a8c6f0be10d..e76c5cbe6b8 100644 --- a/include/configs/zmx25.h +++ b/include/configs/zmx25.h @@ -91,9 +91,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024)) -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE) - /* * Size of malloc() pool diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index a93172b02cd..9e83e177752 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -219,9 +219,6 @@ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MEMTEST_START 0 -#define CONFIG_SYS_MEMTEST_END 0x1000 - #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index cb401d3bec1..741e9545e9c 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3075,8 +3075,6 @@ CONFIG_SYS_MECR_VAL CONFIG_SYS_MEMAC_LITTLE_ENDIAN CONFIG_SYS_MEMORY_BASE CONFIG_SYS_MEMORY_SIZE -CONFIG_SYS_MEMTEST_END -CONFIG_SYS_MEMTEST_START CONFIG_SYS_MEM_MAP CONFIG_SYS_MEM_RESERVE_SECURE CONFIG_SYS_MEM_SIZE From bf38cbf9a289c41a0db6697c280ede73340191e7 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Sun, 3 May 2020 22:27:00 +0800 Subject: [PATCH 231/237] sata: ahsata: Fix resource leak Fix coverity issue CID 3606684: Resource leak (RESOURCE_LEAK) leaked_storage: Variable uc_priv going out of scope leaks the storage it points to Signed-off-by: Ye Li Signed-off-by: Peng Fan Reviewed-by: Simon Glass --- drivers/ata/dwc_ahsata.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c index c2e28fe518e..a7752147928 100644 --- a/drivers/ata/dwc_ahsata.c +++ b/drivers/ata/dwc_ahsata.c @@ -847,6 +847,9 @@ static int ahci_init_one(int pdev) struct ahci_uc_priv *uc_priv = NULL; uc_priv = malloc(sizeof(struct ahci_uc_priv)); + if (!uc_priv) + return -ENOMEM; + memset(uc_priv, 0, sizeof(struct ahci_uc_priv)); uc_priv->dev = pdev; @@ -871,6 +874,8 @@ static int ahci_init_one(int pdev) return 0; err_out: + if (uc_priv) + free(uc_priv); return rc; } From 87e2cb530fc147676319b7c639e7ce138ddf385e Mon Sep 17 00:00:00 2001 From: Ye Li Date: Sun, 3 May 2020 22:27:01 +0800 Subject: [PATCH 232/237] sata: ahsata: Fix wrong operand for checking SERR DIAG_X Fix coverity issue CID 3261683: Wrong operator used (CONSTANT_EXPRESSION_RESULT) operator_confusion: ({...; __v;}) | 67108864 is always 1/true regardless of the values of its operand. This occurs as the logical operand of ! When DIAG_X is set, the PHY COMINIT signal is detected, so should use '&' to check whether it is set. Signed-off-by: Ye Li Signed-off-by: Peng Fan Reviewed-by: Simon Glass --- drivers/ata/dwc_ahsata.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c index a7752147928..4b37a023380 100644 --- a/drivers/ata/dwc_ahsata.c +++ b/drivers/ata/dwc_ahsata.c @@ -223,7 +223,7 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv) /* Wait for COMINIT bit 26 (DIAG_X) in SERR */ timeout = 1000; - while (!(readl(&port_mmio->serr) | SATA_PORT_SERR_DIAG_X) + while (!(readl(&port_mmio->serr) & SATA_PORT_SERR_DIAG_X) && --timeout) ; if (timeout <= 0) { From cdff6fba32db88943be2b04639ad6e7746a2be11 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Sun, 3 May 2020 22:27:02 +0800 Subject: [PATCH 233/237] sata: dwc_ahsata: Fix incorrect free Fix coverity issue CID 43665: Free of address-of expression (BAD_FREE) incorrect_free: free frees incorrect pointer pp. pp points the port array field of struct ahci_uc_priv, should not free it. Acked-by: Peng Fan Signed-off-by: Ye Li Signed-off-by: Peng Fan Reviewed-by: Simon Glass --- drivers/ata/dwc_ahsata.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c index 4b37a023380..82fbb50da62 100644 --- a/drivers/ata/dwc_ahsata.c +++ b/drivers/ata/dwc_ahsata.c @@ -450,7 +450,6 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024); if (!mem) { - free(pp); printf("No mem for table!\n"); return -ENOMEM; } From 6b6c620c824e10a03da3c617aa9f2c6486f7f57a Mon Sep 17 00:00:00 2001 From: Ye Li Date: Sun, 3 May 2020 22:27:03 +0800 Subject: [PATCH 234/237] sata: dwc_ahsata: Fix memory issue in reset_sata The reset_sata should reset the sata device info and free the probe_ent memory. Otherwise, it will cause memory leak if we init the sata again. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- drivers/ata/dwc_ahsata.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c index 82fbb50da62..2bc1de8b98a 100644 --- a/drivers/ata/dwc_ahsata.c +++ b/drivers/ata/dwc_ahsata.c @@ -918,6 +918,9 @@ int reset_sata(int dev) while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) udelay(100); + free(uc_priv); + memset(&sata_dev_desc[dev], 0, sizeof(struct blk_desc)); + return 0; } From 6d3524c2ad9f5b38cf759566c78e4761aeab4c97 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Fri, 27 Mar 2020 00:02:00 +0100 Subject: [PATCH 235/237] env/sf.c: honour CONFIG_SPL_SAVEENV Deciding whether to compile the env_sf_save() function based solely on CONFIG_SPL_BUILD is wrong: For U-Boot proper, it leads to a build warning in case CONFIG_CMD_SAVEENV=n (because the initialization of the .save member is guarded by CONFIG_CMD_SAVEENV, while the env_sf_save() function is built if !CONFIG_SPL_BUILD - and even without the CONFIG_CMD_SAVEENV guard, the env_save_ptr() macro would just expand to NULL, with no reference to env_sf_save visible to the compiler). And for SPL, when one selects CONFIG_SPL_SAVEENV, one obviously expects to actually be able to save the environment. The compiler warning can be fixed by using a " ? env_sf_save : NULL" construction instead of a macro that just eats its argument and expands to NULL. That way, if is false, env_sf_save gets eliminated as dead code, but the compiler still sees the reference to it. For , we can use CONFIG_IS_ENABLED(SAVEENV), which is true precisely: - For U-Boot proper, when CONFIG_CMD_SAVEENV is set (because CONFIG_SAVEENV is a hidden config symbol that gets set if and only if CONFIG_CMD_SAVEENV is set). - For SPL, when CONFIG_SPL_SAVEENV is set. As a bonus, this also removes quite a few preprocessor conditionals. This has been run-time tested on a mpc8309-derived board to verify that saving the environment does indeed work in SPL with these patches applied. Signed-off-by: Rasmus Villemoes --- env/sf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/env/sf.c b/env/sf.c index 22b70ad3197..64c57f2cdf9 100644 --- a/env/sf.c +++ b/env/sf.c @@ -305,7 +305,7 @@ U_BOOT_ENV_LOCATION(sf) = { .location = ENVL_SPI_FLASH, ENV_NAME("SPI Flash") .load = env_sf_load, - .save = ENV_SAVE_PTR(env_sf_save), + .save = CONFIG_IS_ENABLED(SAVEENV) ? ENV_SAVE_PTR(env_sf_save) : NULL, #if defined(INITENV) && (CONFIG_ENV_ADDR != 0x0) .init = env_sf_init, #endif From d0ba026bd22e4b1dfe918da8460bb418bc9f3217 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 6 May 2020 18:26:07 +0200 Subject: [PATCH 236/237] test: describe naming conventions for macro UNIT_TEST Strict naming conventions have to be followed for Python function generate_ut_subtest() to collect C unit tests to be executed via command 'ut'. Describe the requirements both on the C as well on the Python side. Signed-off-by: Heinrich Schuchardt Reviewed-by: Stephen Warren Reviewed-by: Simon Glass --- include/test/test.h | 24 +++++++++++++++++++++++- test/py/tests/test_ut.py | 17 ++++++++++++++++- 2 files changed, 39 insertions(+), 2 deletions(-) diff --git a/include/test/test.h b/include/test/test.h index 2a752110083..029288de880 100644 --- a/include/test/test.h +++ b/include/test/test.h @@ -41,7 +41,29 @@ struct unit_test { int flags; }; -/* Declare a new unit test */ +/** + * UNIT_TEST() - create linker generated list entry for unit a unit test + * + * The macro UNIT_TEST() is used to create a linker generated list entry. These + * list entries are enumerate tests that can be execute using the ut command. + * The list entries are used both by the implementation of the ut command as + * well as in a related Python test. + * + * For Python testing the subtests are collected in Python function + * generate_ut_subtest() by applying a regular expression to the lines of file + * u-boot.sym. The list entries have to follow strict naming conventions to be + * matched by the expression. + * + * Use UNIT_TEST(foo_test_bar, _flags, foo_test) for a test bar in test suite + * foo that can be executed via command 'ut foo bar' and is implemented in + * function foo_test_bar(). + * + * @_name: concatenation of name of the test suite, "_test_", and the name + * of the test + * @_flags: an integer field that can be evaluated by the test suite + * implementation + * @_suite: name of the test suite concatenated with "_test" + */ #define UNIT_TEST(_name, _flags, _suite) \ ll_entry_declare(struct unit_test, _name, _suite) = { \ .file = __FILE__, \ diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py index 6c7b8dd2b30..01c2b3ffa12 100644 --- a/test/py/tests/test_ut.py +++ b/test/py/tests/test_ut.py @@ -22,7 +22,22 @@ def test_ut_dm_init(u_boot_console): fh.write(data) def test_ut(u_boot_console, ut_subtest): - """Execute a "ut" subtest.""" + """Execute a "ut" subtest. + + The subtests are collected in function generate_ut_subtest() from linker + generated lists by applying a regular expression to the lines of file + u-boot.sym. The list entries are created using the C macro UNIT_TEST(). + + Strict naming conventions have to be followed to match the regular + expression. Use UNIT_TEST(foo_test_bar, _flags, foo_test) for a test bar in + test suite foo that can be executed via command 'ut foo bar' and is + implemented in C function foo_test_bar(). + + Args: + u_boot_console (ConsoleBase): U-Boot console + ut_subtest (str): test to be executed via command ut, e.g 'foo bar' to + execute command 'ut foo bar' + """ output = u_boot_console.run_command('ut ' + ut_subtest) assert output.endswith('Failures: 0') From be51c3ca088695e851daf38677d4a8f0fe666f77 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 6 May 2020 18:26:08 +0200 Subject: [PATCH 237/237] test: fix naming of test functions in the log test suite Both the nolog as well as the syslog tests were not found by Python function generate_ut_subtest() due to not following the nameing requirements imposed by the regular expression used to find linker generated list entries in file u-boot.sym. Adjust the naming of test functions. With the patch the following tests are executed successfully for sandbox_defconfig: test/py/tests/test_ut.py::test_ut[ut_log_syslog_debug] PASSED test/py/tests/test_ut.py::test_ut[ut_log_syslog_err] PASSED test/py/tests/test_ut.py::test_ut[ut_log_syslog_info] PASSED test/py/tests/test_ut.py::test_ut[ut_log_syslog_nodebug] PASSED test/py/tests/test_ut.py::test_ut[ut_log_syslog_notice] PASSED test/py/tests/test_ut.py::test_ut[ut_log_syslog_warning] PASSED The nolog tests are only executed if CONFIG_LOG=n and CONFIG_CONSOLE_RECORD=y. Reported-by: Simon Glass Signed-off-by: Heinrich Schuchardt --- test/log/nolog_test.c | 24 ++++++++++----------- test/log/syslog_test.c | 48 +++++++++++++++++++++--------------------- 2 files changed, 36 insertions(+), 36 deletions(-) diff --git a/test/log/nolog_test.c b/test/log/nolog_test.c index 84619521c91..c418ed07c9a 100644 --- a/test/log/nolog_test.c +++ b/test/log/nolog_test.c @@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; #define BUFFSIZE 32 -static int nolog_test_log_err(struct unit_test_state *uts) +static int log_test_nolog_err(struct unit_test_state *uts) { char buf[BUFFSIZE]; @@ -31,9 +31,9 @@ static int nolog_test_log_err(struct unit_test_state *uts) ut_assertok(ut_check_console_end(uts)); return 0; } -LOG_TEST(nolog_test_log_err); +LOG_TEST(log_test_nolog_err); -static int nolog_test_log_warning(struct unit_test_state *uts) +static int log_test_nolog_warning(struct unit_test_state *uts) { char buf[BUFFSIZE]; @@ -45,9 +45,9 @@ static int nolog_test_log_warning(struct unit_test_state *uts) ut_assertok(ut_check_console_end(uts)); return 0; } -LOG_TEST(nolog_test_log_warning); +LOG_TEST(log_test_nolog_warning); -static int nolog_test_log_notice(struct unit_test_state *uts) +static int log_test_nolog_notice(struct unit_test_state *uts) { char buf[BUFFSIZE]; @@ -59,9 +59,9 @@ static int nolog_test_log_notice(struct unit_test_state *uts) ut_assertok(ut_check_console_end(uts)); return 0; } -LOG_TEST(nolog_test_log_notice); +LOG_TEST(log_test_nolog_notice); -static int nolog_test_log_info(struct unit_test_state *uts) +static int log_test_nolog_info(struct unit_test_state *uts) { char buf[BUFFSIZE]; @@ -73,7 +73,7 @@ static int nolog_test_log_info(struct unit_test_state *uts) ut_assertok(ut_check_console_end(uts)); return 0; } -LOG_TEST(nolog_test_log_info); +LOG_TEST(log_test_nolog_info); #undef _DEBUG #define _DEBUG 0 @@ -90,7 +90,7 @@ static int nolog_test_nodebug(struct unit_test_state *uts) } LOG_TEST(nolog_test_nodebug); -static int nolog_test_log_nodebug(struct unit_test_state *uts) +static int log_test_nolog_nodebug(struct unit_test_state *uts) { char buf[BUFFSIZE]; @@ -102,7 +102,7 @@ static int nolog_test_log_nodebug(struct unit_test_state *uts) ut_assertok(ut_check_console_end(uts)); return 0; } -LOG_TEST(nolog_test_log_nodebug); +LOG_TEST(log_test_nolog_nodebug); #undef _DEBUG #define _DEBUG 1 @@ -120,7 +120,7 @@ static int nolog_test_debug(struct unit_test_state *uts) } LOG_TEST(nolog_test_debug); -static int nolog_test_log_debug(struct unit_test_state *uts) +static int log_test_nolog_debug(struct unit_test_state *uts) { char buf[BUFFSIZE]; @@ -132,4 +132,4 @@ static int nolog_test_log_debug(struct unit_test_state *uts) ut_assertok(ut_check_console_end(uts)); return 0; } -LOG_TEST(nolog_test_log_debug); +LOG_TEST(log_test_nolog_debug); diff --git a/test/log/syslog_test.c b/test/log/syslog_test.c index 6ca5760eac3..26536ebca79 100644 --- a/test/log/syslog_test.c +++ b/test/log/syslog_test.c @@ -92,12 +92,12 @@ static int sb_log_tx_handler(struct udevice *dev, void *packet, } /** - * syslog_test_log_err() - test log_err() function + * log_test_syslog_err() - test log_err() function * * @uts: unit test state * Return: 0 = success */ -static int syslog_test_log_err(struct unit_test_state *uts) +static int log_test_syslog_err(struct unit_test_state *uts) { int old_log_level = gd->default_log_level; struct sb_log_env env; @@ -106,7 +106,7 @@ static int syslog_test_log_err(struct unit_test_state *uts) gd->default_log_level = LOGL_INFO; env_set("ethact", "eth@10002000"); env_set("log_hostname", "sandbox"); - env.expected = "<3>sandbox uboot: syslog_test_log_err() " + env.expected = "<3>sandbox uboot: log_test_syslog_err() " "testing log_err\n"; env.uts = uts; sandbox_eth_set_tx_handler(0, sb_log_tx_handler); @@ -119,15 +119,15 @@ static int syslog_test_log_err(struct unit_test_state *uts) return 0; } -LOG_TEST(syslog_test_log_err); +LOG_TEST(log_test_syslog_err); /** - * syslog_test_log_warning() - test log_warning() function + * log_test_syslog_warning() - test log_warning() function * * @uts: unit test state * Return: 0 = success */ -static int syslog_test_log_warning(struct unit_test_state *uts) +static int log_test_syslog_warning(struct unit_test_state *uts) { int old_log_level = gd->default_log_level; struct sb_log_env env; @@ -136,7 +136,7 @@ static int syslog_test_log_warning(struct unit_test_state *uts) gd->default_log_level = LOGL_INFO; env_set("ethact", "eth@10002000"); env_set("log_hostname", "sandbox"); - env.expected = "<4>sandbox uboot: syslog_test_log_warning() " + env.expected = "<4>sandbox uboot: log_test_syslog_warning() " "testing log_warning\n"; env.uts = uts; sandbox_eth_set_tx_handler(0, sb_log_tx_handler); @@ -150,15 +150,15 @@ static int syslog_test_log_warning(struct unit_test_state *uts) return 0; } -LOG_TEST(syslog_test_log_warning); +LOG_TEST(log_test_syslog_warning); /** - * syslog_test_log_notice() - test log_notice() function + * log_test_syslog_notice() - test log_notice() function * * @uts: unit test state * Return: 0 = success */ -static int syslog_test_log_notice(struct unit_test_state *uts) +static int log_test_syslog_notice(struct unit_test_state *uts) { int old_log_level = gd->default_log_level; struct sb_log_env env; @@ -167,7 +167,7 @@ static int syslog_test_log_notice(struct unit_test_state *uts) gd->default_log_level = LOGL_INFO; env_set("ethact", "eth@10002000"); env_set("log_hostname", "sandbox"); - env.expected = "<5>sandbox uboot: syslog_test_log_notice() " + env.expected = "<5>sandbox uboot: log_test_syslog_notice() " "testing log_notice\n"; env.uts = uts; sandbox_eth_set_tx_handler(0, sb_log_tx_handler); @@ -181,15 +181,15 @@ static int syslog_test_log_notice(struct unit_test_state *uts) return 0; } -LOG_TEST(syslog_test_log_notice); +LOG_TEST(log_test_syslog_notice); /** - * syslog_test_log_info() - test log_info() function + * log_test_syslog_info() - test log_info() function * * @uts: unit test state * Return: 0 = success */ -static int syslog_test_log_info(struct unit_test_state *uts) +static int log_test_syslog_info(struct unit_test_state *uts) { int old_log_level = gd->default_log_level; struct sb_log_env env; @@ -198,7 +198,7 @@ static int syslog_test_log_info(struct unit_test_state *uts) gd->default_log_level = LOGL_INFO; env_set("ethact", "eth@10002000"); env_set("log_hostname", "sandbox"); - env.expected = "<6>sandbox uboot: syslog_test_log_info() " + env.expected = "<6>sandbox uboot: log_test_syslog_info() " "testing log_info\n"; env.uts = uts; sandbox_eth_set_tx_handler(0, sb_log_tx_handler); @@ -212,15 +212,15 @@ static int syslog_test_log_info(struct unit_test_state *uts) return 0; } -LOG_TEST(syslog_test_log_info); +LOG_TEST(log_test_syslog_info); /** - * syslog_test_log_debug() - test log_debug() function + * log_test_syslog_debug() - test log_debug() function * * @uts: unit test state * Return: 0 = success */ -static int syslog_test_log_debug(struct unit_test_state *uts) +static int log_test_syslog_debug(struct unit_test_state *uts) { int old_log_level = gd->default_log_level; struct sb_log_env env; @@ -229,7 +229,7 @@ static int syslog_test_log_debug(struct unit_test_state *uts) gd->default_log_level = LOGL_DEBUG; env_set("ethact", "eth@10002000"); env_set("log_hostname", "sandbox"); - env.expected = "<7>sandbox uboot: syslog_test_log_debug() " + env.expected = "<7>sandbox uboot: log_test_syslog_debug() " "testing log_debug\n"; env.uts = uts; sandbox_eth_set_tx_handler(0, sb_log_tx_handler); @@ -243,10 +243,10 @@ static int syslog_test_log_debug(struct unit_test_state *uts) return 0; } -LOG_TEST(syslog_test_log_debug); +LOG_TEST(log_test_syslog_debug); /** - * syslog_test_log_nodebug() - test logging level filter + * log_test_syslog_nodebug() - test logging level filter * * Verify that log_debug() does not lead to a log message if the logging level * is set to LOGL_INFO. @@ -254,7 +254,7 @@ LOG_TEST(syslog_test_log_debug); * @uts: unit test state * Return: 0 = success */ -static int syslog_test_log_nodebug(struct unit_test_state *uts) +static int log_test_syslog_nodebug(struct unit_test_state *uts) { int old_log_level = gd->default_log_level; struct sb_log_env env; @@ -263,7 +263,7 @@ static int syslog_test_log_nodebug(struct unit_test_state *uts) gd->default_log_level = LOGL_INFO; env_set("ethact", "eth@10002000"); env_set("log_hostname", "sandbox"); - env.expected = "<7>sandbox uboot: syslog_test_log_nodebug() " + env.expected = "<7>sandbox uboot: log_test_syslog_nodebug() " "testing log_debug\n"; env.uts = uts; sandbox_eth_set_tx_handler(0, sb_log_tx_handler); @@ -277,4 +277,4 @@ static int syslog_test_log_nodebug(struct unit_test_state *uts) return 0; } -LOG_TEST(syslog_test_log_nodebug); +LOG_TEST(log_test_syslog_nodebug);