- Various minor fixes for x86
This commit is contained in:
Tom Rini 2021-03-09 07:21:51 -05:00
commit b764bf21e6
5 changed files with 30 additions and 10 deletions

View File

@ -1001,6 +1001,28 @@ config PCIEX_LENGTH_128MB
config PCIEX_LENGTH_64MB config PCIEX_LENGTH_64MB
bool bool
config INTEL_SOC
bool
help
This is enabled on Intel SoCs that can support various advanced
features such as power management (requiring asm/arch/pm.h), system
agent (asm/arch/systemagent.h) and an I/O map for ACPI
(asm/arch/iomap.h).
This cannot be selected in a defconfig file. It must be enabled by a
'select' in the SoC's Kconfig.
if INTEL_SOC
config INTEL_ACPIGEN
bool "Support ACPI table generation for Intel SoCs"
depends on ACPIGEN
help
This option adds some functions used for programmatic generation of
ACPI tables on Intel SoCs. This provides features for writing CPU
information such as P states and T stages. Also included is a way
to create a GNVS table and set it up.
config INTEL_GMA_ACPI config INTEL_GMA_ACPI
bool "Generate ACPI table for Intel GMA graphics" bool "Generate ACPI table for Intel GMA graphics"
help help
@ -1023,4 +1045,6 @@ config INTEL_GMA_SWSMISCI
Select this option for Atom-based platforms which use the SWSMISCI Select this option for Atom-based platforms which use the SWSMISCI
register (0xe0) rather than the SWSCI register (0xe8). register (0xe0) rather than the SWSCI register (0xe8).
endif # INTEL_SOC
endmenu endmenu

View File

@ -9,6 +9,7 @@ config INTEL_APOLLOLAKE
select HAVE_FSP select HAVE_FSP
select ARCH_MISC_INIT select ARCH_MISC_INIT
select USE_CAR select USE_CAR
select INTEL_SOC
select INTEL_PMC select INTEL_PMC
select TPL_X86_TSC_TIMER_NATIVE select TPL_X86_TSC_TIMER_NATIVE
select SPL_PCH_SUPPORT select SPL_PCH_SUPPORT

View File

@ -53,7 +53,7 @@ int lpc_common_early_init(struct udevice *dev)
count = fdtdec_get_int_array_count(gd->fdt_blob, dev_of_offset(dev), count = fdtdec_get_int_array_count(gd->fdt_blob, dev_of_offset(dev),
"intel,gen-dec", (u32 *)values, "intel,gen-dec", (u32 *)values,
sizeof(values) / sizeof(u32)); sizeof(values) / (sizeof(u32)));
if (count < 0) if (count < 0)
return -EINVAL; return -EINVAL;

View File

@ -107,6 +107,10 @@ struct __packed acpi_global_nvs {
u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */ u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */
#endif #endif
}; };
#ifdef CONFIG_CHROMEOS
check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#else
check_member(acpi_global_nvs, unused2, GNVS_CHROMEOS_ACPI_OFFSET);
#endif
#endif /* _INTEL_GNVS_H_ */ #endif /* _INTEL_GNVS_H_ */

View File

@ -329,15 +329,6 @@ config ACPIGEN
things like generating device-specific tables and returning the ACPI things like generating device-specific tables and returning the ACPI
name of a device. name of a device.
config INTEL_ACPIGEN
bool "Support ACPI table generation for Intel SoCs"
depends on ACPIGEN
help
This option adds some functions used for programatic generation of
ACPI tables on Intel SoCs. This provides features for writing CPU
information such as P states and T stages. Also included is a way
to create a GNVS table and set it up.
config BOUNCE_BUFFER config BOUNCE_BUFFER
bool "Include bounce buffer API" bool "Include bounce buffer API"
help help