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gdsys: mpc8308: Migrate SYS_FPGA{0, 1}_{BASE, SIZE} to Kconfig

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Move CONFIG_SYS_FPGA0_BASE, CONFIG_SYS_FPGA0_SIZE, CONFIG_SYS_FPGA1_BASE, and
CONFIG_SYS_FPGA1_SIZE to Kconfig.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
This commit is contained in:
Mario Six 2019-03-29 10:18:08 +01:00
parent b12b545836
commit b335fb6d8c
3 changed files with 22 additions and 16 deletions
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22
board/gdsys/mpc8308/Kconfig
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@ -4,6 +4,28 @@ config GDSYS_LEGACY_OSD_CMDS
Use the 'osdw', 'osdp', and 'osdsize' legacy commands required by Use the 'osdw', 'osdp', and 'osdsize' legacy commands required by
gdsys devices. gdsys devices.
config SYS_FPGA0_BASE
hex
default E0600000
help
The base address of the first FPGA's register map.
config SYS_FPGA0_SIZE
hex
default 1
help
The base address of the first FPGA's register map.
config SYS_FPGA1_BASE
hex
help
The base address of the second FPGA's register map.
config SYS_FPGA1_SIZE
hex
help
The base address of the second FPGA's register map.
if TARGET_HRCON if TARGET_HRCON
config SYS_BOARD config SYS_BOARD

8
include/configs/hrcon.h
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@ -129,14 +129,6 @@
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
/*
* FPGA
*/
#define CONFIG_SYS_FPGA0_BASE 0xE0600000
#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
#define CONFIG_SYS_FPGA_DONE(k) 0x0010 #define CONFIG_SYS_FPGA_DONE(k) 0x0010
#define CONFIG_SYS_FPGA_COUNT 1 #define CONFIG_SYS_FPGA_COUNT 1

8
include/configs/strider.h
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@ -127,14 +127,6 @@
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
/*
* FPGA
*/
#define CONFIG_SYS_FPGA0_BASE 0xE0600000
#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
#define CONFIG_SYS_FPGA_DONE(k) 0x0010 #define CONFIG_SYS_FPGA_DONE(k) 0x0010
#define CONFIG_SYS_FPGA_COUNT 1 #define CONFIG_SYS_FPGA_COUNT 1