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net: xgmac: Augment mdio read/write with cl-45 format support

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Currently, clause-22 format is supported. This change adds
support for clause-45 format.

Signed-off-by: Nikunj Kela <nikunj.kela@sima.ai>
Reviewed-by: Boon Khai Ng <boon.khai.ng@altera.com>
Tested-by: Boon Khai Ng <boon.khai.ng@altera.com>
Reviewed-by: Boon Khai Ng <boon.khai.ng@altera.com>
Tested-by: Boon Khai Ng <boon.khai.ng@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
This commit is contained in:
Nikunj Kela 2025-08-28 21:12:32 -07:00 committed by Tien Fong Chee
parent 31bf4a1c30
commit b17c28488b
2 changed files with 41 additions and 20 deletions
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58
drivers/net/dwc_eth_xgmac.c
View File

@ -140,9 +140,34 @@ static int xgmac_mdio_wait_idle(struct xgmac_priv *xgmac)
XGMAC_TIMEOUT_100MS, true); XGMAC_TIMEOUT_100MS, true);
} }
static u32 xgmac_set_clause(struct xgmac_priv *xgmac, int mdio_addr, int mdio_devad,
int mdio_reg, bool is_c45)
{
u32 hw_addr;
u32 val;
if (is_c45) {
val = readl(&xgmac->mac_regs->mdio_clause_22_port);
val &= ~BIT(mdio_addr);
writel(val, &xgmac->mac_regs->mdio_clause_22_port);
hw_addr = (mdio_addr << XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) |
(mdio_reg & XGMAC_MAC_MDIO_REG_ADDR_C45P_MASK);
hw_addr |= mdio_devad << XGMAC_MAC_MDIO_ADDRESS_DA_SHIFT;
} else {
/* Set clause 22 format */
val = BIT(mdio_addr);
writel(val, &xgmac->mac_regs->mdio_clause_22_port);
hw_addr = (mdio_addr << XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) |
(mdio_reg & XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK);
}
return hw_addr;
}
static int xgmac_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, static int xgmac_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
int mdio_reg) int mdio_reg)
{ {
bool is_c45 = (mdio_devad != MDIO_DEVAD_NONE);
struct xgmac_priv *xgmac = bus->priv; struct xgmac_priv *xgmac = bus->priv;
u32 val; u32 val;
u32 hw_addr; u32 hw_addr;
@ -159,18 +184,15 @@ static int xgmac_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
return ret; return ret;
} }
/* Set clause 22 format */ hw_addr = xgmac_set_clause(xgmac, mdio_addr, mdio_devad, mdio_reg, is_c45);
val = BIT(mdio_addr);
writel(val, &xgmac->mac_regs->mdio_clause_22_port);
hw_addr = (mdio_addr << XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) |
(mdio_reg & XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK);
val = xgmac->config->config_mac_mdio << val = xgmac->config->config_mac_mdio <<
XGMAC_MAC_MDIO_ADDRESS_CR_SHIFT; XGMAC_MAC_MDIO_ADDRESS_CR_SHIFT;
val |= XGMAC_MAC_MDIO_ADDRESS_SADDR | if (!is_c45)
XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_READ | val |= XGMAC_MAC_MDIO_ADDRESS_SADDR;
val |= XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_READ |
XGMAC_MAC_MDIO_ADDRESS_SBUSY; XGMAC_MAC_MDIO_ADDRESS_SBUSY;
ret = xgmac_mdio_wait_idle(xgmac); ret = xgmac_mdio_wait_idle(xgmac);
@ -203,6 +225,7 @@ static int xgmac_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
static int xgmac_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, static int xgmac_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad,
int mdio_reg, u16 mdio_val) int mdio_reg, u16 mdio_val)
{ {
bool is_c45 = (mdio_devad != MDIO_DEVAD_NONE);
struct xgmac_priv *xgmac = bus->priv; struct xgmac_priv *xgmac = bus->priv;
u32 val; u32 val;
u32 hw_addr; u32 hw_addr;
@ -219,21 +242,18 @@ static int xgmac_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad,
return ret; return ret;
} }
/* Set clause 22 format */ hw_addr = xgmac_set_clause(xgmac, mdio_addr, mdio_devad, mdio_reg, is_c45);
val = BIT(mdio_addr);
writel(val, &xgmac->mac_regs->mdio_clause_22_port);
hw_addr = (mdio_addr << XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) |
(mdio_reg & XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK);
hw_addr |= (mdio_reg >> XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) <<
XGMAC_MAC_MDIO_ADDRESS_DA_SHIFT;
val = (xgmac->config->config_mac_mdio << val = (xgmac->config->config_mac_mdio <<
XGMAC_MAC_MDIO_ADDRESS_CR_SHIFT); XGMAC_MAC_MDIO_ADDRESS_CR_SHIFT);
val |= XGMAC_MAC_MDIO_ADDRESS_SADDR | if (!is_c45) {
mdio_val | XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_WRITE | hw_addr |= (mdio_reg >> XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) <<
XGMAC_MAC_MDIO_ADDRESS_DA_SHIFT;
val |= XGMAC_MAC_MDIO_ADDRESS_SADDR;
}
val |= mdio_val | XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_WRITE |
XGMAC_MAC_MDIO_ADDRESS_SBUSY; XGMAC_MAC_MDIO_ADDRESS_SBUSY;
ret = xgmac_mdio_wait_idle(xgmac); ret = xgmac_mdio_wait_idle(xgmac);

1
drivers/net/dwc_eth_xgmac.h
View File

@ -109,6 +109,7 @@ struct xgmac_mac_regs {
#define XGMAC_MAC_MDIO_ADDRESS_SBUSY BIT(22) #define XGMAC_MAC_MDIO_ADDRESS_SBUSY BIT(22)
#define XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK GENMASK(4, 0) #define XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK GENMASK(4, 0)
#define XGMAC_MAC_MDIO_DATA_GD_MASK GENMASK(15, 0) #define XGMAC_MAC_MDIO_DATA_GD_MASK GENMASK(15, 0)
#define XGMAC_MAC_MDIO_REG_ADDR_C45P_MASK GENMASK(15, 0)
/* MTL Registers */ /* MTL Registers */