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arm64: zynqmp: Sync gem clock nodes with mainline Linux

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Just fixing indentation and update year in Copyright.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michal Simek 2020-01-09 14:15:07 +01:00
parent b94a3c2ebe
commit b0f36d5ec1
1 changed files with 13 additions and 9 deletions
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22
arch/arm/dts/zynqmp-clk-ccf.dtsi
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@ -2,7 +2,7 @@
/* /*
* Clock specification for Xilinx ZynqMP * Clock specification for Xilinx ZynqMP
* *
* (C) Copyright 2017, Xilinx, Inc. * (C) Copyright 2017 - 2019, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@xilinx.com>
*/ */
@ -173,26 +173,30 @@
}; };
&gem0 { &gem0 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
<&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>; <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
<&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
}; };
&gem1 { &gem1 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>, clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
<&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>; <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
<&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
}; };
&gem2 { &gem2 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>, clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
<&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>; <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
<&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
}; };
&gem3 { &gem3 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>, clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
<&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>; <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
<&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
}; };