From afa8f076db3e4ff322455e4b13b796f39c30eb14 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sat, 10 Jan 2026 20:56:10 +0100 Subject: [PATCH] arm: armv8: Flush TLB before enabling MMU Commit 9ebdbbc43e5f ("arm: armv8: invalidate dcache entries on dcache_enable") broke Apple Silicon machines in certain scenarios. If the MMU is currently not enabled we need to flush the TLB before we enable it to prevent stale TLB entries from becoming active again. So move the __asm_invalidate_tlb_all() back immediately before the mmu_setup() call. Fixes: 9ebdbbc43e5f ("arm: armv8: invalidate dcache entries on dcache_enable") Signed-off-by: Mark Kettenis Reviewed-by: Ilias Apalodimas --- arch/arm/cpu/armv8/cache_v8.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 0309da6d397..39479df7b21 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -878,15 +878,16 @@ void flush_dcache_range(unsigned long start, unsigned long stop) void dcache_enable(void) { /* The data cache is not active unless the mmu is enabled */ - if (!mmu_status()) + if (!mmu_status()) { + __asm_invalidate_tlb_all(); mmu_setup(); + } /* Set up page tables only once (it is done also by mmu_setup()) */ if (!gd->arch.tlb_fillptr) setup_all_pgtables(); invalidate_dcache_all(); - __asm_invalidate_tlb_all(); set_sctlr(get_sctlr() | CR_C); }