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pinctrl: rockchip: Add support for RK3528
Add pinctrl driver for RK3528. Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with adjustments to use regmap_update_bits(). Signed-off-by: Steven Liu <steven.liu@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Steven Liu
Kever Yang
parent
5a7a856b13
commit
addf951c55
@ -14,6 +14,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o
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obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
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obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
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obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
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obj-$(CONFIG_ROCKCHIP_RK3528) += pinctrl-rk3528.o
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obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
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obj-$(CONFIG_ROCKCHIP_RK3588) += pinctrl-rk3588.o
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obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
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273
drivers/pinctrl/rockchip/pinctrl-rk3528.c
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273
drivers/pinctrl/rockchip/pinctrl-rk3528.c
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@ -0,0 +1,273 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*/
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <regmap.h>
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#include <syscon.h>
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#include "pinctrl-rockchip.h"
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#include <dt-bindings/pinctrl/rockchip.h>
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static int rk3528_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int iomux_num = (pin / 8);
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struct regmap *regmap;
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int reg, mask;
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u8 bit;
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u32 data, rmask;
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regmap = priv->regmap_base;
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reg = bank->iomux[iomux_num].offset;
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if ((pin % 8) >= 4)
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reg += 0x4;
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bit = (pin % 4) * 4;
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mask = 0xf;
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data = (mask << (bit + 16));
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rmask = data | (data >> 16);
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data |= (mux & mask) << bit;
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return regmap_update_bits(regmap, reg, rmask, data);
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}
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#define RK3528_DRV_BITS_PER_PIN 8
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#define RK3528_DRV_PINS_PER_REG 2
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#define RK3528_DRV_GPIO0_OFFSET 0x100
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#define RK3528_DRV_GPIO1_OFFSET 0x20120
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#define RK3528_DRV_GPIO2_OFFSET 0x30160
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#define RK3528_DRV_GPIO3_OFFSET 0x20190
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#define RK3528_DRV_GPIO4_OFFSET 0x101C0
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static void rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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*regmap = priv->regmap_base;
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if (bank->bank_num == 0) {
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*reg = RK3528_DRV_GPIO0_OFFSET;
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} else if (bank->bank_num == 1) {
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*reg = RK3528_DRV_GPIO1_OFFSET;
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} else if (bank->bank_num == 2) {
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*reg = RK3528_DRV_GPIO2_OFFSET;
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} else if (bank->bank_num == 3) {
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*reg = RK3528_DRV_GPIO3_OFFSET;
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} else if (bank->bank_num == 4) {
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*reg = RK3528_DRV_GPIO4_OFFSET;
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} else {
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*reg = 0;
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debug("unsupported bank_num %d\n", bank->bank_num);
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}
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*reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4);
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*bit = pin_num % RK3528_DRV_PINS_PER_REG;
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*bit *= RK3528_DRV_BITS_PER_PIN;
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}
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static int rk3528_set_drive(struct rockchip_pin_bank *bank,
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int pin_num, int strength)
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{
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struct regmap *regmap;
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int reg;
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u32 data, rmask;
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u8 bit;
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int drv = (1 << (strength + 1)) - 1;
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rk3528_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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/* enable the write to the equivalent lower bits */
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data = ((1 << RK3528_DRV_BITS_PER_PIN) - 1) << (bit + 16);
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rmask = data | (data >> 16);
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data |= (drv << bit);
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return regmap_update_bits(regmap, reg, rmask, data);
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}
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#define RK3528_PULL_BITS_PER_PIN 2
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#define RK3528_PULL_PINS_PER_REG 8
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#define RK3528_PULL_GPIO0_OFFSET 0x200
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#define RK3528_PULL_GPIO1_OFFSET 0x20210
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#define RK3528_PULL_GPIO2_OFFSET 0x30220
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#define RK3528_PULL_GPIO3_OFFSET 0x20230
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#define RK3528_PULL_GPIO4_OFFSET 0x10240
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static void rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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*regmap = priv->regmap_base;
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if (bank->bank_num == 0) {
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*reg = RK3528_PULL_GPIO0_OFFSET;
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} else if (bank->bank_num == 1) {
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*reg = RK3528_PULL_GPIO1_OFFSET;
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} else if (bank->bank_num == 2) {
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*reg = RK3528_PULL_GPIO2_OFFSET;
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} else if (bank->bank_num == 3) {
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*reg = RK3528_PULL_GPIO3_OFFSET;
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} else if (bank->bank_num == 4) {
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*reg = RK3528_PULL_GPIO4_OFFSET;
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} else {
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*reg = 0;
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debug("unsupported bank_num %d\n", bank->bank_num);
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}
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*reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4);
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*bit = pin_num % RK3528_PULL_PINS_PER_REG;
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*bit *= RK3528_PULL_BITS_PER_PIN;
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}
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static int rk3528_set_pull(struct rockchip_pin_bank *bank,
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int pin_num, int pull)
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{
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struct regmap *regmap;
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int reg, ret;
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u8 bit, type;
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u32 data, rmask;
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if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
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return -EOPNOTSUPP;
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rk3528_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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type = bank->pull_type[pin_num / 8];
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ret = rockchip_translate_pull_value(type, pull);
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if (ret < 0) {
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debug("unsupported pull setting %d\n", pull);
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return ret;
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}
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/* enable the write to the equivalent lower bits */
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data = ((1 << RK3528_PULL_BITS_PER_PIN) - 1) << (bit + 16);
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rmask = data | (data >> 16);
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data |= (ret << bit);
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return regmap_update_bits(regmap, reg, rmask, data);
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}
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#define RK3528_SMT_BITS_PER_PIN 1
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#define RK3528_SMT_PINS_PER_REG 8
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#define RK3528_SMT_GPIO0_OFFSET 0x400
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#define RK3528_SMT_GPIO1_OFFSET 0x20410
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#define RK3528_SMT_GPIO2_OFFSET 0x30420
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#define RK3528_SMT_GPIO3_OFFSET 0x20430
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#define RK3528_SMT_GPIO4_OFFSET 0x10440
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static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num,
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struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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*regmap = priv->regmap_base;
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if (bank->bank_num == 0) {
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*reg = RK3528_SMT_GPIO0_OFFSET;
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} else if (bank->bank_num == 1) {
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*reg = RK3528_SMT_GPIO1_OFFSET;
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} else if (bank->bank_num == 2) {
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*reg = RK3528_SMT_GPIO2_OFFSET;
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} else if (bank->bank_num == 3) {
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*reg = RK3528_SMT_GPIO3_OFFSET;
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} else if (bank->bank_num == 4) {
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*reg = RK3528_SMT_GPIO4_OFFSET;
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} else {
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*reg = 0;
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debug("unsupported bank_num %d\n", bank->bank_num);
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}
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*reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4);
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*bit = pin_num % RK3528_SMT_PINS_PER_REG;
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*bit *= RK3528_SMT_BITS_PER_PIN;
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return 0;
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}
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static int rk3528_set_schmitt(struct rockchip_pin_bank *bank,
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int pin_num, int enable)
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{
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struct regmap *regmap;
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int reg;
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u32 data, rmask;
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u8 bit;
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rk3528_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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/* enable the write to the equivalent lower bits */
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data = ((1 << RK3528_SMT_BITS_PER_PIN) - 1) << (bit + 16);
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rmask = data | (data >> 16);
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data |= (enable << bit);
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return regmap_update_bits(regmap, reg, rmask, data);
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}
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static struct rockchip_pin_bank rk3528_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0, 0, 0, 0),
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PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0x20020, 0x20028, 0x20030, 0x20038),
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PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0x30040, 0, 0, 0),
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PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0x20060, 0x20068, 0x20070, 0),
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PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0x10080, 0x10088, 0x10090, 0x10098),
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};
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static const struct rockchip_pin_ctrl rk3528_pin_ctrl = {
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.pin_banks = rk3528_pin_banks,
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.nr_banks = ARRAY_SIZE(rk3528_pin_banks),
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.grf_mux_offset = 0x0,
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.set_mux = rk3528_set_mux,
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.set_pull = rk3528_set_pull,
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.set_drive = rk3528_set_drive,
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.set_schmitt = rk3528_set_schmitt,
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};
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static const struct udevice_id rk3528_pinctrl_ids[] = {
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{
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.compatible = "rockchip,rk3528-pinctrl",
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.data = (ulong)&rk3528_pin_ctrl
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},
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{ }
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};
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U_BOOT_DRIVER(rockchip_rk3528_pinctrl) = {
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.name = "rockchip_rk3528_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = rk3528_pinctrl_ids,
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.priv_auto = sizeof(struct rockchip_pinctrl_priv),
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.ops = &rockchip_pinctrl_ops,
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#if CONFIG_IS_ENABLED(OF_REAL)
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.bind = dm_scan_fdt_dev,
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#endif
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.probe = rockchip_pinctrl_probe,
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};
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