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arm: dts: Use upstream dts for additional bcmbca devices

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Make use of OF_UPSTREAM which uses Linux dts.

Changes in v2:
- Removed enabling of nand functionality

Signed-off-by: david degan <dregan@broadcom.com>
Reviewed-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Anand Gore <anand.gore@broadcom.com>
This commit is contained in:
david regan 2025-01-13 20:54:23 -08:00 committed by Tom Rini
parent 6a0db9ee03
commit aba477ce0a
12 changed files with 9 additions and 472 deletions
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127
arch/arm/dts/bcm4908.dtsi
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@ -1,127 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/dts-v1/;
/ {
compatible = "brcm,bcm4908", "brcm,bcmbca";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "brcm,brahma-b53";
reg = <0x0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0xfff8>;
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "brcm,brahma-b53";
reg = <0x1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0xfff8>;
next-level-cache = <&l2>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "brcm,brahma-b53";
reg = <0x2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0xfff8>;
next-level-cache = <&l2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "brcm,brahma-b53";
reg = <0x3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0xfff8>;
next-level-cache = <&l2>;
};
l2: l2-cache0 {
compatible = "cache";
};
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x81000000 0x4000>;
gic: interrupt-controller@1000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x1000 0x1000>,
<0x2000 0x2000>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
clocks {
periph_clk: periph_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "periph";
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0xff800000 0x3000>;
uart0: serial@640 {
compatible = "brcm,bcm6345-uart";
reg = <0x640 0x18>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&periph_clk>;
clock-names = "refclk";
status = "disabled";
};
};
};

149
arch/arm/dts/bcm63138.dtsi
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@ -1,149 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Broadcom BCM63138 DSL SoCs Device Tree
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "brcm,bcm63138", "brcm,bcmbca";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0>;
enable-method = "brcm,bcm63138";
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <1>;
enable-method = "brcm,bcm63138";
};
};
clocks {
/* UBUS peripheral clock */
periph_clk: periph_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
clock-output-names = "periph";
};
/* peripheral clock for system timer */
axi_clk: axi_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&armpll>;
clock-div = <2>;
clock-mult = <1>;
};
/* APB bus clock */
apb_clk: apb_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&armpll>;
clock-div = <4>;
clock-mult = <1>;
};
};
/* ARM bus */
axi@80000000 {
compatible = "simple-bus";
ranges = <0 0x80000000 0x784000>;
#address-cells = <1>;
#size-cells = <1>;
L2: cache-controller@1d000 {
compatible = "arm,pl310-cache";
reg = <0x1d000 0x1000>;
cache-unified;
cache-level = <2>;
cache-size = <524288>;
cache-sets = <1024>;
cache-line-size = <32>;
interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
scu: scu@1e000 {
compatible = "arm,cortex-a9-scu";
reg = <0x1e000 0x100>;
};
gic: interrupt-controller@1f000 {
compatible = "arm,cortex-a9-gic";
reg = <0x1f000 0x1000
0x1e100 0x100>;
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
};
global_timer: timer@1e200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x1e200 0x20>;
interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
clocks = <&axi_clk>;
};
local_timer: local-timer@1e600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x1e600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_EDGE_RISING)>;
clocks = <&axi_clk>;
};
twd_watchdog: watchdog@1e620 {
compatible = "arm,cortex-a9-twd-wdt";
reg = <0x1e620 0x20>;
interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
};
armpll: armpll@20000 {
#clock-cells = <0>;
compatible = "brcm,bcm63138-armpll";
clocks = <&periph_clk>;
reg = <0x20000 0xf00>;
};
};
/* Legacy UBUS base */
bus@fffe8000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfffe8000 0x8000>;
timer0: timer@80 {
compatible = "brcm,bcmbca-periph-timer";
reg = <0x80 0x28>;
clocks = <&periph_clk>;
};
uart0: serial@600 {
compatible = "brcm,bcm6345-uart";
reg = <0x600 0x20>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&periph_clk>;
clock-names = "refclk";
status = "disabled";
};
};
};

103
arch/arm/dts/bcm63148.dtsi
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@ -1,103 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "brcm,bcm63148", "brcm,bcmbca";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
B15_0: cpu@0 {
device_type = "cpu";
compatible = "brcm,brahma-b15";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B15_1: cpu@1 {
device_type = "cpu";
compatible = "brcm,brahma-b15";
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu: pmu {
compatible = "arm,cortex-a15-pmu";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&B15_0>, <&B15_1>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@80030000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x80030000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfffe8000 0x8000>;
uart0: serial@600 {
compatible = "brcm,bcm6345-uart";
reg = <0x600 0x20>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&periph_clk>;
clock-names = "refclk";
status = "disabled";
};
};
};

30
arch/arm/dts/bcm94908.dts
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@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm4908.dtsi"
/ {
model = "Broadcom BCM94908 Reference Board";
compatible = "brcm,bcm94908", "brcm,bcm4908", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm963138.dts
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@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm63138.dtsi"
/ {
model = "Broadcom BCM963138 Reference Board";
compatible = "brcm,bcm963138", "brcm,bcm63138", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm963148.dts
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@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm63148.dtsi"
/ {
model = "Broadcom BCM963148 Reference Board";
compatible = "brcm,bcm963148", "brcm,bcm63148", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

1
arch/arm/mach-bcmbca/bcm4908/Kconfig
View File

@ -8,6 +8,7 @@ if BCM4908
config TARGET_BCM94908
bool "Broadcom 4908 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm4908"

1
arch/arm/mach-bcmbca/bcm63138/Kconfig
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@ -8,6 +8,7 @@ if BCM63138
config TARGET_BCM963138
bool "Broadcom 63138 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm63138"

1
arch/arm/mach-bcmbca/bcm63148/Kconfig
View File

@ -8,6 +8,7 @@ if BCM63148
config TARGET_BCM963148
bool "Broadcom 63148 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm63148"

3
configs/bcm94908_defconfig
View File

@ -9,7 +9,7 @@ CONFIG_TARGET_BCM94908=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm94908"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm94908"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM4908"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
@ -17,5 +17,6 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CACHE=y
CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y

3
configs/bcm963138_defconfig
View File

@ -8,7 +8,7 @@ CONFIG_TARGET_BCM963138=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm963138"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm963138"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM63138"
@ -17,5 +17,6 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CACHE=y
CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y

3
configs/bcm963148_defconfig
View File

@ -9,7 +9,7 @@ CONFIG_TARGET_BCM963148=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm963148"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm963148"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM63148"
@ -18,5 +18,6 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CACHE=y
CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y