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video: tegra: parametrize PCLK and DE polarity

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Configure pixel clock and data enable polarity according to panel flags.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
This commit is contained in:
Svyatoslav Ryhel 2025-04-18 09:12:03 +03:00
parent d564f395bc
commit aa291c5f8b
2 changed files with 19 additions and 0 deletions
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3
arch/arm/include/asm/arch-tegra/dc.h
View File

@ -448,6 +448,9 @@ enum win_color_depth_id {
#define LVS_OUTPUT_POLARITY_LOW BIT(28) #define LVS_OUTPUT_POLARITY_LOW BIT(28)
#define LSC0_OUTPUT_POLARITY_LOW BIT(24) #define LSC0_OUTPUT_POLARITY_LOW BIT(24)
/* DC_COM_PIN_OUTPUT_POLARITY3 0x309 */
#define LSPI_OUTPUT_POLARITY_LOW BIT(8)
/* DC_COM_PIN_OUTPUT_SELECT6 0x31a */ /* DC_COM_PIN_OUTPUT_SELECT6 0x31a */
#define LDC_OUTPUT_SELECT_V_PULSE1 BIT(14) /* 100b */ #define LDC_OUTPUT_SELECT_V_PULSE1 BIT(14) /* 100b */

16
drivers/video/tegra/dc.c
View File

@ -238,8 +238,24 @@ static void rgb_enable(struct tegra_lcd_priv *priv)
else else
value &= ~LVS_OUTPUT_POLARITY_LOW; value &= ~LVS_OUTPUT_POLARITY_LOW;
/* configure pixel data signal polarity */
if (dt->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
value &= ~LSC0_OUTPUT_POLARITY_LOW;
else
value |= LSC0_OUTPUT_POLARITY_LOW;
writel(value, &com->pin_output_polarity[1]); writel(value, &com->pin_output_polarity[1]);
/* configure data enable signal polarity */
value = readl(&com->pin_output_polarity[3]);
if (dt->flags & DISPLAY_FLAGS_DE_LOW)
value |= LSPI_OUTPUT_POLARITY_LOW;
else
value &= ~LSPI_OUTPUT_POLARITY_LOW;
writel(value, &com->pin_output_polarity[3]);
for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++) for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
writel(rgb_sel_tab[i], &com->pin_output_sel[i]); writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
} }