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	MPC512x: Add MSCAN1...4 Clock Control Registers
Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
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				@ -185,10 +185,11 @@ typedef struct clk512x {
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	u8 res0[4];
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	u32 bcr;		/* Bread Crumb Register */
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	u32 pscccr[12];		/* PSC0-11 Clock Control Registers */
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	u32 spccr;		/* SPDIF Clock Control Registers */
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	u32 cccr;		/* CFM Clock Control Registers */
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	u32 dccr;		/* DIU Clock Control Registers */
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	u8 res1[0xa8];
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	u32 spccr;		/* SPDIF Clock Control Register */
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	u32 cccr;		/* CFM Clock Control Register */
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	u32 dccr;		/* DIU Clock Control Register */
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	u32 msccr[4];		/* MSCAN1-4 Clock Control Registers */
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	u8 res1[0x98];
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} clk512x_t;
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/* SPMR - System PLL Mode Register */
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