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https://source.denx.de/u-boot/u-boot.git
synced 2025-10-14 00:51:24 +02:00
imx6: remove aristainetos board
remove not anymore used aristainetos board. Signed-off-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Heiko Schocher
Stefano Babic
parent
0b0c6af387
commit
a7e2dc9cf6
@ -125,9 +125,6 @@ config TARGET_APALIS_IMX6
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imply CMD_DM
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imply CMD_DM
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imply CMD_SATA
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imply CMD_SATA
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config TARGET_ARISTAINETOS
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bool "aristainetos"
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config TARGET_ARISTAINETOS2
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config TARGET_ARISTAINETOS2
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bool "aristainetos2"
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bool "aristainetos2"
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select BOARD_LATE_INIT
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select BOARD_LATE_INIT
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@ -1,13 +1,3 @@
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if TARGET_ARISTAINETOS
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config SYS_BOARD
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default "aristainetos"
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config SYS_CONFIG_NAME
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default "aristainetos"
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endif
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if TARGET_ARISTAINETOS2
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if TARGET_ARISTAINETOS2
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config SYS_BOARD
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config SYS_BOARD
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@ -2,8 +2,6 @@ ARISTAINETOS BOARD
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M: Heiko Schocher <hs@denx.de>
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M: Heiko Schocher <hs@denx.de>
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S: Maintained
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S: Maintained
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F: board/aristainetos/
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F: board/aristainetos/
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F: include/configs/aristainetos.h
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F: configs/aristainetos_defconfig
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F: include/configs/aristainetos2.h
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F: include/configs/aristainetos2.h
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F: configs/aristainetos2_defconfig
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F: configs/aristainetos2_defconfig
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F: configs/aristainetos2b_defconfig
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F: configs/aristainetos2b_defconfig
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@ -1,278 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2015
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* Based on:
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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*
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <linux/errno.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/mach-imx/video.h>
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#include <mmc.h>
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#include <fsl_esdhc_imx.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/crm_regs.h>
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#include <linux/fb.h>
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#include <ipu_pixfmt.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <pwm.h>
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struct i2c_pads_info i2c_pad_info3 = {
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.scl = {
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.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
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.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
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.gp = IMX_GPIO_NR(3, 17)
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},
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.sda = {
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.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
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.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
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.gp = IMX_GPIO_NR(3, 18)
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}
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};
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iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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iomux_v3_cfg_t const uart5_pads[] = {
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MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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iomux_v3_cfg_t const gpio_pads[] = {
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/* LED enable */
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MX6_PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* spi flash WP protect */
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MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* backlight enable */
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MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* LED yellow */
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MX6_PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* LED red */
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MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* LED green */
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MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* LED blue */
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MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* i2c4 scl */
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MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* i2c4 sda */
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MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* spi CS 1 */
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MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const misc_pads[] = {
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MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* OTG Power enable */
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MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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iomux_v3_cfg_t const enet_pads[] = {
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MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(0x4001b0a8),
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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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};
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static void setup_iomux_enet(void)
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{
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
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/* set GPIO_16 as ENET_REF_CLK_OUT */
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setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
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}
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static iomux_v3_cfg_t const backlight_pads[] = {
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MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_SD4_DAT1__PWM3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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iomux_v3_cfg_t const ecspi4_pads[] = {
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MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const display_pads[] = {
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MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
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MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
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MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
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MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
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MX6_PAD_DI0_PIN4__GPIO4_IO20,
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MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
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MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
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MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
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MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
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MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
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MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
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MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
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MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
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MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
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MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
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MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
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MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
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MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
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MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
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MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
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MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
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MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
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MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
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MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
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MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
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MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
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MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
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MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
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MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
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};
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int board_spi_cs_gpio(unsigned bus, unsigned cs)
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{
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return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
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? (IMX_GPIO_NR(3, 20)) : -1;
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}
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static void setup_spi(void)
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{
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int i;
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imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
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for (i = 0; i < 3; i++)
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enable_spi_clk(true, i);
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/* set cs1 to high */
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gpio_direction_output(ECSPI4_CS1, 1);
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}
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
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}
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int board_eth_init(bd_t *bis)
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{
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struct iomuxc *iomuxc_regs =
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(struct iomuxc *)IOMUXC_BASE_ADDR;
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int ret;
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/* clear gpr1[14], gpr1[18:17] to select anatop clock */
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clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
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ret = enable_fec_anatop_clock(0, ENET_50MHZ);
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if (ret)
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return ret;
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setup_iomux_enet();
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return cpu_eth_init(bis);
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}
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static void enable_lvds(struct display_info_t const *dev)
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{
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imx_iomux_v3_setup_multiple_pads(
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display_pads,
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ARRAY_SIZE(display_pads));
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imx_iomux_v3_setup_multiple_pads(
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backlight_pads,
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ARRAY_SIZE(backlight_pads));
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/* enable backlight PWM 3 */
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if (pwm_init(2, 0, 0))
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goto error;
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/* duty cycle 500ns, period: 3000ns */
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if (pwm_config(2, 500, 3000))
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goto error;
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if (pwm_enable(2))
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goto error;
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return;
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error:
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puts("error init pwm for backlight\n");
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return;
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}
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static void setup_display(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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int reg;
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enable_ipu_clock();
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reg = readl(&mxc_ccm->cs2cdr);
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/* select pll 5 clock */
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reg &= MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
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reg &= MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
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writel(reg, &mxc_ccm->cs2cdr);
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imx_iomux_v3_setup_multiple_pads(backlight_pads,
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ARRAY_SIZE(backlight_pads));
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}
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static void setup_iomux_gpio(void)
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{
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imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
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}
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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setup_iomux_gpio();
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setup_display();
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return 0;
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}
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static void setup_i2c4(void)
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{
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/* i2c4 not used, set it to gpio input */
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gpio_request(IMX_GPIO_NR(1, 7), "i2c4_scl");
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gpio_direction_input(IMX_GPIO_NR(1, 7));
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gpio_request(IMX_GPIO_NR(1, 8), "i2c4_sda");
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gpio_direction_input(IMX_GPIO_NR(1, 8));
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}
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static void setup_board_gpio(void)
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{
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/* enable LED */
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gpio_request(IMX_GPIO_NR(2, 13), "LED ena");
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gpio_direction_output(IMX_GPIO_NR(2, 13), 0);
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gpio_request(IMX_GPIO_NR(1, 3), "LED yellow");
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gpio_direction_output(IMX_GPIO_NR(1, 3), 1);
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gpio_request(IMX_GPIO_NR(1, 4), "LED red");
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gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
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gpio_request(IMX_GPIO_NR(1, 5), "LED green");
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gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
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gpio_request(IMX_GPIO_NR(1, 6), "LED blue");
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gpio_direction_output(IMX_GPIO_NR(1, 6), 1);
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}
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static void setup_board_spi(void)
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{
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}
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|
||||||
@ -58,9 +58,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||||||
|
|
||||||
#define ECSPI4_CS1 IMX_GPIO_NR(5, 2)
|
#define ECSPI4_CS1 IMX_GPIO_NR(5, 2)
|
||||||
|
|
||||||
#if (CONFIG_SYS_BOARD_VERSION == 1)
|
#if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
|
||||||
#include "./aristainetos-v1.c"
|
|
||||||
#elif ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
|
|
||||||
#include "./aristainetos-v2.c"
|
#include "./aristainetos-v2.c"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|||||||
@ -1,32 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
||||||
/*
|
|
||||||
* (C) Copyright 2014
|
|
||||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
|
||||||
*
|
|
||||||
* Based on:
|
|
||||||
* Copyright (C) 2013 Boundary Devices
|
|
||||||
*
|
|
||||||
* Refer doc/README.imximage for more details about how-to configure
|
|
||||||
* and create imximage boot image
|
|
||||||
*
|
|
||||||
* The syntax is taken as close as possible with the kwbimage
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* image version */
|
|
||||||
IMAGE_VERSION 2
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Boot Device : one of
|
|
||||||
* spi, sd
|
|
||||||
*/
|
|
||||||
BOOT_FROM spi
|
|
||||||
|
|
||||||
#define __ASSEMBLY__
|
|
||||||
#include <config.h>
|
|
||||||
#include "asm/arch/mx6-ddr.h"
|
|
||||||
#include "asm/arch/iomux.h"
|
|
||||||
#include "asm/arch/crm_regs.h"
|
|
||||||
|
|
||||||
#include "ddr-setup.cfg"
|
|
||||||
#include "mt41j128M.cfg"
|
|
||||||
#include "clocks.cfg"
|
|
||||||
@ -1,23 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
||||||
/*
|
|
||||||
* Copyright (C) 2013 Boundary Devices
|
|
||||||
*
|
|
||||||
* Device Configuration Data (DCD)
|
|
||||||
*
|
|
||||||
* Each entry must have the format:
|
|
||||||
* Addr-type Address Value
|
|
||||||
*
|
|
||||||
* where:
|
|
||||||
* Addr-type register length (1,2 or 4 bytes)
|
|
||||||
* Address absolute address of the register
|
|
||||||
* value value to be stored in the register
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* set the default clock gate to save power */
|
|
||||||
DATA 4, CCM_CCGR0, 0x00c03f3f
|
|
||||||
DATA 4, CCM_CCGR1, 0x0030fcff
|
|
||||||
DATA 4, CCM_CCGR2, 0x0fffcfc0
|
|
||||||
DATA 4, CCM_CCGR3, 0x3ff0300f
|
|
||||||
DATA 4, CCM_CCGR4, 0xfffff30c /* enable NAND/GPMI/BCH clocks */
|
|
||||||
DATA 4, CCM_CCGR5, 0x0f0000c3
|
|
||||||
DATA 4, CCM_CCGR6, 0x000003ff
|
|
||||||
@ -1,60 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
||||||
/*
|
|
||||||
* Copyright (C) 2013 Boundary Devices
|
|
||||||
*
|
|
||||||
* Device Configuration Data (DCD)
|
|
||||||
*
|
|
||||||
* Each entry must have the format:
|
|
||||||
* Addr-type Address Value
|
|
||||||
*
|
|
||||||
* where:
|
|
||||||
* Addr-type register length (1,2 or 4 bytes)
|
|
||||||
* Address absolute address of the register
|
|
||||||
* value value to be stored in the register
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* DDR IO TYPE */
|
|
||||||
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
|
|
||||||
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
|
|
||||||
/* Clock */
|
|
||||||
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
|
|
||||||
/* Address */
|
|
||||||
DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
|
|
||||||
/* Control */
|
|
||||||
DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
|
|
||||||
DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
|
|
||||||
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
|
|
||||||
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
|
|
||||||
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
|
|
||||||
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
|
|
||||||
/* Data Strobe */
|
|
||||||
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
|
|
||||||
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
|
|
||||||
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
|
|
||||||
DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
|
|
||||||
@ -1,69 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
||||||
/*
|
|
||||||
* Copyright (C) 2013 Boundary Devices
|
|
||||||
*/
|
|
||||||
/* ZQ Calibration */
|
|
||||||
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
|
|
||||||
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003
|
|
||||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
|
|
||||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
|
|
||||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
|
|
||||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
|
|
||||||
/*
|
|
||||||
* DQS gating, read delay, write delay calibration values
|
|
||||||
* based on calibration compare of 0x00ffff00
|
|
||||||
*/
|
|
||||||
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420E020E
|
|
||||||
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02000200
|
|
||||||
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42020202
|
|
||||||
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x01720172
|
|
||||||
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x494C4F4C
|
|
||||||
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4C4C49
|
|
||||||
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3133
|
|
||||||
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x39373F2E
|
|
||||||
/* read data bit delay */
|
|
||||||
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
|
|
||||||
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
|
|
||||||
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
|
|
||||||
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
|
|
||||||
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
|
|
||||||
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
|
|
||||||
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
|
|
||||||
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
|
|
||||||
/* Complete calibration by forced measurment */
|
|
||||||
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
|
|
||||||
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
|
|
||||||
/* in DDR3, 64-bit mode, only MMDC0 is initiated */
|
|
||||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
|
|
||||||
DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
|
|
||||||
DATA 4, MX6_MMDC_P0_MDCFG0, 0x40445323
|
|
||||||
DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8c63
|
|
||||||
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
|
|
||||||
DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
|
|
||||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
|
|
||||||
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
|
|
||||||
DATA 4, MX6_MMDC_P0_MDOR, 0x00440e21
|
|
||||||
DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
|
|
||||||
DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
|
|
||||||
/* MR2 */
|
|
||||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
|
|
||||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x0400803a
|
|
||||||
/* MR3 */
|
|
||||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
|
|
||||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b
|
|
||||||
/* MR1 */
|
|
||||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
|
|
||||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
|
|
||||||
/* MR0 */
|
|
||||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x07208030
|
|
||||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x07208038
|
|
||||||
/* ZQ calibration */
|
|
||||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
|
|
||||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
|
|
||||||
/* final ddr setup */
|
|
||||||
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
|
|
||||||
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
|
|
||||||
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000007
|
|
||||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
|
|
||||||
DATA 4, MX6_MMDC_P1_MAPSR, 0x00011006
|
|
||||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
|
|
||||||
@ -1,69 +0,0 @@
|
|||||||
CONFIG_ARM=y
|
|
||||||
CONFIG_ARCH_MX6=y
|
|
||||||
CONFIG_SYS_TEXT_BASE=0x17800000
|
|
||||||
CONFIG_TARGET_ARISTAINETOS=y
|
|
||||||
CONFIG_ENV_SIZE=0x3000
|
|
||||||
CONFIG_ENV_OFFSET=0xD0000
|
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
|
||||||
CONFIG_ENV_SECT_SIZE=0x10000
|
|
||||||
CONFIG_FIT=y
|
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL"
|
|
||||||
CONFIG_BOOTDELAY=3
|
|
||||||
# CONFIG_CONSOLE_MUX is not set
|
|
||||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
|
||||||
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
|
|
||||||
CONFIG_SUPPORT_RAW_INITRD=y
|
|
||||||
CONFIG_BOUNCE_BUFFER=y
|
|
||||||
CONFIG_BOARD_EARLY_INIT_F=y
|
|
||||||
CONFIG_HUSH_PARSER=y
|
|
||||||
CONFIG_CMD_BOOTZ=y
|
|
||||||
# CONFIG_CMD_FLASH is not set
|
|
||||||
CONFIG_CMD_GPIO=y
|
|
||||||
CONFIG_CMD_I2C=y
|
|
||||||
CONFIG_CMD_MMC=y
|
|
||||||
CONFIG_CMD_NAND_TRIMFFS=y
|
|
||||||
CONFIG_CMD_SF=y
|
|
||||||
CONFIG_CMD_USB=y
|
|
||||||
CONFIG_CMD_DHCP=y
|
|
||||||
CONFIG_CMD_MII=y
|
|
||||||
CONFIG_CMD_PING=y
|
|
||||||
CONFIG_CMD_BMP=y
|
|
||||||
CONFIG_CMD_CACHE=y
|
|
||||||
CONFIG_CMD_DATE=y
|
|
||||||
CONFIG_CMD_EXT2=y
|
|
||||||
CONFIG_CMD_EXT4=y
|
|
||||||
CONFIG_CMD_EXT4_WRITE=y
|
|
||||||
CONFIG_CMD_FAT=y
|
|
||||||
CONFIG_CMD_FS_GENERIC=y
|
|
||||||
CONFIG_CMD_MTDPARTS=y
|
|
||||||
CONFIG_CMD_UBI=y
|
|
||||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
|
||||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
|
||||||
CONFIG_ENV_OFFSET_REDUND=0xE0000
|
|
||||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
|
||||||
CONFIG_FSL_USDHC=y
|
|
||||||
CONFIG_MTD=y
|
|
||||||
CONFIG_MTD_RAW_NAND=y
|
|
||||||
CONFIG_NAND_MXS=y
|
|
||||||
CONFIG_SPI_FLASH=y
|
|
||||||
CONFIG_SF_DEFAULT_BUS=3
|
|
||||||
CONFIG_SF_DEFAULT_MODE=0
|
|
||||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
|
||||||
CONFIG_SPI_FLASH_STMICRO=y
|
|
||||||
CONFIG_SPI_FLASH_MTD=y
|
|
||||||
CONFIG_MTD_UBI_FASTMAP=y
|
|
||||||
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
|
|
||||||
CONFIG_PHYLIB=y
|
|
||||||
CONFIG_PHY_MICREL=y
|
|
||||||
CONFIG_PHY_MICREL_KSZ8XXX=y
|
|
||||||
CONFIG_MII=y
|
|
||||||
CONFIG_PWM_IMX=y
|
|
||||||
CONFIG_SPI=y
|
|
||||||
CONFIG_MXC_SPI=y
|
|
||||||
CONFIG_USB=y
|
|
||||||
CONFIG_USB_STORAGE=y
|
|
||||||
CONFIG_VIDEO_IPUV3=y
|
|
||||||
CONFIG_VIDEO=y
|
|
||||||
# CONFIG_VIDEO_SW_CURSOR is not set
|
|
||||||
CONFIG_IMX_WATCHDOG=y
|
|
||||||
CONFIG_OF_LIBFDT=y
|
|
||||||
@ -1,43 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
||||||
/*
|
|
||||||
* (C) Copyright 2015
|
|
||||||
* (C) Copyright 2014
|
|
||||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
|
||||||
*
|
|
||||||
* Based on:
|
|
||||||
* Copyright (C) 2012 Freescale Semiconductor, Inc.
|
|
||||||
*
|
|
||||||
* Configuration settings for the Freescale i.MX6Q SabreSD board.
|
|
||||||
*/
|
|
||||||
#ifndef __ARISTAINETOS_CONFIG_H
|
|
||||||
#define __ARISTAINETOS_CONFIG_H
|
|
||||||
|
|
||||||
#define CONFIG_SYS_BOARD_VERSION 1
|
|
||||||
#define CONFIG_HOSTNAME "aristainetos"
|
|
||||||
#define CONFIG_BOARDNAME "aristainetos"
|
|
||||||
|
|
||||||
#define CONFIG_MXC_UART_BASE UART5_BASE
|
|
||||||
#define CONSOLE_DEV "ttymxc4"
|
|
||||||
|
|
||||||
#define CONFIG_FEC_XCV_TYPE RMII
|
|
||||||
|
|
||||||
#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
|
|
||||||
"board_type=aristainetos7@1\0" \
|
|
||||||
"mtdids=nand0=gpmi-nand,nor0=spi3.0\0" \
|
|
||||||
"mtdparts=mtdparts=spi3.0:832k(u-boot),64k(env),64k(env-red)," \
|
|
||||||
"-(rescue-system);gpmi-nand:-(ubi)\0" \
|
|
||||||
"addmisc=setenv bootargs ${bootargs} consoleblank=0\0" \
|
|
||||||
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
|
|
||||||
"ubiargs=setenv bootargs console=${console},${baudrate} " \
|
|
||||||
"ubi.mtd=0,2048 root=ubi0:rootfs rootfstype=ubifs\0 " \
|
|
||||||
"ubifs_load_fit=sf probe;ubi part ubi 2048;ubifsmount ubi:rootfs;" \
|
|
||||||
"ubifsload ${fit_addr_r} /boot/system.itb; " \
|
|
||||||
"imi ${fit_addr_r}\0 "
|
|
||||||
|
|
||||||
#define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15)
|
|
||||||
#define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(3, 31)
|
|
||||||
#define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15)
|
|
||||||
|
|
||||||
#include "aristainetos-common.h"
|
|
||||||
|
|
||||||
#endif /* __ARISTAINETOS_CONFIG_H */
|
|
||||||
Loading…
x
Reference in New Issue
Block a user