From ebdc27895492e740d96c67d624821cfeb56c7544 Mon Sep 17 00:00:00 2001 From: Alex Nemirovsky Date: Mon, 23 Dec 2019 20:19:20 +0000 Subject: [PATCH 1/6] MIPS: allow override of flush_dcache_range() Useful in custom HW designs which have a need to flush dcache range in a completely non standard way. Signed-off-by: Alex Nemirovsky --- arch/mips/lib/cache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index 502956d050c..1a8c87d0943 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -141,7 +141,7 @@ ops_done: instruction_hazard_barrier(); } -void flush_dcache_range(ulong start_addr, ulong stop) +void __weak flush_dcache_range(ulong start_addr, ulong stop) { unsigned long lsize = dcache_line_size(); unsigned long slsize = scache_line_size(); From 47a1933aa738851ffde5770316ab0f8b47db753a Mon Sep 17 00:00:00 2001 From: Alex Nemirovsky Date: Mon, 23 Dec 2019 20:53:56 +0000 Subject: [PATCH 2/6] MIPS: allow override of get_tbclk() Allow SoC or board layers with reconfigurable cpu clocks capabilties to do implementation specific lookups and service get_tbclk() requests. Signed-off-by: Alex Nemirovsky --- arch/mips/cpu/time.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/cpu/time.c b/arch/mips/cpu/time.c index a1508e3b886..e0c1868b8c2 100644 --- a/arch/mips/cpu/time.c +++ b/arch/mips/cpu/time.c @@ -13,7 +13,7 @@ unsigned long notrace timer_read_counter(void) return read_c0_count(); } -ulong notrace get_tbclk(void) +ulong notrace __weak get_tbclk(void) { return CONFIG_SYS_MIPS_TIMER_FREQ; } From bfaa54f912196bfab6e0ba8878893cc8506566db Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 1 Jan 2020 08:34:03 +0100 Subject: [PATCH 3/6] doc: board: qemu-mips.rst: fix code examples Code sections should be syntax highlighted as bash. Comment lines in code should start with a hash sign ('#') but code lines should not. Most commands can be executed as normal users. Prepend those commands requiring elevated authorization with 'sudo'. dd does not have a parameter cout. sfdisk does not have a -C parameter on Debian Buster. Provide the necessary input to sfdisk. Creating a partition of length zero makes no sense. Signed-off-by: Heinrich Schuchardt --- doc/board/emulation/qemu-mips.rst | 108 +++++++++++++++++------------- 1 file changed, 60 insertions(+), 48 deletions(-) diff --git a/doc/board/emulation/qemu-mips.rst b/doc/board/emulation/qemu-mips.rst index 529a908b55b..f206039f548 100644 --- a/doc/board/emulation/qemu-mips.rst +++ b/doc/board/emulation/qemu-mips.rst @@ -25,37 +25,45 @@ Example usage Using u-boot.bin as ROM (replaces Qemu monitor): -32 bit, big endian:: +32 bit, big endian - # make qemu_mips - # qemu-system-mips -M mips -bios u-boot.bin -nographic +.. code-block:: bash -32 bit, little endian:: + make qemu_mips + qemu-system-mips -M mips -bios u-boot.bin -nographic - # make qemu_mipsel - # qemu-system-mipsel -M mips -bios u-boot.bin -nographic +32 bit, little endian -64 bit, big endian:: +.. code-block:: bash - # make qemu_mips64 - # qemu-system-mips64 -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic + make qemu_mipsel + qemu-system-mipsel -M mips -bios u-boot.bin -nographic -64 bit, little endian:: +64 bit, big endian - # make qemu_mips64el - # qemu-system-mips64el -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic +.. code-block:: bash + + make qemu_mips64 + qemu-system-mips64 -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic + +64 bit, little endian + +.. code-block:: bash + + make qemu_mips64el + qemu-system-mips64el -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic or using u-boot.bin from emulated flash: -if you use a qemu version after commit 4224 +if you use a QEMU version after commit 4224 -.. code-block:: none +.. code-block:: bash - create image: - # dd of=flash bs=1k count=4k if=/dev/zero - # dd of=flash bs=1k conv=notrunc if=u-boot.bin - start it (see above): - # qemu-system-mips[64][el] [-cpu MIPS64R2-generic] -M mips -pflash flash -nographic + # create image: + dd of=flash bs=1k count=4k if=/dev/zero + dd of=flash bs=1k conv=notrunc if=u-boot.bin + # start it (see above): + qemu-system-mips[64][el] [-cpu MIPS64R2-generic] -M mips -pflash flash -nographic Download kernel + initrd ^^^^^^^^^^^^^^^^^^^^^^^^ @@ -75,61 +83,63 @@ you can downland:: Generate uImage ^^^^^^^^^^^^^^^ -.. code-block:: none +.. code-block:: bash - # tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage + tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage Copy uImage to Flash ^^^^^^^^^^^^^^^^^^^^ -.. code-block:: none +.. code-block:: bash - # dd if=uImage bs=1k conv=notrunc seek=224 of=flash + dd if=uImage bs=1k conv=notrunc seek=224 of=flash Generate Ide Disk ^^^^^^^^^^^^^^^^^ -.. code-block:: none +.. code-block:: bash - # dd of=ide bs=1k cout=100k if=/dev/zero + dd of=ide bs=1k count=100k if=/dev/zero - # sfdisk -C 261 -d ide - # partition table of ide + # Create partion table + sudo sfdisk ide << EOF + label: dos + label-id: 0x6fe3a999 + device: image unit: sectors - - ide1 : start= 63, size= 32067, Id=83 - ide2 : start= 32130, size= 32130, Id=83 - ide3 : start= 64260, size= 4128705, Id=83 - ide4 : start= 0, size= 0, Id= 0 + image1 : start= 63, size= 32067, Id=83 + image2 : start= 32130, size= 32130, Id=83 + image3 : start= 64260, size= 4128705, Id=83 + EOF Copy to ide ^^^^^^^^^^^ -.. code-block:: none +.. code-block:: bash - # dd if=uImage bs=512 conv=notrunc seek=63 of=ide + dd if=uImage bs=512 conv=notrunc seek=63 of=ide Generate ext2 on part 2 on Copy uImage and initrd.gz ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -.. code-block:: none +.. code-block:: bash # Attached as loop device ide offset = 32130 * 512 - # losetup -o 16450560 -f ide + sudo losetup -o 16450560 /dev/loop0 ide # Format as ext2 ( arg2 : nb blocks) - # mke2fs /dev/loop0 16065 - # losetup -d /dev/loop0 + sudo mkfs.ext2 /dev/loop0 16065 + sudo losetup -d /dev/loop0 # Mount and copy uImage and initrd.gz to it - # mount -o loop,offset=16450560 -t ext2 ide /mnt - # mkdir /mnt/boot - # cp {initrd.gz,uImage} /mnt/boot/ + sudo mount -o loop,offset=16450560 -t ext2 ide /mnt + sudo mkdir /mnt/boot + cp {initrd.gz,uImage} /mnt/boot/ # Umount it - # umount /mnt + sudo umount /mnt Set Environment ^^^^^^^^^^^^^^^ -.. code-block:: none +.. code-block:: bash setenv rd_start 0x80800000 setenv rd_size 2663940 @@ -157,9 +167,11 @@ Set Environment setenv addmisc 'setenv bootargs ${bootargs} console=ttyS0,${baudrate} rd_start=${rd_start} rd_size=${rd_size} ethaddr=${ethaddr}' setenv bootcmd 'run boot_tftp_flash' -Now you can boot from flash, ide, ide+ext2 and tfp:: +Now you can boot from flash, ide, ide+ext2 and tfp - # qemu-system-mips -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide +.. code-block:: bash + + qemu-system-mips -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide How to debug U-Boot @@ -168,9 +180,9 @@ How to debug U-Boot In order to debug U-Boot you need to start qemu with gdb server support (-s) and waiting the connection to start the CPU (-S) -.. code-block:: none +.. code-block:: bash - # qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide + qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide in an other console you start gdb @@ -182,7 +194,7 @@ by connecting to the gdb server localhost:1234 .. code-block:: none - # mipsel-unknown-linux-gnu-gdb u-boot + $ mipsel-unknown-linux-gnu-gdb u-boot GNU gdb 6.6 Copyright (C) 2006 Free Software Foundation, Inc. GDB is free software, covered by the GNU General Public License, and you are From ea148789318c8152acb0a3974d4a8342dbd6b901 Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Thu, 6 Feb 2020 10:43:18 +0100 Subject: [PATCH 4/6] mips: vcoreiii: Ajust CONFIG_SYS_MEMTEST_END This patch ajust CONFIG_SYS_MEMTEST_END for vcoreiii-based systems to avoid overwriting the relocated u-boot. The former setting was too agressive with networking etc. enabled on some platforms. Reviewed-by: Alexandre Belloni Reviewed-by: Horatiu Vultur Signed-off-by: Lars Povlsen --- include/configs/vcoreiii.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index e69456ef7ce..6a2f80c2fb4 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -39,7 +39,8 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - SZ_1M) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_SDRAM_SIZE - SZ_4M) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE From 7048bb13b2d6309ef8386fca665247d3afa36ab0 Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Thu, 6 Feb 2020 10:45:40 +0100 Subject: [PATCH 5/6] mips: vcoreiii: Fix cache coherency issues This patch fixes an stability issue seen on some vcoreiii targets, which was root caused to a cache inconsistency situation. The inconsistency was caused by having kuseg pointing to NOR area but used as a stack/gd/heap area during initialization, while only relatively late remapping the RAM area into kuseg position. The fix is to initialize the DDR right after the TLB setup, and then remapping it into position before gd/stack/heap usage. Reported-by: Ramin Seyed-Moussavi Reviewed-by: Alexandre Belloni Reviewed-by: Horatiu Vultur Signed-off-by: Lars Povlsen --- arch/mips/mach-mscc/cpu.c | 9 +++++---- arch/mips/mach-mscc/dram.c | 14 +++++--------- arch/mips/mach-mscc/include/mach/ddr.h | 4 ---- arch/mips/mach-mscc/lowlevel_init.S | 17 ++++++++++++++++- 4 files changed, 26 insertions(+), 18 deletions(-) diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c index ac75d51da5f..3ee589891b1 100644 --- a/arch/mips/mach-mscc/cpu.c +++ b/arch/mips/mach-mscc/cpu.c @@ -7,6 +7,7 @@ #include #include +#include #include #include @@ -53,7 +54,6 @@ void vcoreiii_tlb_init(void) MMU_REGIO_RW); #endif -#if CONFIG_SYS_TEXT_BASE == MSCC_FLASH_TO /* * If U-Boot is located in NOR then we want to be able to use * the data cache in order to boot in a decent duration @@ -71,9 +71,10 @@ void vcoreiii_tlb_init(void) create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, MSCC_ATTRIB2); - /* Enable caches by clearing the bit ERL, which is set on reset */ - write_c0_status(read_c0_status() & ~BIT(2)); -#endif /* CONFIG_SYS_TEXT_BASE */ + /* Enable mapping (using TLB) kuseg by clearing the bit ERL, + * which is set on reset. + */ + write_c0_status(read_c0_status() & ~ST0_ERL); } int mach_cpu_init(void) diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c index c43f7a585bf..72c70c9e843 100644 --- a/arch/mips/mach-mscc/dram.c +++ b/arch/mips/mach-mscc/dram.c @@ -31,7 +31,7 @@ static inline int vcoreiii_train_bytelane(void) int vcoreiii_ddr_init(void) { - int res; + register int res; if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) & ICPU_MEMCTRL_STAT_INIT_DONE)) { @@ -40,20 +40,19 @@ int vcoreiii_ddr_init(void) if (hal_vcoreiii_init_dqs() || vcoreiii_train_bytelane()) hal_vcoreiii_ddr_failed(); } -#if (CONFIG_SYS_TEXT_BASE != 0x20000000) + res = dram_check(); if (res == 0) hal_vcoreiii_ddr_verified(); else hal_vcoreiii_ddr_failed(); - /* Clear boot-mode and read-back to activate/verify */ + /* Remap DDR to kuseg: Clear boot-mode */ clrbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, ICPU_GENERAL_CTRL_BOOT_MODE_ENA); + /* - and read-back to activate/verify */ readl(BASE_CFG + ICPU_GENERAL_CTRL); -#else - res = 0; -#endif + return res; } @@ -66,9 +65,6 @@ int print_cpuinfo(void) int dram_init(void) { - while (vcoreiii_ddr_init()) - ; - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; return 0; } diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h index d1f4287f654..bf75e52ec3c 100644 --- a/arch/mips/mach-mscc/include/mach/ddr.h +++ b/arch/mips/mach-mscc/include/mach/ddr.h @@ -435,16 +435,12 @@ static inline void hal_vcoreiii_ddr_failed(void) reset = KSEG0ADDR(_machine_restart); icache_lock((void *)reset, 128); asm volatile ("jr %0"::"r" (reset)); - - panic("DDR init failed\n"); } #else /* JR2 || ServalT */ static inline void hal_vcoreiii_ddr_failed(void) { writel(0, BASE_CFG + ICPU_RESET); writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST); - - panic("DDR init failed\n"); } #endif diff --git a/arch/mips/mach-mscc/lowlevel_init.S b/arch/mips/mach-mscc/lowlevel_init.S index dfbe06766cd..91f29ae252c 100644 --- a/arch/mips/mach-mscc/lowlevel_init.S +++ b/arch/mips/mach-mscc/lowlevel_init.S @@ -8,6 +8,7 @@ .set noreorder .extern vcoreiii_tlb_init + .extern vcoreiii_ddr_init #ifdef CONFIG_SOC_LUTON .extern pll_init #endif @@ -17,14 +18,28 @@ LEAF(lowlevel_init) * As we have no stack yet, we can assume the restricted * luxury of the sX-registers without saving them */ - move s0,ra + + /* Modify ra/s0 such we return to physical NOR location */ + li t0, 0x0fffffff + li t1, CONFIG_SYS_TEXT_BASE + and s0, ra, t0 + add s0, s0, t1 jal vcoreiii_tlb_init nop + #ifdef CONFIG_SOC_LUTON jal pll_init nop #endif + + /* Initialize DDR controller to enable stack/gd/heap */ +0: + jal vcoreiii_ddr_init + nop + bnez v0, 0b /* Retry on error */ + nop + jr s0 nop END(lowlevel_init) From fb9acad30562177287d8cffec19e5dfa6f072de7 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 13 Feb 2020 07:04:00 +0100 Subject: [PATCH 6/6] mips: cmd: go: Flush cache before jumping to app/image It has been noticed on MT7628/88 platforms, that booting the RAM image does not work reliably. Sometimes it works and sometimes not. Debugging showed that this "might" be a cache related issue as very strange errors occurred (e.g. output corrupted etc). This patch adds a cache flush for the complete SDRAM area to the go cmd before jumping to the entry point for the MIPS architecture. The complete area is flushed as we don't know at this point, how big the area of the "application" really is. Signed-off-by: Stefan Roese Reviewed-by: Daniel Schwierzeck Tested-by: Mauro Condarelli Cc: Daniel Schwierzeck Cc: Mauro Condarelli Cc: Weijie Gao --- arch/mips/lib/Makefile | 1 + arch/mips/lib/boot.c | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 arch/mips/lib/boot.c diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 589bc651f94..24a72d9c973 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -11,5 +11,6 @@ obj-y += stack.o obj-y += traps.o obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_CMD_GO) += boot.o lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o diff --git a/arch/mips/lib/boot.c b/arch/mips/lib/boot.c new file mode 100644 index 00000000000..db862f63792 --- /dev/null +++ b/arch/mips/lib/boot.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Stefan Roese + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +unsigned long do_go_exec(ulong (*entry)(int, char * const []), + int argc, char * const argv[]) +{ + /* + * Flush cache before jumping to application. Let's flush the + * whole SDRAM area, since we don't know the size of the image + * that was loaded. + */ + flush_cache(gd->bd->bi_memstart, gd->ram_top - gd->bd->bi_memstart); + + return entry(argc, argv); +}