mirrors/u-boot
1
0
Fork 0
mirror of https://source.denx.de/u-boot/u-boot.git synced 2025-12-20 17:01:50 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity

ARM: stm32: Limit early cache enablement in SPL to STM32MP15xx

Browse Source 
The STM32MP13xx SRAM size is half that the SRAM size on STM32MP15xx,
disable early dcache start on STM32MP13xx as the TLB itself takes
about a quarter of the SPL size. The dcache will be enabled later,
once DRAM is available and TLB can be placed in DRAM.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
This commit is contained in:
Marek Vasut 2025-06-30 02:10:29 +02:00 committed by Patrice Chotard
parent b87ebbe87c
commit a36e87127a
2 changed files with 8 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm/mach-stm32mp/stm32mp1/cpu.c
View File

@ -28,7 +28,9 @@
* early TLB into the .data section so that it not get cleared
* with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
*/
#if (!IS_ENABLED(CONFIG_XPL_BUILD) || !IS_ENABLED(CONFIG_STM32MP13X))
u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
#endif
u32 get_bootmode(void)
{
@ -95,8 +97,8 @@ void dram_bank_mmu_setup(int bank)
*/
static void early_enable_caches(void)
{
#if (!IS_ENABLED(CONFIG_XPL_BUILD) || !IS_ENABLED(CONFIG_STM32MP13X))
/* I-cache is already enabled in start.S: cpu_init_cp15 */
if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
return;
@ -107,6 +109,7 @@ static void early_enable_caches(void)
/* enable MMU (default configuration) */
dcache_enable();
#endif
}
/*

3
arch/arm/mach-stm32mp/stm32mp1/spl.c
View File

@ -220,10 +220,11 @@ void board_init_f(ulong dummy)
* activate cache on DDR only when DDR is fully initialized
* to avoid speculative access and issue in get_ram_size()
*/
if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !IS_ENABLED(CONFIG_STM32MP13X)) {
mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
CONFIG_DDR_CACHEABLE_SIZE,
DCACHE_DEFAULT_OPTION);
}
}
void spl_board_prepare_for_boot(void)