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drivers: use dev_read_addr_ptr when cast to pointer

Browse Source 
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_ptr instead of the dev_read_addr function in the
various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Johan Jonker 2023-03-13 01:32:04 +01:00 committed by Kever Yang
parent e5822ecba2
commit a12a73b664
47 changed files with 75 additions and 75 deletions
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4
arch/arm/mach-mvebu/system-controller.c
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@ -71,8 +71,8 @@ static int mvebu_reset_of_to_plat(struct udevice *dev)
{ {
struct mvebu_reset_data *data = dev_get_priv(dev); struct mvebu_reset_data *data = dev_get_priv(dev);
data->base = (void *)dev_read_addr(dev); data->base = dev_read_addr_ptr(dev);
if ((fdt_addr_t)data->base == FDT_ADDR_T_NONE) if (!data->base)
return -EINVAL; return -EINVAL;
return 0; return 0;

2
doc/develop/driver-model/livetree.rst
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@ -103,7 +103,7 @@ The new code is:
struct udevice *bus; struct udevice *bus;
i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev); i2c_bus->regs = dev_read_addr_ptr(dev);
plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", 500000); plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", 500000);
The dev_read\_...() interface is more convenient and works with both the The dev_read\_...() interface is more convenient and works with both the

2
drivers/ata/dwc_ahsata.c
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@ -912,7 +912,7 @@ int dwc_ahsata_probe(struct udevice *dev)
#endif #endif
uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI; ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev); uc_priv->mmio_base = dev_read_addr_ptr(dev);
/* initialize adapter */ /* initialize adapter */
ret = ahci_host_init(uc_priv); ret = ahci_host_init(uc_priv);

2
drivers/cache/cache-l2x0.c vendored
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@ -13,7 +13,7 @@ static void l2c310_of_parse_and_init(struct udevice *dev)
{ {
u32 tag[3] = { 0, 0, 0 }; u32 tag[3] = { 0, 0, 0 };
u32 saved_reg, prefetch; u32 saved_reg, prefetch;
struct pl310_regs *regs = (struct pl310_regs *)dev_read_addr(dev); struct pl310_regs *regs = dev_read_addr_ptr(dev);
/* Disable the L2 Cache */ /* Disable the L2 Cache */
clrbits_le32(&regs->pl310_ctrl, L2X0_CTRL_EN); clrbits_le32(&regs->pl310_ctrl, L2X0_CTRL_EN);

2
drivers/cache/cache-v5l2.c vendored
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@ -119,7 +119,7 @@ static int v5l2_of_to_plat(struct udevice *dev)
struct v5l2_plat *plat = dev_get_plat(dev); struct v5l2_plat *plat = dev_get_plat(dev);
struct l2cache *regs; struct l2cache *regs;
regs = (struct l2cache *)(uintptr_t)dev_read_addr(dev); regs = dev_read_addr_ptr(dev);
plat->regs = regs; plat->regs = regs;
plat->iprefetch = -EINVAL; plat->iprefetch = -EINVAL;

2
drivers/gpio/mscc_sgpio.c
View File

@ -232,7 +232,7 @@ static int mscc_sgpio_probe(struct udevice *dev)
debug("probe: gpios = %d, bit-count = %d\n", debug("probe: gpios = %d, bit-count = %d\n",
uc_priv->gpio_count, priv->bitcount); uc_priv->gpio_count, priv->bitcount);
priv->regs = (u32 __iomem *)dev_read_addr(dev); priv->regs = dev_read_addr_ptr(dev);
uc_priv->bank_name = "sgpio"; uc_priv->bank_name = "sgpio";
sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0,

4
drivers/gpio/tegra_gpio.c
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@ -339,8 +339,8 @@ static int gpio_tegra_bind(struct udevice *parent)
if (len < 0) if (len < 0)
return len; return len;
bank_count = len / 3 / sizeof(u32); bank_count = len / 3 / sizeof(u32);
ctlr = (struct gpio_ctlr *)dev_read_addr(parent); ctlr = dev_read_addr_ptr(parent);
if ((ulong)ctlr == FDT_ADDR_T_NONE) if (!ctlr)
return -EINVAL; return -EINVAL;
} }
#endif #endif

2
drivers/gpio/xilinx_gpio.c
View File

@ -268,7 +268,7 @@ static int xilinx_gpio_of_to_plat(struct udevice *dev)
struct xilinx_gpio_plat *plat = dev_get_plat(dev); struct xilinx_gpio_plat *plat = dev_get_plat(dev);
int is_dual; int is_dual;
plat->regs = (struct gpio_regs *)dev_read_addr(dev); plat->regs = dev_read_addr_ptr(dev);
plat->bank_max[0] = dev_read_u32_default(dev, "xlnx,gpio-width", 0); plat->bank_max[0] = dev_read_u32_default(dev, "xlnx,gpio-width", 0);
plat->bank_input[0] = dev_read_u32_default(dev, "xlnx,all-inputs", 0); plat->bank_input[0] = dev_read_u32_default(dev, "xlnx,all-inputs", 0);

4
drivers/i2c/i2c-cdns.c
View File

@ -479,9 +479,9 @@ static int cdns_i2c_of_to_plat(struct udevice *dev)
struct clk clk; struct clk clk;
int ret; int ret;
i2c_bus->regs = (struct cdns_i2c_regs *)dev_read_addr(dev); i2c_bus->regs = dev_read_addr_ptr(dev);
if (!i2c_bus->regs) if (!i2c_bus->regs)
return -ENOMEM; return -EINVAL;
if (pdata) if (pdata)
i2c_bus->quirks = pdata->quirks; i2c_bus->quirks = pdata->quirks;

4
drivers/i2c/tegra_i2c.c
View File

@ -364,8 +364,8 @@ static int tegra_i2c_probe(struct udevice *dev)
i2c_bus->id = dev_seq(dev); i2c_bus->id = dev_seq(dev);
i2c_bus->type = dev_get_driver_data(dev); i2c_bus->type = dev_get_driver_data(dev);
i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev); i2c_bus->regs = dev_read_addr_ptr(dev);
if ((ulong)i2c_bus->regs == FDT_ADDR_T_NONE) { if (!i2c_bus->regs) {
debug("%s: Cannot get regs address\n", __func__); debug("%s: Cannot get regs address\n", __func__);
return -EINVAL; return -EINVAL;
} }

2
drivers/mmc/am654_sdhci.c
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@ -584,7 +584,7 @@ static int am654_sdhci_of_to_plat(struct udevice *dev)
int ret; int ret;
host->name = dev->name; host->name = dev->name;
host->ioaddr = (void *)dev_read_addr(dev); host->ioaddr = dev_read_addr_ptr(dev);
plat->non_removable = dev_read_bool(dev, "non-removable"); plat->non_removable = dev_read_bool(dev, "non-removable");
if (plat->flags & DLL_PRESENT) { if (plat->flags & DLL_PRESENT) {

2
drivers/mmc/davinci_mmc.c
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@ -506,7 +506,7 @@ static int davinci_mmc_of_to_plat(struct udevice *dev)
struct davinci_mmc_plat *plat = dev_get_plat(dev); struct davinci_mmc_plat *plat = dev_get_plat(dev);
struct mmc_config *cfg = &plat->cfg; struct mmc_config *cfg = &plat->cfg;
plat->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev); plat->reg_base = dev_read_addr_ptr(dev);
cfg->f_min = 200000; cfg->f_min = 200000;
cfg->f_max = 25000000; cfg->f_max = 25000000;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34, cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34,

2
drivers/mmc/piton_mmc.c
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@ -74,7 +74,7 @@ static int piton_mmc_ofdata_to_platdata(struct udevice *dev)
struct mmc *mmc; struct mmc *mmc;
struct blk_desc *bdesc; struct blk_desc *bdesc;
priv->base_addr = (void *)dev_read_addr(dev); priv->base_addr = dev_read_addr_ptr(dev);
cfg = &plat->cfg; cfg = &plat->cfg;
cfg->name = "PITON MMC"; cfg->name = "PITON MMC";
cfg->host_caps = MMC_MODE_8BIT; cfg->host_caps = MMC_MODE_8BIT;

2
drivers/mmc/tegra_mmc.c
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@ -708,7 +708,7 @@ static int tegra_mmc_probe(struct udevice *dev)
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
priv->reg = (void *)dev_read_addr(dev); priv->reg = dev_read_addr_ptr(dev);
ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl); ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
if (ret) { if (ret) {

6
drivers/mmc/zynq_sdhci.c
View File

@ -1196,9 +1196,9 @@ static int arasan_sdhci_of_to_plat(struct udevice *dev)
arasan_dt_parse_clk_phases(dev); arasan_dt_parse_clk_phases(dev);
#endif #endif
priv->host->ioaddr = (void *)dev_read_addr(dev); priv->host->ioaddr = dev_read_addr_ptr(dev);
if (IS_ERR(priv->host->ioaddr)) if (!priv->host->ioaddr)
return PTR_ERR(priv->host->ioaddr); return -EINVAL;
priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0); priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
priv->no_1p8 = dev_read_bool(dev, "no-1-8-v"); priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");

2
drivers/mtd/nand/raw/arasan_nfc.c
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@ -1233,7 +1233,7 @@ static int arasan_probe(struct udevice *dev)
ofnode child; ofnode child;
int err = -1; int err = -1;
info->reg = (struct nand_regs *)dev_read_addr(dev); info->reg = dev_read_addr_ptr(dev);
mtd = nand_to_mtd(nand_chip); mtd = nand_to_mtd(nand_chip);
nand_set_controller_data(nand_chip, &arasan->nand_ctrl); nand_set_controller_data(nand_chip, &arasan->nand_ctrl);

2
drivers/mtd/nand/raw/cortina_nand.c
View File

@ -1174,7 +1174,7 @@ static int fdt_decode_nand(struct udevice *dev, struct nand_drv *info)
{ {
int ecc_strength; int ecc_strength;
info->reg = (struct nand_ctlr *)dev_read_addr(dev); info->reg = dev_read_addr_ptr(dev);
info->dma_glb = dev_read_addr_index_ptr(dev, 1); info->dma_glb = dev_read_addr_index_ptr(dev, 1);
info->dma_nand = dev_read_addr_index_ptr(dev, 2); info->dma_nand = dev_read_addr_index_ptr(dev, 2);
info->config.enabled = dev_read_enabled(dev); info->config.enabled = dev_read_enabled(dev);

2
drivers/mtd/nand/raw/mxic_nand.c
View File

@ -538,7 +538,7 @@ static int mxic_nfc_probe(struct udevice *dev)
ofnode child; ofnode child;
int err; int err;
nfc->regs = (void *)dev_read_addr(dev); nfc->regs = dev_read_addr_ptr(dev);
nfc->send_clk = devm_clk_get(dev, "send"); nfc->send_clk = devm_clk_get(dev, "send");
if (IS_ERR(nfc->send_clk)) if (IS_ERR(nfc->send_clk))

2
drivers/mtd/nand/raw/tegra_nand.c
View File

@ -906,7 +906,7 @@ static int fdt_decode_nand(struct udevice *dev, struct fdt_nand *config)
{ {
int err; int err;
config->reg = (struct nand_ctlr *)dev_read_addr(dev); config->reg = dev_read_addr_ptr(dev);
config->enabled = dev_read_enabled(dev); config->enabled = dev_read_enabled(dev);
config->width = dev_read_u32_default(dev, "nvidia,nand-width", 8); config->width = dev_read_u32_default(dev, "nvidia,nand-width", 8);
err = gpio_request_by_name(dev, "nvidia,wp-gpios", 0, &config->wp_gpio, err = gpio_request_by_name(dev, "nvidia,wp-gpios", 0, &config->wp_gpio,

2
drivers/mtd/nand/raw/zynq_nand.c
View File

@ -1085,7 +1085,7 @@ static int zynq_nand_probe(struct udevice *dev)
int ondie_ecc_enabled = 0; int ondie_ecc_enabled = 0;
int is_16bit_bw; int is_16bit_bw;
smc->reg = (struct zynq_nand_smc_regs *)dev_read_addr(dev); smc->reg = dev_read_addr_ptr(dev);
of_nand = dev_read_subnode(dev, "nand-controller@0,0"); of_nand = dev_read_subnode(dev, "nand-controller@0,0");
if (!ofnode_valid(of_nand)) { if (!ofnode_valid(of_nand)) {
of_nand = dev_read_subnode(dev, "flash@e1000000"); of_nand = dev_read_subnode(dev, "flash@e1000000");

2
drivers/net/mvmdio.c
View File

@ -208,7 +208,7 @@ static int mvmdio_probe(struct udevice *dev)
{ {
struct mvmdio_priv *priv = dev_get_priv(dev); struct mvmdio_priv *priv = dev_get_priv(dev);
priv->mdio_base = (void *)dev_read_addr(dev); priv->mdio_base = dev_read_addr_ptr(dev);
priv->type = (enum mvmdio_bus_type)dev_get_driver_data(dev); priv->type = (enum mvmdio_bus_type)dev_get_driver_data(dev);
return 0; return 0;

2
drivers/net/qe/dm_qe_uec_phy.c
View File

@ -97,7 +97,7 @@ static int qe_uec_mdio_probe(struct udevice *dev)
u32 num = 0; u32 num = 0;
int ret = -ENODEV; int ret = -ENODEV;
priv->base = (struct ucc_mii_mng *)dev_read_addr(dev); priv->base = dev_read_addr_ptr(dev);
base = (fdt_size_t)priv->base; base = (fdt_size_t)priv->base;
/* /*

4
drivers/pci/pci-aardvark.c
View File

@ -983,8 +983,8 @@ static int pcie_advk_of_to_plat(struct udevice *dev)
struct pcie_advk *pcie = dev_get_priv(dev); struct pcie_advk *pcie = dev_get_priv(dev);
/* Get the register base address */ /* Get the register base address */
pcie->base = (void *)dev_read_addr(dev); pcie->base = dev_read_addr_ptr(dev);
if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE) if (!pcie->base)
return -EINVAL; return -EINVAL;
return 0; return 0;

6
drivers/phy/allwinner/phy-sun50i-usb3.c
View File

@ -149,9 +149,9 @@ static int sun50i_usb3_phy_probe(struct udevice *dev)
return ret; return ret;
} }
priv->regs = (void __iomem *)dev_read_addr(dev); priv->regs = dev_read_addr_ptr(dev);
if (IS_ERR(priv->regs)) if (!priv->regs)
return PTR_ERR(priv->regs); return -EINVAL;
return 0; return 0;
} }

4
drivers/phy/qcom/phy-qcom-usb-hs-28nm.c
View File

@ -184,8 +184,8 @@ static int hsphy_probe(struct udevice *dev)
struct hsphy_priv *priv = dev_get_priv(dev); struct hsphy_priv *priv = dev_get_priv(dev);
int ret; int ret;
priv->base = (void *)dev_read_addr(dev); priv->base = dev_read_addr_ptr(dev);
if ((ulong)priv->base == FDT_ADDR_T_NONE) if (!priv->base)
return -EINVAL; return -EINVAL;
ret = reset_get_by_name(dev, "phy", &priv->phy_rst); ret = reset_get_by_name(dev, "phy", &priv->phy_rst);

4
drivers/phy/qcom/phy-qcom-usb-ss.c
View File

@ -115,8 +115,8 @@ static int ssphy_probe(struct udevice *dev)
struct ssphy_priv *priv = dev_get_priv(dev); struct ssphy_priv *priv = dev_get_priv(dev);
int ret; int ret;
priv->base = (void *)dev_read_addr(dev); priv->base = dev_read_addr_ptr(dev);
if ((ulong)priv->base == FDT_ADDR_T_NONE) if (!priv->base)
return -EINVAL; return -EINVAL;
ret = ssphy_clk_init(dev, priv); ret = ssphy_clk_init(dev, priv);

4
drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
View File

@ -93,8 +93,8 @@ static int rockchip_p3phy_probe(struct udevice *dev)
struct udevice *syscon; struct udevice *syscon;
int ret; int ret;
priv->mmio = (void __iomem *)dev_read_addr(dev); priv->mmio = dev_read_addr_ptr(dev);
if ((fdt_addr_t)priv->mmio == FDT_ADDR_T_NONE) if (!priv->mmio)
return -EINVAL; return -EINVAL;
ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,

6
drivers/phy/rockchip/phy-rockchip-typec.c
View File

@ -674,9 +674,9 @@ static int rockchip_tcphy_probe(struct udevice *dev)
unsigned int reg; unsigned int reg;
int index, ret; int index, ret;
priv->reg_base = (void __iomem *)dev_read_addr(dev); priv->reg_base = dev_read_addr_ptr(dev);
if (IS_ERR(priv->reg_base)) if (!priv->reg_base)
return PTR_ERR(priv->reg_base); return -EINVAL;
ret = dev_read_u32_index(dev, "reg", 1, &reg); ret = dev_read_u32_index(dev, "reg", 1, &reg);
if (ret) { if (ret) {

2
drivers/pwm/tegra_pwm.c
View File

@ -59,7 +59,7 @@ static int tegra_pwm_of_to_plat(struct udevice *dev)
{ {
struct tegra_pwm_priv *priv = dev_get_priv(dev); struct tegra_pwm_priv *priv = dev_get_priv(dev);
priv->regs = (struct pwm_ctlr *)dev_read_addr(dev); priv->regs = dev_read_addr_ptr(dev);
return 0; return 0;
} }

6
drivers/serial/serial_zynq.c
View File

@ -259,9 +259,9 @@ static int zynq_serial_of_to_plat(struct udevice *dev)
{ {
struct zynq_uart_plat *plat = dev_get_plat(dev); struct zynq_uart_plat *plat = dev_get_plat(dev);
plat->regs = (struct uart_zynq *)dev_read_addr(dev); plat->regs = dev_read_addr_ptr(dev);
if (IS_ERR(plat->regs)) if (!plat->regs)
return PTR_ERR(plat->regs); return -EINVAL;
return 0; return 0;
} }

2
drivers/spi/mpc8xxx_spi.c
View File

@ -56,7 +56,7 @@ static int mpc8xxx_spi_of_to_plat(struct udevice *dev)
struct clk clk; struct clk clk;
int ret; int ret;
priv->spi = (spi8xxx_t *)dev_read_addr(dev); priv->spi = dev_read_addr_ptr(dev);
ret = gpio_request_list_by_name(dev, "gpios", priv->gpios, ret = gpio_request_list_by_name(dev, "gpios", priv->gpios,
ARRAY_SIZE(priv->gpios), GPIOD_IS_OUT | GPIOD_ACTIVE_LOW); ARRAY_SIZE(priv->gpios), GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);

2
drivers/spi/mscc_bb_spi.c
View File

@ -217,7 +217,7 @@ static int mscc_bb_spi_probe(struct udevice *bus)
debug("%s: loaded, priv %p\n", __func__, priv); debug("%s: loaded, priv %p\n", __func__, priv);
priv->regs = (void __iomem *)dev_read_addr(bus); priv->regs = dev_read_addr_ptr(bus);
priv->deactivate_delay_us = priv->deactivate_delay_us =
dev_read_u32_default(bus, "spi-deactivate-delay", 0); dev_read_u32_default(bus, "spi-deactivate-delay", 0);

2
drivers/spi/sh_qspi.c
View File

@ -334,7 +334,7 @@ static int sh_qspi_of_to_plat(struct udevice *dev)
{ {
struct sh_qspi_slave *plat = dev_get_plat(dev); struct sh_qspi_slave *plat = dev_get_plat(dev);
plat->regs = (struct sh_qspi_regs *)dev_read_addr(dev); plat->regs = dev_read_addr_ptr(dev);
return 0; return 0;
} }

2
drivers/spi/spi-mxic.c
View File

@ -508,7 +508,7 @@ static int mxic_spi_probe(struct udevice *bus)
{ {
struct mxic_spi_priv *priv = dev_get_priv(bus); struct mxic_spi_priv *priv = dev_get_priv(bus);
priv->regs = (void *)dev_read_addr(bus); priv->regs = dev_read_addr_ptr(bus);
priv->send_clk = devm_clk_get(bus, "send_clk"); priv->send_clk = devm_clk_get(bus, "send_clk");
if (IS_ERR(priv->send_clk)) if (IS_ERR(priv->send_clk))

2
drivers/spi/xilinx_spi.c
View File

@ -114,7 +114,7 @@ static int xilinx_spi_probe(struct udevice *bus)
struct xilinx_spi_priv *priv = dev_get_priv(bus); struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs; struct xilinx_spi_regs *regs;
regs = priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus); regs = priv->regs = dev_read_addr_ptr(bus);
priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0); priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
writel(SPISSR_RESET_VALUE, &regs->srr); writel(SPISSR_RESET_VALUE, &regs->srr);

2
drivers/ufs/ufs.c
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@ -1880,7 +1880,7 @@ int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops)
hba->dev = ufs_dev; hba->dev = ufs_dev;
hba->ops = hba_ops; hba->ops = hba_ops;
hba->mmio_base = (void *)dev_read_addr(ufs_dev); hba->mmio_base = dev_read_addr_ptr(ufs_dev);
/* Set descriptor lengths to specification defaults */ /* Set descriptor lengths to specification defaults */
ufshcd_def_desc_sizes(hba); ufshcd_def_desc_sizes(hba);

2
drivers/usb/host/ehci-tegra.c
View File

@ -723,7 +723,7 @@ static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config)
{ {
const char *phy, *mode; const char *phy, *mode;
config->reg = (struct usb_ctlr *)dev_read_addr(dev); config->reg = dev_read_addr_ptr(dev);
debug("reg=%p\n", config->reg); debug("reg=%p\n", config->reg);
mode = dev_read_string(dev, "dr_mode"); mode = dev_read_string(dev, "dr_mode");
if (mode) { if (mode) {

4
drivers/video/dw_mipi_dsi.c
View File

@ -800,8 +800,8 @@ static int dw_mipi_dsi_init(struct udevice *dev,
dsi->dsi_host.ops = &dw_mipi_dsi_host_ops; dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
device->host = &dsi->dsi_host; device->host = &dsi->dsi_host;
dsi->base = (void *)dev_read_addr(device->dev); dsi->base = dev_read_addr_ptr(device->dev);
if ((fdt_addr_t)dsi->base == FDT_ADDR_T_NONE) { if (!dsi->base) {
dev_err(device->dev, "dsi dt register address error\n"); dev_err(device->dev, "dsi dt register address error\n");
return -EINVAL; return -EINVAL;
} }

2
drivers/video/rockchip/rk_vop.c
View File

@ -447,7 +447,7 @@ int rk_vop_probe(struct udevice *dev)
efi_add_memory_map(plat->base, plat->size, EFI_RESERVED_MEMORY_TYPE); efi_add_memory_map(plat->base, plat->size, EFI_RESERVED_MEMORY_TYPE);
#endif #endif
priv->regs = (struct rk3288_vop *)dev_read_addr(dev); priv->regs = dev_read_addr_ptr(dev);
/* /*
* Try all the ports until we find one that works. In practice this * Try all the ports until we find one that works. In practice this

4
drivers/video/stm32/stm32_dsi.c
View File

@ -427,8 +427,8 @@ static int stm32_dsi_probe(struct udevice *dev)
device->dev = dev; device->dev = dev;
priv->base = (void *)dev_read_addr(dev); priv->base = dev_read_addr_ptr(dev);
if ((fdt_addr_t)priv->base == FDT_ADDR_T_NONE) { if (!priv->base) {
dev_err(dev, "dsi dt register address error\n"); dev_err(dev, "dsi dt register address error\n");
return -EINVAL; return -EINVAL;
} }

4
drivers/video/stm32/stm32_ltdc.c
View File

@ -507,8 +507,8 @@ static int stm32_ltdc_probe(struct udevice *dev)
ulong rate; ulong rate;
int ret; int ret;
priv->regs = (void *)dev_read_addr(dev); priv->regs = dev_read_addr_ptr(dev);
if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) { if (!priv->regs) {
dev_err(dev, "ltdc dt register address error\n"); dev_err(dev, "ltdc dt register address error\n");
return -EINVAL; return -EINVAL;
} }

2
drivers/video/tegra124/display.c
View File

@ -361,7 +361,7 @@ static int display_init(struct udevice *dev, void *lcdbase,
return ret; return ret;
} }
dc_ctlr = (struct dc_ctlr *)dev_read_addr(dev); dc_ctlr = dev_read_addr_ptr(dev);
if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) { if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) {
debug("%s: Failed to decode display timing\n", __func__); debug("%s: Failed to decode display timing\n", __func__);
return -EINVAL; return -EINVAL;

6
drivers/video/tegra124/sor.c
View File

@ -765,7 +765,7 @@ int tegra_dc_sor_attach(struct udevice *dc_dev, struct udevice *dev,
/* Use the first display controller */ /* Use the first display controller */
debug("%s\n", __func__); debug("%s\n", __func__);
disp_ctrl = (struct dc_ctlr *)dev_read_addr(dc_dev); disp_ctrl = dev_read_addr_ptr(dc_dev);
tegra_dc_sor_enable_dc(disp_ctrl); tegra_dc_sor_enable_dc(disp_ctrl);
tegra_dc_sor_config_panel(sor, 0, link_cfg, timing); tegra_dc_sor_config_panel(sor, 0, link_cfg, timing);
@ -978,7 +978,7 @@ int tegra_dc_sor_detach(struct udevice *dc_dev, struct udevice *dev)
debug("%s\n", __func__); debug("%s\n", __func__);
/* Use the first display controller */ /* Use the first display controller */
disp_ctrl = (struct dc_ctlr *)dev_read_addr(dev); disp_ctrl = dev_read_addr_ptr(dev);
/* Sleep mode */ /* Sleep mode */
tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP | tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |
@ -1047,7 +1047,7 @@ static int tegra_sor_of_to_plat(struct udevice *dev)
struct tegra_dc_sor_data *priv = dev_get_priv(dev); struct tegra_dc_sor_data *priv = dev_get_priv(dev);
int ret; int ret;
priv->base = (void *)dev_read_addr(dev); priv->base = dev_read_addr_ptr(dev);
priv->pmc_base = (void *)syscon_get_first_range(TEGRA_SYSCON_PMC); priv->pmc_base = (void *)syscon_get_first_range(TEGRA_SYSCON_PMC);
if (IS_ERR(priv->pmc_base)) if (IS_ERR(priv->pmc_base))

4
drivers/video/ti/tilcdc.c
View File

@ -387,8 +387,8 @@ static int tilcdc_of_to_plat(struct udevice *dev)
{ {
struct tilcdc_priv *priv = dev_get_priv(dev); struct tilcdc_priv *priv = dev_get_priv(dev);
priv->regs = (struct tilcdc_regs *)dev_read_addr(dev); priv->regs = dev_read_addr_ptr(dev);
if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) { if (!priv->regs) {
dev_err(dev, "failed to get base address\n"); dev_err(dev, "failed to get base address\n");
return -EINVAL; return -EINVAL;
} }

6
drivers/watchdog/cdns_wdt.c
View File

@ -271,9 +271,9 @@ static int cdns_wdt_of_to_plat(struct udevice *dev)
{ {
struct cdns_wdt_priv *priv = dev_get_priv(dev); struct cdns_wdt_priv *priv = dev_get_priv(dev);
priv->regs = (struct cdns_regs *)dev_read_addr(dev); priv->regs = dev_read_addr_ptr(dev);
if (IS_ERR(priv->regs)) if (!priv->regs)
return PTR_ERR(priv->regs); return -EINVAL;
priv->rst = dev_read_bool(dev, "reset-on-timeout"); priv->rst = dev_read_bool(dev, "reset-on-timeout");

6
drivers/watchdog/sp805_wdt.c
View File

@ -116,9 +116,9 @@ static int sp805_wdt_of_to_plat(struct udevice *dev)
struct sp805_wdt_priv *priv = dev_get_priv(dev); struct sp805_wdt_priv *priv = dev_get_priv(dev);
struct clk clk; struct clk clk;
priv->reg = (void __iomem *)dev_read_addr(dev); priv->reg = dev_read_addr_ptr(dev);
if (IS_ERR(priv->reg)) if (!priv->reg)
return PTR_ERR(priv->reg); return -EINVAL;
if (!clk_get_by_index(dev, 0, &clk)) if (!clk_get_by_index(dev, 0, &clk))
priv->clk_rate = clk_get_rate(&clk); priv->clk_rate = clk_get_rate(&clk);

6
drivers/watchdog/xilinx_tb_wdt.c
View File

@ -94,9 +94,9 @@ static int xlnx_wdt_of_to_plat(struct udevice *dev)
{ {
struct xlnx_wdt_plat *plat = dev_get_plat(dev); struct xlnx_wdt_plat *plat = dev_get_plat(dev);
plat->regs = (struct watchdog_regs *)dev_read_addr(dev); plat->regs = dev_read_addr_ptr(dev);
if (IS_ERR(plat->regs)) if (!plat->regs)
return PTR_ERR(plat->regs); return -EINVAL;
plat->enable_once = dev_read_u32_default(dev, "xlnx,wdt-enable-once", plat->enable_once = dev_read_u32_default(dev, "xlnx,wdt-enable-once",
0); 0);