From ca4b097d7ba88778189ae36b549ea81be89db650 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 24 Nov 2021 18:00:30 +0100 Subject: [PATCH 01/19] vexpress64: Remove unused macro XR3PCI_ECAM_OFFSET MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Macro XR3PCI_ECAM_OFFSET is unused and in case it would be needed in future it can be replaced by standard PCIE_ECAM_OFFSET macro from pci.h file. Signed-off-by: Pali Rohár --- board/armltd/vexpress64/pcie.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c index 733b190e594..1e74158630b 100644 --- a/board/armltd/vexpress64/pcie.c +++ b/board/armltd/vexpress64/pcie.c @@ -56,10 +56,6 @@ #define XR3PCI_ATR_TRSLID_PCIE_IO (0x020000) #define XR3PCI_ATR_TRSLID_PCIE_MEMORY (0x000000) -#define XR3PCI_ECAM_OFFSET(b, d, o) (((b) << 20) | \ - (PCI_SLOT(d) << 15) | \ - (PCI_FUNC(d) << 12) | o) - #define JUNO_RESET_CTRL 0x1004 #define JUNO_RESET_CTRL_PHY BIT(0) #define JUNO_RESET_CTRL_RC BIT(1) From fbfa15c0b82b4e1ee1e974e2a85075cead502976 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 24 Nov 2021 18:00:31 +0100 Subject: [PATCH 02/19] pci: pcie-brcmstb: Use PCIE_ECAM_OFFSET() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace custom driver macros by PCIE_ECAM_OFFSET() macro from pci.h Signed-off-by: Pali Rohár Reviewed-by: Nicolas Saenz Julienne --- drivers/pci/pcie_brcmstb.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c index 90225f67795..1de28021138 100644 --- a/drivers/pci/pcie_brcmstb.c +++ b/drivers/pci/pcie_brcmstb.c @@ -97,9 +97,6 @@ #define PCIE_EXT_CFG_DATA 0x8000 #define PCIE_EXT_CFG_INDEX 0x9000 -#define PCIE_EXT_BUSNUM_SHIFT 20 -#define PCIE_EXT_SLOT_SHIFT 15 -#define PCIE_EXT_FUNC_SHIFT 12 #define PCIE_RGR1_SW_INIT_1 0x9210 #define RGR1_SW_INIT_1_PERST_MASK 0x1 @@ -227,9 +224,7 @@ static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf, } /* For devices, write to the config space index register */ - idx = (pci_bus << PCIE_EXT_BUSNUM_SHIFT) - | (pci_dev << PCIE_EXT_SLOT_SHIFT) - | (pci_func << PCIE_EXT_FUNC_SHIFT); + idx = PCIE_ECAM_OFFSET(pci_bus, pci_dev, pci_func, 0); writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); *paddress = pcie->base + PCIE_EXT_CFG_DATA + offset; From 3264b6177f692c9dc5355f4b11f3a7f0dce6cb1f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 24 Nov 2021 18:00:32 +0100 Subject: [PATCH 03/19] pci: pcie_iproc: Use PCIE_ECAM_OFFSET() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace custom driver macros by PCIE_ECAM_OFFSET() macro from pci.h Signed-off-by: Pali Rohár --- drivers/pci/pcie_iproc.c | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) diff --git a/drivers/pci/pcie_iproc.c b/drivers/pci/pcie_iproc.c index be03dcbd97c..a31e74a0f2e 100644 --- a/drivers/pci/pcie_iproc.c +++ b/drivers/pci/pcie_iproc.c @@ -24,15 +24,7 @@ #define CFG_IND_ADDR_MASK 0x00001ffc -#define CFG_ADDR_BUS_NUM_SHIFT 20 -#define CFG_ADDR_BUS_NUM_MASK 0x0ff00000 -#define CFG_ADDR_DEV_NUM_SHIFT 15 -#define CFG_ADDR_DEV_NUM_MASK 0x000f8000 -#define CFG_ADDR_FUNC_NUM_SHIFT 12 -#define CFG_ADDR_FUNC_NUM_MASK 0x00007000 -#define CFG_ADDR_REG_NUM_SHIFT 2 -#define CFG_ADDR_REG_NUM_MASK 0x00000ffc -#define CFG_ADDR_CFG_TYPE_SHIFT 0 +#define CFG_ADDR_CFG_ECAM_MASK 0xfffffffc #define CFG_ADDR_CFG_TYPE_MASK 0x00000003 #define IPROC_PCI_PM_CAP 0x48 @@ -473,11 +465,8 @@ static int iproc_pcie_map_ep_cfg_reg(const struct udevice *udev, pci_dev_t bdf, return -ENODEV; /* EP device access */ - val = (busno << CFG_ADDR_BUS_NUM_SHIFT) | - (slot << CFG_ADDR_DEV_NUM_SHIFT) | - (fn << CFG_ADDR_FUNC_NUM_SHIFT) | - (where & CFG_ADDR_REG_NUM_MASK) | - (1 & CFG_ADDR_CFG_TYPE_MASK); + val = (PCIE_ECAM_OFFSET(busno, slot, fn, where) & CFG_ADDR_CFG_ECAM_MASK) + | (1 & CFG_ADDR_CFG_TYPE_MASK); iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val); offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA); From bf667d5f15a75c2f1d4715ac3b7525b300ae1c58 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 24 Nov 2021 18:00:33 +0100 Subject: [PATCH 04/19] pci: pci_octeontx: Use PCIE_ECAM_OFFSET() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace custom driver macros by PCIE_ECAM_OFFSET() macro from pci.h Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/pci/pci_octeontx.c | 61 +++++++++++++------------------------- 1 file changed, 20 insertions(+), 41 deletions(-) diff --git a/drivers/pci/pci_octeontx.c b/drivers/pci/pci_octeontx.c index 46855c5cd3a..875cf7f7115 100644 --- a/drivers/pci/pci_octeontx.c +++ b/drivers/pci/pci_octeontx.c @@ -49,25 +49,6 @@ struct octeontx_pci { struct resource bus; }; -static uintptr_t octeontx_cfg_addr(struct octeontx_pci *pcie, - int bus_offs, int shift_offs, - pci_dev_t bdf, uint offset) -{ - u32 bus, dev, func; - uintptr_t address; - - bus = PCI_BUS(bdf) + bus_offs; - dev = PCI_DEV(bdf); - func = PCI_FUNC(bdf); - - address = (bus << (20 + shift_offs)) | - (dev << (15 + shift_offs)) | - (func << (12 + shift_offs)) | offset; - address += pcie->cfg.start; - - return address; -} - static ulong readl_size(uintptr_t addr, enum pci_size_t size) { ulong val; @@ -123,9 +104,9 @@ static int octeontx_ecam_read_config(const struct udevice *bus, pci_dev_t bdf, struct pci_controller *hose = dev_get_uclass_priv(bus); uintptr_t address; - address = octeontx_cfg_addr(pcie, pcie->bus.start - hose->first_busno, - 0, bdf, offset); - *valuep = readl_size(address, size); + address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + pcie->bus.start - hose->first_busno, + PCI_DEV(bdf), PCI_FUNC(bdf), offset); + *valuep = readl_size(pcie->cfg.start + address, size); debug("%02x.%02x.%02x: u%d %x -> %lx\n", PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset, *valuep); @@ -141,9 +122,9 @@ static int octeontx_ecam_write_config(struct udevice *bus, pci_dev_t bdf, struct pci_controller *hose = dev_get_uclass_priv(bus); uintptr_t address; - address = octeontx_cfg_addr(pcie, pcie->bus.start - hose->first_busno, - 0, bdf, offset); - writel_size(address, size, value); + address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + pcie->bus.start - hose->first_busno, + PCI_DEV(bdf), PCI_FUNC(bdf), offset); + writel_size(pcie->cfg.start + address, size, value); debug("%02x.%02x.%02x: u%d %x <- %lx\n", PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset, value); @@ -162,17 +143,16 @@ static int octeontx_pem_read_config(const struct udevice *bus, pci_dev_t bdf, u8 pri_bus = pcie->bus.start + 1 - hose->first_busno; u32 bus_offs = (pri_bus << 16) | (pri_bus << 8) | (pri_bus << 0); - address = octeontx_cfg_addr(pcie, 1 - hose->first_busno, 4, - bdf, 0); - *valuep = pci_conv_32_to_size(~0UL, offset, size); if (octeontx_bdf_invalid(bdf)) return -EPERM; - *valuep = readl_size(address + offset, size); + address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + 1 - hose->first_busno, + PCI_DEV(bdf), PCI_FUNC(bdf), 0) << 4; + *valuep = readl_size(pcie->cfg.start + address + offset, size); - hdrtype = readb(address + PCI_HEADER_TYPE); + hdrtype = readb(pcie->cfg.start + address + PCI_HEADER_TYPE); if (hdrtype == PCI_HEADER_TYPE_BRIDGE && offset >= PCI_PRIMARY_BUS && offset <= PCI_SUBORDINATE_BUS && @@ -193,9 +173,10 @@ static int octeontx_pem_write_config(struct udevice *bus, pci_dev_t bdf, u8 pri_bus = pcie->bus.start + 1 - hose->first_busno; u32 bus_offs = (pri_bus << 16) | (pri_bus << 8) | (pri_bus << 0); - address = octeontx_cfg_addr(pcie, 1 - hose->first_busno, 4, bdf, 0); + address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + 1 - hose->first_busno, + PCI_DEV(bdf), PCI_FUNC(bdf), 0) << 4; - hdrtype = readb(address + PCI_HEADER_TYPE); + hdrtype = readb(pcie->cfg.start + address + PCI_HEADER_TYPE); if (hdrtype == PCI_HEADER_TYPE_BRIDGE && offset >= PCI_PRIMARY_BUS && offset <= PCI_SUBORDINATE_BUS && @@ -205,7 +186,7 @@ static int octeontx_pem_write_config(struct udevice *bus, pci_dev_t bdf, if (octeontx_bdf_invalid(bdf)) return -EPERM; - writel_size(address + offset, size, value); + writel_size(pcie->cfg.start + address + offset, size, value); debug("%02x.%02x.%02x: u%d %x (%lx) <- %lx\n", PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset, @@ -222,15 +203,14 @@ static int octeontx2_pem_read_config(const struct udevice *bus, pci_dev_t bdf, struct pci_controller *hose = dev_get_uclass_priv(bus); uintptr_t address; - address = octeontx_cfg_addr(pcie, 1 - hose->first_busno, 0, - bdf, 0); - *valuep = pci_conv_32_to_size(~0UL, offset, size); if (octeontx_bdf_invalid(bdf)) return -EPERM; - *valuep = readl_size(address + offset, size); + address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + 1 - hose->first_busno, + PCI_DEV(bdf), PCI_FUNC(bdf), offset); + *valuep = readl_size(pcie->cfg.start + address, size); debug("%02x.%02x.%02x: u%d %x (%lx) -> %lx\n", PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset, @@ -247,13 +227,12 @@ static int octeontx2_pem_write_config(struct udevice *bus, pci_dev_t bdf, struct pci_controller *hose = dev_get_uclass_priv(bus); uintptr_t address; - address = octeontx_cfg_addr(pcie, 1 - hose->first_busno, 0, - bdf, 0); - if (octeontx_bdf_invalid(bdf)) return -EPERM; - writel_size(address + offset, size, value); + address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + 1 - hose->first_busno, + PCI_DEV(bdf), PCI_FUNC(bdf), offset); + writel_size(pcie->cfg.start + address, size, value); debug("%02x.%02x.%02x: u%d %x (%lx) <- %lx\n", PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset, From f2094143c5367f38c74d4233a65afb07a25a8ace Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 25 Nov 2021 11:30:58 +0100 Subject: [PATCH 05/19] pci: Fix register for determining type of IO base address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Function dm_pciauto_prescan_setup_bridge() configures base address registers, therefore it should read type of IO from base address registers (and not from limit address registers). Note that base and limit address registers should have same type, so this change is just usage correction and has no functional change on correctly working hardware. Fixes: 8e85f36a8fab ("pci: Fix configuring io/memory base and limit registers of PCI bridges") Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/pci/pci_auto.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 5af4ee6e56d..7e6ee54be08 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -197,7 +197,7 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat); dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64); prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; - dm_pci_read_config8(dev, PCI_IO_LIMIT, &io_32); + dm_pci_read_config8(dev, PCI_IO_BASE, &io_32); io_32 &= PCI_IO_RANGE_TYPE_MASK; /* Configure bus number registers */ From 06f25bd2a907fa543d69757da4e3c752b7103e54 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 25 Nov 2021 11:32:43 +0100 Subject: [PATCH 06/19] pci: Disable I/O forwarding during autoconfiguration if unsupported MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If U-Boot does not have any I/O resource for assignment then disable I/O forwarding in PCI bridge autoconfiguration code. Default initial state of PCI bridge IO registers is unspecified, therefore they can be in enabled if U-Boot does not touch them. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/pci/pci_auto.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 7e6ee54be08..6e5ed194f24 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -265,6 +265,14 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) (pci_io->bus_lower & 0xffff0000) >> 16); cmdstat |= PCI_COMMAND_IO; + } else { + /* Disable I/O if unsupported */ + dm_pci_write_config8(dev, PCI_IO_BASE, 0xf0 | io_32); + dm_pci_write_config8(dev, PCI_IO_LIMIT, 0x0 | io_32); + if (io_32 == PCI_IO_RANGE_TYPE_32) { + dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, 0x0); + dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, 0x0); + } } /* Enable memory and I/O accesses, enable bus master */ From 95ab5784bfc2d1a431d1a95b215893c2d808f7e8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 25 Nov 2021 11:34:37 +0100 Subject: [PATCH 07/19] pci: When disabling pref MEM set all base bits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is common to set all base address bits to one and all limit address bits to zero for disabling address forwarding. Forwarding is disabled when base address is higher than limit address, so this change should not have any effect. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/pci/pci_auto.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 6e5ed194f24..c0acf331398 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -243,7 +243,7 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) cmdstat |= PCI_COMMAND_MEMORY; } else { /* We don't support prefetchable memory for now, so disable */ - dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000 | + dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0xfff0 | prefechable_64); dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0 | prefechable_64); From 2a8d4025c3bdeeca0484ab45606e08649f8b85a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 26 Nov 2021 11:42:41 +0100 Subject: [PATCH 08/19] pci: Add standard PCI Config Address macros MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Lot of PCI and PCIe controllers are using standard Config Address for PCI Configuration Mechanism #1 or its extended version. So add PCI_CONF1_ADDRESS() and PCI_CONF1_EXT_ADDRESS() macros into U-Boot's pci.h header file which can be suitable for most PCI and PCIe controller drivers. Drivers do not have to invent their own macros and can use these new U-Boot macros. Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- include/pci.h | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/include/pci.h b/include/pci.h index 6c1094d7299..0ea41a7e1ba 100644 --- a/include/pci.h +++ b/include/pci.h @@ -522,6 +522,51 @@ #include +/* + * Config Address for PCI Configuration Mechanism #1 + * + * See PCI Local Bus Specification, Revision 3.0, + * Section 3.2.2.3.2, Figure 3-2, p. 50. + */ + +#define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ +#define PCI_CONF1_DEV_SHIFT 11 /* Device number */ +#define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ + +#define PCI_CONF1_BUS_MASK 0xff +#define PCI_CONF1_DEV_MASK 0x1f +#define PCI_CONF1_FUNC_MASK 0x7 +#define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ + +#define PCI_CONF1_ENABLE BIT(31) +#define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) +#define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) +#define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) +#define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) + +#define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ + (PCI_CONF1_ENABLE | \ + PCI_CONF1_BUS(bus) | \ + PCI_CONF1_DEV(dev) | \ + PCI_CONF1_FUNC(func) | \ + PCI_CONF1_REG(reg)) + +/* + * Extension of PCI Config Address for accessing extended PCIe registers + * + * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs + * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address + * are used for specifying additional 4 high bits of PCI Express register. + */ + +#define PCI_CONF1_EXT_REG_SHIFT 16 +#define PCI_CONF1_EXT_REG_MASK 0xf00 +#define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) + +#define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ + (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ + PCI_CONF1_EXT_REG(reg)) + /* * Enhanced Configuration Access Mechanism (ECAM) * From 2b29d79be83ab0d34582577300bf1de8f39dd97e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 26 Nov 2021 11:42:42 +0100 Subject: [PATCH 09/19] pci: gt64120: Use PCI_CONF1_ADDRESS() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCI gt64120 driver uses standard format of Config Address for PCI Configuration Mechanism #1. So use new U-Boot macro PCI_CONF1_ADDRESS() and remove old custom driver address macros. Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- drivers/pci/pci_gt64120.c | 7 ++----- include/gt64120.h | 12 ------------ 2 files changed, 2 insertions(+), 17 deletions(-) diff --git a/drivers/pci/pci_gt64120.c b/drivers/pci/pci_gt64120.c index 153c65b119a..2c2a80eeaa0 100644 --- a/drivers/pci/pci_gt64120.c +++ b/drivers/pci/pci_gt64120.c @@ -48,7 +48,7 @@ static int gt_config_access(struct gt64120_pci_controller *gt, { unsigned int bus = PCI_BUS(bdf); unsigned int dev = PCI_DEV(bdf); - unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf); + unsigned int func = PCI_FUNC(bdf); u32 intr; u32 addr; u32 val; @@ -65,10 +65,7 @@ static int gt_config_access(struct gt64120_pci_controller *gt, /* Clear cause register bits */ writel(~GT_INTRCAUSE_ABORT_BITS, >->regs->intrcause); - addr = GT_PCI0_CFGADDR_CONFIGEN_BIT; - addr |= bus << GT_PCI0_CFGADDR_BUSNUM_SHF; - addr |= devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF; - addr |= (where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF; + addr = PCI_CONF1_ADDRESS(bus, dev, func, where); /* Setup address */ writel(addr, >->regs->pci0_cfgaddr); diff --git a/include/gt64120.h b/include/gt64120.h index 0b577f3f44b..b58afe3c4af 100644 --- a/include/gt64120.h +++ b/include/gt64120.h @@ -491,18 +491,6 @@ #define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK -#define GT_PCI0_CFGADDR_REGNUM_SHF 2 -#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) -#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 -#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) -#define GT_PCI0_CFGADDR_DEVNUM_SHF 11 -#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) -#define GT_PCI0_CFGADDR_BUSNUM_SHF 16 -#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) -#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 -#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) -#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK - #define GT_PCI0_CMD_MBYTESWAP_SHF 0 #define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF) #define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK From 247ffc6b36ac2605d54fe31628ae6b827603d0ac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 26 Nov 2021 11:42:43 +0100 Subject: [PATCH 10/19] pci: mpc85xx: Use PCI_CONF1_EXT_ADDRESS() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCI mpc85xx driver uses extended format of Config Address for PCI Configuration Mechanism #1. So use new U-Boot macro PCI_CONF1_EXT_ADDRESS(). Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- drivers/pci/pci_mpc85xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci_mpc85xx.c b/drivers/pci/pci_mpc85xx.c index 574cb784a89..1e180ee289b 100644 --- a/drivers/pci/pci_mpc85xx.c +++ b/drivers/pci/pci_mpc85xx.c @@ -23,7 +23,7 @@ static int mpc85xx_pci_dm_read_config(const struct udevice *dev, pci_dev_t bdf, struct mpc85xx_pci_priv *priv = dev_get_priv(dev); u32 addr; - addr = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; + addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset); out_be32(priv->cfg_addr, addr); sync(); *value = pci_conv_32_to_size(in_le32(priv->cfg_data), offset, size); @@ -38,7 +38,7 @@ static int mpc85xx_pci_dm_write_config(struct udevice *dev, pci_dev_t bdf, struct mpc85xx_pci_priv *priv = dev_get_priv(dev); u32 addr; - addr = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; + addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset); out_be32(priv->cfg_addr, addr); sync(); out_le32(priv->cfg_data, pci_conv_size_to_32(0, value, offset, size)); From f146bd96e448200d05261e92738812ca6e37c372 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 26 Nov 2021 11:42:44 +0100 Subject: [PATCH 11/19] pci: msc01: Use PCI_CONF1_ADDRESS() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCI msc01 driver uses standard format of Config Address for PCI Configuration Mechanism #1 but with cleared Enable bit. So use new U-Boot macro PCI_CONF1_ADDRESS() with clearing PCI_CONF1_ENABLE bit and remove old custom driver address macros. Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- drivers/pci/pci_msc01.c | 7 ++----- include/msc01.h | 9 --------- 2 files changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/pci/pci_msc01.c b/drivers/pci/pci_msc01.c index 2f1b688fc32..8d363d60498 100644 --- a/drivers/pci/pci_msc01.c +++ b/drivers/pci/pci_msc01.c @@ -34,16 +34,13 @@ static int msc01_config_access(struct msc01_pci_controller *msc01, void *cfgdata = msc01->base + MSC01_PCI_CFGDATA_OFS; unsigned int bus = PCI_BUS(bdf); unsigned int dev = PCI_DEV(bdf); - unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf); + unsigned int func = PCI_FUNC(bdf); /* clear abort status */ __raw_writel(aborts, intstat); /* setup address */ - __raw_writel((bus << MSC01_PCI_CFGADDR_BNUM_SHF) | - (dev << MSC01_PCI_CFGADDR_DNUM_SHF) | - (devfn << MSC01_PCI_CFGADDR_FNUM_SHF) | - ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF), + __raw_writel((PCI_CONF1_ADDRESS(bus, dev, func, where) & ~PCI_CONF1_ENABLE), msc01->base + MSC01_PCI_CFGADDR_OFS); /* perform access */ diff --git a/include/msc01.h b/include/msc01.h index ec18a724eb9..20158123494 100644 --- a/include/msc01.h +++ b/include/msc01.h @@ -71,15 +71,6 @@ #define MSC01_PCI_INTSTAT_MA_SHF 7 #define MSC01_PCI_INTSTAT_MA_MSK (0x1 << MSC01_PCI_INTSTAT_MA_SHF) -#define MSC01_PCI_CFGADDR_BNUM_SHF 16 -#define MSC01_PCI_CFGADDR_BNUM_MSK (0xff << MSC01_PCI_CFGADDR_BNUM_SHF) -#define MSC01_PCI_CFGADDR_DNUM_SHF 11 -#define MSC01_PCI_CFGADDR_DNUM_MSK (0x1f << MSC01_PCI_CFGADDR_DNUM_SHF) -#define MSC01_PCI_CFGADDR_FNUM_SHF 8 -#define MSC01_PCI_CFGADDR_FNUM_MSK (0x3 << MSC01_PCI_CFGADDR_FNUM_SHF) -#define MSC01_PCI_CFGADDR_RNUM_SHF 2 -#define MSC01_PCI_CFGADDR_RNUM_MSK (0x3f << MSC01_PCI_CFGADDR_RNUM_SHF) - #define MSC01_PCI_HEAD0_VENDORID_SHF 0 #define MSC01_PCI_HEAD0_DEVICEID_SHF 16 From d0dd49f92937f7aa76231908aafbf21f55dc5376 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 26 Nov 2021 11:42:45 +0100 Subject: [PATCH 12/19] pci: mvebu: Use PCI_CONF1_EXT_ADDRESS() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCI mvebu driver uses extended format of Config Address for PCI Configuration Mechanism #1. So use new U-Boot macro PCI_CONF1_EXT_ADDRESS() and remove old custom driver address macros. Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- drivers/pci/pci_mvebu.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index 9248cbc294c..18f79d249c7 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -46,15 +46,6 @@ #define PCIE_WIN5_BASE_OFF 0x1884 #define PCIE_WIN5_REMAP_OFF 0x188c #define PCIE_CONF_ADDR_OFF 0x18f8 -#define PCIE_CONF_ADDR_EN BIT(31) -#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) -#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) -#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) -#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) -#define PCIE_CONF_ADDR(b, d, f, reg) \ - (PCIE_CONF_BUS(b) | PCIE_CONF_DEV(d) | \ - PCIE_CONF_FUNC(f) | PCIE_CONF_REG(reg) | \ - PCIE_CONF_ADDR_EN) #define PCIE_CONF_DATA_OFF 0x18fc #define PCIE_MASK_OFF 0x1910 #define PCIE_MASK_ENABLE_INTS (0xf << 24) @@ -186,9 +177,9 @@ static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, * secondary bus with device number 1. */ if (busno == pcie->first_busno) - addr = PCIE_CONF_ADDR(pcie->sec_busno, 1, 0, offset); + addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset); else - addr = PCIE_CONF_ADDR(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset); + addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset); /* write address */ writel(addr, pcie->base + PCIE_CONF_ADDR_OFF); @@ -284,9 +275,9 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf, * secondary bus with device number 1. */ if (busno == pcie->first_busno) - addr = PCIE_CONF_ADDR(pcie->sec_busno, 1, 0, offset); + addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset); else - addr = PCIE_CONF_ADDR(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset); + addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset); /* write address */ writel(addr, pcie->base + PCIE_CONF_ADDR_OFF); From 86be29e9d985b57e03e2eede6394e0c1edc6660a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 26 Nov 2021 11:42:46 +0100 Subject: [PATCH 13/19] pci: tegra: Use PCI_CONF1_EXT_ADDRESS() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCI tegra driver uses extended format of Config Address for PCI Configuration Mechanism #1 but with cleared Enable bit. So use new U-Boot macro PCI_CONF1_EXT_ADDRESS() with clearing PCI_CONF1_ENABLE bit and remove old custom driver address function. Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- drivers/pci/pci_tegra.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index 9cb4414836f..fc05ee00f1f 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -275,13 +275,6 @@ static void rp_writel(struct tegra_pcie_port *port, unsigned long value, writel(value, port->regs.start + offset); } -static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where) -{ - return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) | - (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) | - (where & 0xfc); -} - static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf, int where, unsigned long *address) { @@ -305,7 +298,9 @@ static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf, return -EFAULT; #endif - *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where); + *address = pcie->cs.start + + (PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), + PCI_FUNC(bdf), where) & ~PCI_CONF1_ENABLE); return 0; } } From f031f07f3abe2c611b03d733f23b6fd459d9d6dd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 26 Nov 2021 11:42:47 +0100 Subject: [PATCH 14/19] pci: fsl: Use PCI_CONF1_EXT_ADDRESS() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCI fsl driver uses extended format of Config Address for PCI Configuration Mechanism #1. So use new U-Boot macro PCI_CONF1_EXT_ADDRESS(). Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- drivers/pci/pcie_fsl.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 3c2a2a47611..cc6efdd5b46 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -58,8 +58,9 @@ static int fsl_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, return 0; } - bdf = bdf - PCI_BDF(dev_seq(bus), 0, 0); - val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; + val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus), + PCI_DEV(bdf), PCI_FUNC(bdf), + offset); out_be32(®s->cfg_addr, val); sync(); @@ -94,8 +95,9 @@ static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf, if (fsl_pcie_addr_valid(pcie, bdf)) return 0; - bdf = bdf - PCI_BDF(dev_seq(bus), 0, 0); - val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; + val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus), + PCI_DEV(bdf), PCI_FUNC(bdf), + offset); out_be32(®s->cfg_addr, val); sync(); From 022d43bdfb3e8064097666a7d8ddd4670a8b530f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 26 Nov 2021 11:42:48 +0100 Subject: [PATCH 15/19] pci: mediatek: Use PCI_CONF1_EXT_ADDRESS() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCI mediatek driver uses extended format of Config Address for PCI Configuration Mechanism #1 but with cleared Enable bit. So use new U-Boot macro PCI_CONF1_EXT_ADDRESS() with clearing PCI_CONF1_ENABLE bit and remove old custom driver address macros. Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- drivers/pci/pcie_mediatek.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/pci/pcie_mediatek.c b/drivers/pci/pcie_mediatek.c index f5556713878..051a3bc9693 100644 --- a/drivers/pci/pcie_mediatek.c +++ b/drivers/pci/pcie_mediatek.c @@ -41,10 +41,6 @@ #define PCIE_BAR_ENABLE BIT(0) #define PCIE_REVISION_ID BIT(0) #define PCIE_CLASS_CODE (0x60400 << 8) -#define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \ - ((((regn) >> 8) & GENMASK(3, 0)) << 24)) -#define PCIE_CONF_ADDR(regn, bdf) \ - (PCIE_CONF_REG(regn) | (bdf)) /* MediaTek specific configuration registers */ #define PCIE_FTS_NUM 0x70c @@ -147,8 +143,11 @@ static int mtk_pcie_config_address(const struct udevice *udev, pci_dev_t bdf, uint offset, void **paddress) { struct mtk_pcie *pcie = dev_get_priv(udev); + u32 val; - writel(PCIE_CONF_ADDR(offset, bdf), pcie->base + PCIE_CFG_ADDR); + val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), + PCI_FUNC(bdf), offset) & ~PCI_CONF1_ENABLE; + writel(val, pcie->base + PCIE_CFG_ADDR); *paddress = pcie->base + PCIE_CFG_DATA + (offset & 3); return 0; @@ -330,7 +329,6 @@ static void mtk_pcie_port_free(struct mtk_pcie_port *port) static int mtk_pcie_startup_port(struct mtk_pcie_port *port) { struct mtk_pcie *pcie = port->pcie; - u32 slot = PCI_DEV(port->slot << 11); u32 val; int err; @@ -357,13 +355,14 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port) writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS); /* configure FC credit */ - writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, slot), - pcie->base + PCIE_CFG_ADDR); + val = PCI_CONF1_EXT_ADDRESS(0, port->slot, 0, PCIE_FC_CREDIT) & ~PCI_CONF1_ENABLE; + writel(val, pcie->base + PCIE_CFG_ADDR); clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FC_CREDIT_MASK, PCIE_FC_CREDIT_VAL(0x806c)); /* configure RC FTS number to 250 when it leaves L0s */ - writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, slot), pcie->base + PCIE_CFG_ADDR); + val = PCI_CONF1_EXT_ADDRESS(0, port->slot, 0, PCIE_FTS_NUM) & ~PCI_CONF1_ENABLE; + writel(val, pcie->base + PCIE_CFG_ADDR); clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FTS_NUM_MASK, PCIE_FTS_NUM_L0(0x50)); From 7fabaa5313352a563568504a8354aaf11c1af85a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 26 Nov 2021 11:42:49 +0100 Subject: [PATCH 16/19] pci: sh7780: Use PCI_CONF1_ADDRESS() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCI sh7780 driver uses standard format of Config Address for PCI Configuration Mechanism #1. So use new U-Boot macro PCI_CONF1_ADDRESS(). Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- drivers/pci/pci_sh7780.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pci_sh7780.c b/drivers/pci/pci_sh7780.c index 06d711a6cb9..7533286c015 100644 --- a/drivers/pci/pci_sh7780.c +++ b/drivers/pci/pci_sh7780.c @@ -34,9 +34,9 @@ int pci_sh4_read_config_dword(struct pci_controller *hose, pci_dev_t dev, int offset, u32 *value) { - u32 par_data = 0x80000000 | dev; + u32 par_data = PCI_CONF1_ADDRESS(PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), offset); - p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR); + p4_out(par_data, SH7780_PCIPAR); *value = p4_in(SH7780_PCIPDR); return 0; @@ -45,9 +45,9 @@ int pci_sh4_read_config_dword(struct pci_controller *hose, int pci_sh4_write_config_dword(struct pci_controller *hose, pci_dev_t dev, int offset, u32 value) { - u32 par_data = 0x80000000 | dev; + u32 par_data = PCI_CONF1_ADDRESS(PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), offset); - p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR); + p4_out(par_data, SH7780_PCIPAR); p4_out(value, SH7780_PCIPDR); return 0; } From 7598759d194e09a8301f2912739feda9cb7dcb70 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 26 Nov 2021 11:42:50 +0100 Subject: [PATCH 17/19] x86: pci: Use PCI_CONF1_ADDRESS() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit x86 platform uses standard format of Config Address for PCI Configuration Mechanism #1. So use new U-Boot macro PCI_CONF1_ADDRESS(). Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- arch/x86/cpu/pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c index d4f9290ca73..8a992ed8233 100644 --- a/arch/x86/cpu/pci.c +++ b/arch/x86/cpu/pci.c @@ -20,7 +20,7 @@ int pci_x86_read_config(pci_dev_t bdf, uint offset, ulong *valuep, enum pci_size_t size) { - outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR); + outl(PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset), PCI_REG_ADDR); switch (size) { case PCI_SIZE_8: *valuep = inb(PCI_REG_DATA + (offset & 3)); @@ -39,7 +39,7 @@ int pci_x86_read_config(pci_dev_t bdf, uint offset, ulong *valuep, int pci_x86_write_config(pci_dev_t bdf, uint offset, ulong value, enum pci_size_t size) { - outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR); + outl(PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset), PCI_REG_ADDR); switch (size) { case PCI_SIZE_8: outb(value, PCI_REG_DATA + (offset & 3)); From c49f1fa8927340e7e3ea19f6ec6164510f9cd737 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 26 Nov 2021 11:42:51 +0100 Subject: [PATCH 18/19] m68k: mcf5445x: pci: Use PCI_CONF1_ADDRESS() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit mcf5445x platform uses standard format of Config Address for PCI Configuration Mechanism #1. So use new U-Boot macro PCI_CONF1_ADDRESS(). Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- arch/m68k/cpu/mcf5445x/pci.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/m68k/cpu/mcf5445x/pci.c b/arch/m68k/cpu/mcf5445x/pci.c index af02c4934c9..d487468d0bf 100644 --- a/arch/m68k/cpu/mcf5445x/pci.c +++ b/arch/m68k/cpu/mcf5445x/pci.c @@ -26,12 +26,11 @@ int pci_##rw##_cfg_##size(struct pci_controller *hose, \ pci_dev_t dev, int offset, type val) \ { \ - u32 addr = 0; \ - u16 cfg_type = 0; \ - addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \ + u32 addr = PCI_CONF1_ADDRESS(PCI_BUS(dev), PCI_DEV(dev), \ + PCI_FUNC(dev), offset); \ out_be32(hose->cfg_addr, addr); \ cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ - out_be32(hose->cfg_addr, addr & 0x7fffffff); \ + out_be32(hose->cfg_addr, addr & ~PCI_CONF1_ENABLE); \ return 0; \ } From 2a67bf65dd6c362487f416878348398d1842ae6b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 26 Nov 2021 11:42:52 +0100 Subject: [PATCH 19/19] pci: sh7751: Fix access to config space via PCI_CONF1_ADDRESS() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit sh7751 platform uses standard format of Config Address for PCI Configuration Mechanism #1. Commit 72c2f4acd76f ("pci: sh7751: Convert to DM and DT probing") which did conversion of PCI sh7751 driver to DM, broke access to config space as that commit somehow swapped device and function bits in config address. Fix all these issues by using new U-Boot macro PCI_CONF1_ADDRESS() which calculates Config Address correctly. Also remove nonsense function sh7751_pci_addr_valid() which was introduced in commit 72c2f4acd76f ("pci: sh7751: Convert to DM and DT probing") probably due to workarounded issues with mixing/swapping device and function bits of config address which probably resulted in non-working access to some devices. With correct composing of config address there should not be such issue anymore. Signed-off-by: Pali Rohár Fixes: 72c2f4acd76f ("pci: sh7751: Convert to DM and DT probing") Cc: Marek Vasut Reviewed-by: Simon Glass --- drivers/pci/pci_sh7751.c | 29 ++--------------------------- 1 file changed, 2 insertions(+), 27 deletions(-) diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c index e110550c71c..d514c040344 100644 --- a/drivers/pci/pci_sh7751.c +++ b/drivers/pci/pci_sh7751.c @@ -74,33 +74,13 @@ #define p4_in(addr) (*addr) #define p4_out(data, addr) (*addr) = (data) -static int sh7751_pci_addr_valid(pci_dev_t d, uint offset) -{ - if (PCI_FUNC(d)) - return -EINVAL; - - return 0; -} - -static u32 get_bus_address(const struct udevice *dev, pci_dev_t bdf, u32 offset) -{ - return BIT(31) | (PCI_DEV(bdf) << 8) | (offset & ~3); -} - static int sh7751_pci_read_config(const struct udevice *dev, pci_dev_t bdf, uint offset, ulong *value, enum pci_size_t size) { u32 addr, reg; - int ret; - ret = sh7751_pci_addr_valid(bdf, offset); - if (ret) { - *value = pci_get_ff(size); - return 0; - } - - addr = get_bus_address(dev, bdf, offset); + addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset); p4_out(addr, SH7751_PCIPAR); reg = p4_in(SH7751_PCIPDR); *value = pci_conv_32_to_size(reg, offset, size); @@ -113,13 +93,8 @@ static int sh7751_pci_write_config(struct udevice *dev, pci_dev_t bdf, enum pci_size_t size) { u32 addr, reg, old; - int ret; - ret = sh7751_pci_addr_valid(bdf, offset); - if (ret) - return ret; - - addr = get_bus_address(dev, bdf, offset); + addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset); p4_out(addr, SH7751_PCIPAR); old = p4_in(SH7751_PCIPDR); reg = pci_conv_size_to_32(old, value, offset, size);