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https://source.denx.de/u-boot/u-boot.git
synced 2026-05-06 05:06:13 +02:00
remoteproc: renesas: Add Renesas R-Car Gen5 remote processor driver
Add R-Car Gen5 RSIP controller remoteproc driver capable of starting the SCP, Cortex-R52 and Cortex-A720 cores in Renesas R-Car R8A78000 X5H SoC. The SCP core is started by releasing the core from reset, the Cortex-R52 and Cortex-A720 are started using the SCP SCMI call. The entry point for SCP core is fixed to its STCM, entry points for Cortex-R52 and Cortex-A720 are set during rproc load. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut
parent
8528f2ed20
commit
9f71b271db
@ -48,6 +48,15 @@ config REMOTEPROC_RENESAS_APMU
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Say 'y' here to add support for Renesas R-Car Gen4 Cortex-R52
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processor via the remoteproc framework.
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config REMOTEPROC_RENESAS_RSIP
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bool "Support for Renesas R-Car Gen5 RSIP start of SCP/CR52/CA720 processors"
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select REMOTEPROC
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depends on ARCH_RENESAS && RCAR_GEN5 && DM && OF_CONTROL
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help
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Say 'y' here to add support for Renesas R-Car Gen5 RSIP
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start of SCP, Cortex-R52 and Cortex-A720 processors via
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the remoteproc framework.
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config REMOTEPROC_SANDBOX
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bool "Support for Test processor for Sandbox"
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select REMOTEPROC
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@ -11,6 +11,7 @@ obj-$(CONFIG_K3_SYSTEM_CONTROLLER) += k3_system_controller.o
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obj-$(CONFIG_REMOTEPROC_ADI_SC5XX) += adi_sc5xx_rproc.o
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obj-$(CONFIG_REMOTEPROC_IMX) += imx_rproc.o
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obj-$(CONFIG_REMOTEPROC_RENESAS_APMU) += renesas_apmu.o
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obj-$(CONFIG_REMOTEPROC_RENESAS_RSIP) += renesas_rsip.o
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obj-$(CONFIG_REMOTEPROC_SANDBOX) += sandbox_testproc.o
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obj-$(CONFIG_REMOTEPROC_STM32_COPRO) += stm32_copro.o
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obj-$(CONFIG_REMOTEPROC_TI_K3_ARM64) += ti_k3_arm64_rproc.o
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358
drivers/remoteproc/renesas_rsip.c
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358
drivers/remoteproc/renesas_rsip.c
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@ -0,0 +1,358 @@
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2026 Renesas Electronics Corp.
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*/
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#include <asm/io.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <errno.h>
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#include <hang.h>
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#include <linux/iopoll.h>
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#include <linux/sizes.h>
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#include <malloc.h>
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#include <remoteproc.h>
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/* R-Car X5H contains 1 SCP core, 6 lockstep Cortex-R52 and 32 Cortex-A720AE cores. */
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#define RCAR5_SCP_CORES 1
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#define RCAR5_CR52_CORES 12
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#define RCAR5_CA720_CORES 32
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#define SCP_BASE 0xc1340000
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#define SCP_CPUWAIT (SCP_BASE + 0x30)
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#define SCP_CPUWAIT_WAIT BIT(0)
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#define SCP_STCM 0xc1000000
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struct scp_scmi_shmem {
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u32 reserved0;
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u32 status;
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u64 reserved1;
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u32 flags;
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u32 length;
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u32 message_header;
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u8 payload[];
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};
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struct scp_scmi_pd_power_state_set_a2p {
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u32 flags;
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u32 domain_id;
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u32 power_state;
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u32 boot_addr;
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};
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/* The addresses in range 0x08000000..0x1fffffff are incremented by 0xa0000000 */
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#define MFIS_COMMON_BASE 0xb89e1000
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#define MFIS_SCP_WACNTR (MFIS_COMMON_BASE + 0x904)
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/* The addresses in range 0x08000000..0x1fffffff are incremented by 0xa0000000 */
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#define MFIS_SCP_BASE 0xb8840000
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#define MFIS_SCP_REICR8 (MFIS_SCP_BASE + 0x28004)
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#define MFIS_SCP_CODEVALUE 0xacc00000
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#define MFIS_SCP_REG_MASK GENMASK(19, 0)
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/**
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* mfis_scp_unlock() - Release MFIS-SCP lock
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* @lck: MFIS lock register
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*/
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static void mfis_scp_unlock(const u32 lck)
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{
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writel(MFIS_SCP_CODEVALUE | (lck & MFIS_SCP_REG_MASK), MFIS_SCP_WACNTR);
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}
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#define SCP_SCMI_SHMEM_AREA09 0xc1060800
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#define SCP_SCMI_STATUS_MASK 0x3
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#define SCP_SCMI_STATUS_FREE 0x1
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/**
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* scp_wait_fw_free() - Wait for SCP channel to be free for communication
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*/
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static void scp_wait_fw_free(void)
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{
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struct scp_scmi_shmem *shmem = (struct scp_scmi_shmem *)SCP_SCMI_SHMEM_AREA09;
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while ((shmem->status & SCP_SCMI_STATUS_MASK) != SCP_SCMI_STATUS_FREE)
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mdelay(1);
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}
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/**
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* scp_send_interrupt() - Raise interrupt on SCP side
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*/
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static void scp_send_interrupt(void)
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{
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mfis_scp_unlock(MFIS_SCP_REICR8);
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/* Send SCP IRQ */
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writel(1, MFIS_SCP_REICR8);
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}
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/* SCMI power domain IDs */
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#define SCMI_PD_CORE_RT_CORE00 117
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#define SCMI_PD_CORE_AP_CORE00 129
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/*
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* FIXME: This is custom extension to the SCMI PD protocol:
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* - Protocol 0x11 (PD)
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* - Command 0x11 (POWER_STATE_SET_BOOTADDR - custom)
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* This must be removed when proper upstream SCP port exists
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*/
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#define SCMI_PD_POWER_STATE_SET_BOOTADDR 0x4411
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/**
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* scp_cpu_core_start() - Boot CPU core by invoking SCP via SCMI
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* @core: CPU core to boot
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* @ep: Entry point
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*/
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static void scp_cpu_core_start(const u32 core, const u32 ep)
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{
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struct scp_scmi_shmem *shmem = (struct scp_scmi_shmem *)SCP_SCMI_SHMEM_AREA09;
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struct scp_scmi_pd_power_state_set_a2p scmi_parameter = {
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.flags = 1, /* Asynchronous power transition using APMU */
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.domain_id = core,
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.power_state = 0, /* Power on */
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.boot_addr = ep,
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};
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u32 status;
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/* Wait for SCP to be free, then set it busy */
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scp_wait_fw_free();
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shmem->status &= ~SCP_SCMI_STATUS_FREE;
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/* Set up the message and copy it to SHMEM */
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shmem->message_header = SCMI_PD_POWER_STATE_SET_BOOTADDR;
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memcpy(shmem->payload, &scmi_parameter, sizeof(scmi_parameter));
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shmem->length = sizeof(shmem->message_header) + sizeof(scmi_parameter);
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/* Send message to SCP and wait for completion */
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scp_send_interrupt();
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scp_wait_fw_free();
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/* Read back the result */
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status = readl((uintptr_t)shmem->payload);
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if (status)
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printf("SCP POWER_STATE_SET failed, status=0x%x\n", status);
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}
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/**
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* struct renesas_rsip_rproc_privdata - remote processor private data
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* @core_id: CPU core id
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* @ep: Entry point
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*/
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struct renesas_rsip_rproc_privdata {
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ulong core_id;
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ulong ep;
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};
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/**
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* renesas_rsip_rproc_load() - Load the remote processor
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* @dev: corresponding remote processor device
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* @addr: Address in memory where image is stored
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* @size: Size in bytes of the image
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*
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* Return: 0 if all went ok, else corresponding -ve error
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*/
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static int renesas_rsip_rproc_load(struct udevice *dev, ulong addr, ulong size)
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{
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struct renesas_rsip_rproc_privdata *priv = dev_get_priv(dev);
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priv->ep = addr;
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if (priv->core_id == 0) /* SCP */
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memcpy((void *)SCP_STCM, (void *)addr, size);
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return 0;
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}
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/**
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* renesas_rsip_rproc_start() - Start the remote processor
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* @dev: corresponding remote processor device
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*
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* Return: 0 if all went ok, else corresponding -ve error
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*/
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static int renesas_rsip_rproc_start(struct udevice *dev)
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{
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struct renesas_rsip_rproc_privdata *priv = dev_get_priv(dev);
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int scmi_core;
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if (priv->core_id == 0) {
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/* SCP */
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clrbits_le32(SCP_CPUWAIT, SCP_CPUWAIT_WAIT);
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return 0;
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} else if (priv->core_id >= RCAR5_SCP_CORES &&
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priv->core_id < RCAR5_SCP_CORES + RCAR5_CR52_CORES) {
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/* CR52 */
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scmi_core = priv->core_id - RCAR5_SCP_CORES +
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SCMI_PD_CORE_RT_CORE00;
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} else if (priv->core_id >= RCAR5_SCP_CORES + RCAR5_CR52_CORES &&
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priv->core_id < RCAR5_SCP_CORES + RCAR5_CR52_CORES + RCAR5_CA720_CORES) {
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/* CA720 */
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scmi_core = priv->core_id - RCAR5_SCP_CORES - RCAR5_CR52_CORES +
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SCMI_PD_CORE_AP_CORE00;
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}
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scp_cpu_core_start(scmi_core, priv->ep);
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return 0;
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}
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/**
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* renesas_rsip_rproc_stop() - Stop the remote processor
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* @dev: corresponding remote processor device
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*
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* Return: 0 if all went ok, else corresponding -ve error
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*/
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static int renesas_rsip_rproc_stop(struct udevice *dev)
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{
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struct renesas_rsip_rproc_privdata *priv = dev_get_priv(dev);
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if (priv->core_id == 0) { /* SCP */
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setbits_le32(SCP_CPUWAIT, SCP_CPUWAIT_WAIT);
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return 0;
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}
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return 0;
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}
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/**
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* renesas_rsip_rproc_reset() - Reset the remote processor
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* @dev: corresponding remote processor device
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*
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* Return: 0 if all went ok, else corresponding -ve error
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*/
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static int renesas_rsip_rproc_reset(struct udevice *dev)
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{
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renesas_rsip_rproc_stop(dev);
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renesas_rsip_rproc_start(dev);
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return 0;
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}
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/**
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* renesas_rsip_rproc_is_running() - Is the remote processor running
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* @dev: corresponding remote processor device
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*
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* Return: 0 if the remote processor is running, 1 otherwise
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*/
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static int renesas_rsip_rproc_is_running(struct udevice *dev)
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{
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/* We assume the core is stopped. */
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return 1;
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}
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/**
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* renesas_rsip_rproc_init() - Initialize the remote processor
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* @dev: corresponding remote processor device
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*
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* Return: 0 if all went ok, else corresponding -ve error
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*/
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static int renesas_rsip_rproc_init(struct udevice *dev)
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{
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return 0;
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}
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/**
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* renesas_rsip_rproc_device_to_virt() - Convert device address to virtual address
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* @dev: corresponding remote processor device
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* @da: device address
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* @size: Size of the memory region @da is pointing to
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* @is_iomem: optional pointer filled in to indicate if @da is iomapped memory
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*
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* Return: converted virtual address
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*/
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static void *renesas_rsip_rproc_device_to_virt(struct udevice *dev, ulong da,
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ulong size, bool *is_iomem)
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{
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return (void *)da;
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}
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static const struct dm_rproc_ops renesas_rsip_rproc_ops = {
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.init = renesas_rsip_rproc_init,
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.load = renesas_rsip_rproc_load,
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.start = renesas_rsip_rproc_start,
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.stop = renesas_rsip_rproc_stop,
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.reset = renesas_rsip_rproc_reset,
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.is_running = renesas_rsip_rproc_is_running,
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.device_to_virt = renesas_rsip_rproc_device_to_virt,
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};
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/**
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* renesas_rsip_rproc_of_to_plat() - Convert OF data to platform data
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* @dev: corresponding remote processor device
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*
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* Return: 0 if all went ok, else corresponding -ve error
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*/
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static int renesas_rsip_rproc_of_to_plat(struct udevice *dev)
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{
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struct renesas_rsip_rproc_privdata *priv = dev_get_priv(dev);
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priv->core_id = dev_get_driver_data(dev);
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return 0;
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}
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U_BOOT_DRIVER(renesas_rsip_core) = {
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.name = "rcar-rsip-core",
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.id = UCLASS_REMOTEPROC,
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.ops = &renesas_rsip_rproc_ops,
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.of_to_plat = renesas_rsip_rproc_of_to_plat,
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.priv_auto = sizeof(struct renesas_rsip_rproc_privdata),
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};
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/**
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* renesas_rsip_rproc_bind() - Bind rproc driver to each core control
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* @dev: corresponding remote processor parent device
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*
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* Return: 0 if all went ok, else corresponding -ve error
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*/
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static int renesas_rsip_rproc_bind(struct udevice *parent)
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{
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ofnode pnode = dev_ofnode(parent);
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struct udevice *cdev;
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struct driver *cdrv;
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char name[32];
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ulong i;
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int ret;
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cdrv = lists_driver_lookup_name("rcar-rsip-core");
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if (!cdrv)
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return -ENOENT;
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/* Singleton SCP core is core 0 */
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ret = device_bind_with_driver_data(parent, cdrv,
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strdup("rcar-rsip-scp"),
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0, pnode, &cdev);
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if (ret)
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return ret;
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/* Cores 1..13 are Cortex-R52 */
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for (i = 0; i < RCAR5_CR52_CORES; i++) {
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snprintf(name, sizeof(name), "rcar-rsip-cr.%ld", i);
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ret = device_bind_with_driver_data(parent, cdrv, strdup(name),
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i + RCAR5_SCP_CORES, pnode,
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&cdev);
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if (ret)
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return ret;
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}
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/* Cores 14..46 are Cortex-A720 */
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for (i = 0; i < RCAR5_CA720_CORES; i++) {
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snprintf(name, sizeof(name), "rcar-rsip-ca.%ld", i);
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ret = device_bind_with_driver_data(parent, cdrv, strdup(name),
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i + RCAR5_SCP_CORES + RCAR5_CR52_CORES,
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pnode, &cdev);
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if (ret)
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return ret;
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}
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return 0;
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}
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static const struct udevice_id renesas_rsip_rproc_ids[] = {
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{ .compatible = "renesas,r8a78000-rproc" },
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{ }
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};
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U_BOOT_DRIVER(renesas_rsip_rproc) = {
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.name = "rcar-rsip-rproc",
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.of_match = renesas_rsip_rproc_ids,
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.id = UCLASS_NOP,
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.bind = renesas_rsip_rproc_bind,
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};
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