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ppc/85xx: add boot from NAND/eSDHC/eSPI support

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The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.

For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.

When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NAND loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.

When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.

The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Mingkai Hu 2009-09-11 14:19:10 +08:00 committed by Tom Rix
parent 8d82308305
commit 9f3243612c
5 changed files with 183 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
cpu/mpc85xx/cpu_init.c
View File

@ -291,6 +291,25 @@ int cpu_init_r(void)
asm("msync;isync");
cache_ctl = l2cache->l2ctl;
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
if (cache_ctl & MPC85xx_L2CTL_L2E) {
/* Clear L2 SRAM memory-mapped base address */
out_be32(&l2cache->l2srbar0, 0x0);
out_be32(&l2cache->l2srbar1, 0x0);
/* set MBECCDIS=0, SBECCDIS=0 */
clrbits_be32(&l2cache->l2errdis,
(MPC85xx_L2ERRDIS_MBECC |
MPC85xx_L2ERRDIS_SBECC));
/* set L2E=0, L2SRAM=0 */
clrbits_be32(&l2cache->l2ctl,
(MPC85xx_L2CTL_L2E |
MPC85xx_L2CTL_L2SRAM_ENTIRE));
}
#endif
l2siz_field = (cache_ctl >> 28) & 0x3;
switch (l2siz_field) {

23
cpu/mpc85xx/start.S
View File

@ -57,10 +57,12 @@
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
#ifndef CONFIG_NAND_SPL
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
GOT_ENTRY(_end_of_vectors)
GOT_ENTRY(transfer_to_handler)
#endif
GOT_ENTRY(__init_end)
GOT_ENTRY(_end)
@ -239,10 +241,11 @@ _start_e500:
#endif /* CONFIG_MPC8569 */
/* create a temp mapping in AS=1 to the 4M boot window */
lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
#ifndef CONFIG_SYS_RAMBOOT
/* create a temp mapping in AS=1 to the 4M boot window */
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
@ -252,6 +255,20 @@ _start_e500:
/* The 85xx has the default boot window 0xff800000 - 0xffffffff */
lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
#else
/*
* create a temp mapping in AS=1 to the 1M TEXT_BASE space, the main
* image has been relocated to TEXT_BASE on the second stage.
*/
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h
ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l
lis r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
ori r9,r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
#endif
mtspr MAS0,r6
mtspr MAS1,r7
@ -363,6 +380,7 @@ _start_cont:
bl board_init_f
isync
#ifndef CONFIG_NAND_SPL
. = EXC_OFF_SYS_RESET
.globl _start_of_vectors
_start_of_vectors:
@ -817,6 +835,7 @@ in32:
in32r:
lwbrx r3,r0,r3
blr
#endif /* !CONFIG_NAND_SPL */
/*------------------------------------------------------------------------------*/
@ -1001,6 +1020,7 @@ clear_bss:
mr r4,r10 /* Destination Address */
bl board_init_r
#ifndef CONFIG_NAND_SPL
/*
* Copy exception vector code to low memory
*
@ -1154,3 +1174,4 @@ setup_ivors:
#include "fixed_ivor.S"
blr
#endif /* !CONFIG_NAND_SPL */

2
cpu/mpc85xx/tlb.c
View File

@ -55,6 +55,7 @@ void init_tlbs(void)
return ;
}
#ifndef CONFIG_NAND_SPL
void set_tlb(u8 tlb, u32 epn, u64 rpn,
u8 perms, u8 wimge,
u8 ts, u8 esel, u8 tsize, u8 iprot)
@ -209,3 +210,4 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
*/
return memsize_in_meg;
}
#endif /* !CONFIG_NAND_SPL */

138
cpu/mpc85xx/u-boot-nand.lds Normal file
View File

@ -0,0 +1,138 @@
/*
* Copyright 2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
PHDRS
{
text PT_LOAD;
bss PT_LOAD;
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
*(.text)
*(.fixup)
*(.got1)
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
} :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
.bootpg ADDR(.text) - 0x1000 :
{
cpu/mpc85xx/start.o (.bootpg)
} :text = 0xffff
. = ADDR(.text) + 0x80000;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
} :bss
. = ALIGN(4);
_end = . ;
PROVIDE (end = .);
}

2
drivers/misc/fsl_law.c
View File

@ -74,6 +74,7 @@ int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
return idx;
}
#ifndef CONFIG_NAND_SPL
int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
u32 idx;
@ -166,6 +167,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
return 0;
}
#endif
void init_laws(void)
{