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riscv: mbv: Align DT with QEMU

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Align U-Boot with QEMU amd-microblaze-v-virt platform to be able to wire
it with CI.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Padmarao Begari <padmarao.begari@amd.com>
This commit is contained in:
Michal Simek 2024-10-23 08:06:40 +02:00 committed by Leo Yu-Chi Liang
parent bfdfc6c12e
commit 9d688e6da5
3 changed files with 19 additions and 29 deletions
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30
arch/riscv/dts/xilinx-mbv32.dts
View File

@ -20,7 +20,7 @@
cpus: cpus { cpus: cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
timebase-frequency = <102000000>; timebase-frequency = <100000000>;
cpu_0: cpu@0 { cpu_0: cpu@0 {
compatible = "amd,mbv32", "riscv"; compatible = "amd,mbv32", "riscv";
device_type = "cpu"; device_type = "cpu";
@ -28,7 +28,7 @@
riscv,isa = "rv32imafdc"; riscv,isa = "rv32imafdc";
i-cache-size = <32768>; i-cache-size = <32768>;
d-cache-size = <32768>; d-cache-size = <32768>;
clock-frequency = <102000000>; clock-frequency = <100000000>;
cpu0_intc: interrupt-controller { cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc"; compatible = "riscv,cpu-intc";
interrupt-controller; interrupt-controller;
@ -46,15 +46,15 @@
stdout-path = "serial0:115200n8"; stdout-path = "serial0:115200n8";
}; };
memory@20000000 { memory@80000000 {
device_type = "memory"; device_type = "memory";
reg = <0x20000000 0x20000000>; reg = <0x80000000 0x40000000>;
}; };
clk102: clock { clk100: clock {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>; #clock-cells = <0>;
clock-frequency = <102000000>; clock-frequency = <100000000>;
}; };
axi: axi { axi: axi {
@ -77,30 +77,20 @@
compatible = "xlnx,xps-timer-1.00.a"; compatible = "xlnx,xps-timer-1.00.a";
reg = <0x41c00000 0x1000>; reg = <0x41c00000 0x1000>;
interrupt-parent = <&axi_intc>; interrupt-parent = <&axi_intc>;
interrupts = <1 2>; interrupts = <0 2>;
bootph-all; bootph-all;
xlnx,one-timer-only = <0>; xlnx,one-timer-only = <0>;
clock-names = "s_axi_aclk"; clock-names = "s_axi_aclk";
clocks = <&clk102>; clocks = <&clk100>;
};
xlnx_timer1: timer@41c20000 {
compatible = "xlnx,xps-timer-1.00.a";
reg = <0x41c20000 0x1000>;
interrupt-parent = <&axi_intc>;
interrupts = <0 2>;
xlnx,one-timer-only = <0>;
clock-names = "s_axi_aclk";
clocks = <&clk102>;
}; };
uart0: serial@40600000 { uart0: serial@40600000 {
compatible = "xlnx,xps-uartlite-1.00.a"; compatible = "xlnx,xps-uartlite-1.00.a";
reg = <0x40600000 0x1000>; reg = <0x40600000 0x1000>;
interrupt-parent = <&axi_intc>; interrupt-parent = <&axi_intc>;
interrupts = <2 2>; interrupts = <1 2>;
bootph-all; bootph-all;
clocks = <&clk102>; clocks = <&clk100>;
current-speed = <115200>; current-speed = <115200>;
xlnx,data-bits = <8>; xlnx,data-bits = <8>;
xlnx,use-parity = <0>; xlnx,use-parity = <0>;

6
board/xilinx/mbv/Kconfig
View File

@ -10,14 +10,14 @@ config SYS_CPU
default "generic" default "generic"
config TEXT_BASE config TEXT_BASE
default 0x21200000 default 0x81200000
config SPL_TEXT_BASE config SPL_TEXT_BASE
default 0x20000000 default 0x80000000
config SPL_OPENSBI_LOAD_ADDR config SPL_OPENSBI_LOAD_ADDR
hex hex
default 0x20200000 default 0x80200000
config BOARD_SPECIFIC_OPTIONS config BOARD_SPECIFIC_OPTIONS
def_bool y def_bool y

12
configs/xilinx_mbv32_defconfig
View File

@ -2,17 +2,17 @@ CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0xe00000 CONFIG_SYS_MALLOC_LEN=0xe00000
CONFIG_NR_DRAM_BANKS=1 CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x21200000 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000
CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32"
CONFIG_SPL_STACK=0x20200000 CONFIG_SPL_STACK=0x80200000
CONFIG_SPL_BSS_START_ADDR=0x24000000 CONFIG_SPL_BSS_START_ADDR=0x84000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SYS_LOAD_ADDR=0x20200000 CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL_SIZE_LIMIT=0x40000
CONFIG_SPL=y CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x40600000 CONFIG_DEBUG_UART_BASE=0x40600000
CONFIG_DEBUG_UART_CLOCK=1000000 CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_SYS_CLK_FREQ=100000000 CONFIG_SYS_CLK_FREQ=100000000
CONFIG_BOOT_SCRIPT_OFFSET=0x0 CONFIG_BOOT_SCRIPT_OFFSET=0x0
CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART=y
@ -20,7 +20,7 @@ CONFIG_TARGET_XILINX_MBV=y
# CONFIG_SPL_SMP is not set # CONFIG_SPL_SMP is not set
CONFIG_REMAKE_ELF=y CONFIG_REMAKE_ELF=y
CONFIG_FIT=y CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x20200000 CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
CONFIG_DISTRO_DEFAULTS=y CONFIG_DISTRO_DEFAULTS=y
CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y CONFIG_DISPLAY_BOARDINFO=y