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Merge patch series "board: BuS: Remove duplicate newlines"

Browse Source 
Drop all duplicate newlines from the board directory files.
This commit is contained in:
Tom Rini 2024-07-22 10:52:36 -06:00
commit 9b186f68af
103 changed files with 0 additions and 138 deletions
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1
board/BuS/eb_cpu5282/eb_cpu5282.c
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@ -181,5 +181,4 @@ void __led_set(led_id_t mask, int state)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/* EOF EB+MCF-EV123.c */ /* EOF EB+MCF-EV123.c */

1
board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
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@ -59,7 +59,6 @@ struct efi_capsule_update_info update_info = {
#endif /* EFI_HAVE_CAPSULE_SUPPORT */ #endif /* EFI_HAVE_CAPSULE_SUPPORT */
int board_early_init_f(void) int board_early_init_f(void)
{ {
init_uart_clk(2); init_uart_clk(2);

1
board/altera/arria5-socdk/qts/iocsr_config.h
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@ -691,5 +691,4 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x00004100, 0x00004100,
}; };
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ #endif /* __SOCFPGA_IOCSR_CONFIG_H__ */

1
board/altera/arria5-socdk/qts/pll_config.h
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@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 2 #define CFG_HPS_ALTERAGRP_MAINCLK 2
#define CFG_HPS_ALTERAGRP_DBGATCLK 3 #define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ #endif /* __SOCFPGA_PLL_CONFIG_H__ */

1
board/altera/cyclone5-socdk/qts/iocsr_config.h
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@ -655,5 +655,4 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x00004100, 0x00004100,
}; };
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ #endif /* __SOCFPGA_IOCSR_CONFIG_H__ */

1
board/altera/cyclone5-socdk/qts/pll_config.h
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@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 4 #define CFG_HPS_ALTERAGRP_MAINCLK 4
#define CFG_HPS_ALTERAGRP_DBGATCLK 4 #define CFG_HPS_ALTERAGRP_DBGATCLK 4
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ #endif /* __SOCFPGA_PLL_CONFIG_H__ */

1
board/aries/mcvevk/qts/iocsr_config.h
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@ -655,5 +655,4 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x00004000, 0x00004000,
}; };
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ #endif /* __SOCFPGA_IOCSR_CONFIG_H__ */

1
board/aries/mcvevk/qts/pll_config.h
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@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 3 #define CFG_HPS_ALTERAGRP_MAINCLK 3
#define CFG_HPS_ALTERAGRP_DBGATCLK 3 #define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ #endif /* __SOCFPGA_PLL_CONFIG_H__ */

1
board/armltd/vexpress64/pcie.c
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@ -109,7 +109,6 @@ static void xr3pci_setup_atr(void)
XR3_PCI_MEMSPACE64_SIZE, XR3_PCI_MEMSPACE64_SIZE,
XR3PCI_ATR_TRSLID_AXIMEMORY); XR3PCI_ATR_TRSLID_AXIMEMORY);
/* setup CPU to PCIe address translation table */ /* setup CPU to PCIe address translation table */
base = XR3_CONFIG_BASE + XR3PCI_ATR_AXI4_SLV0; base = XR3_CONFIG_BASE + XR3PCI_ATR_AXI4_SLV0;

1
board/cadence/xtfpga/xtfpga.c
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@ -23,7 +23,6 @@ DECLARE_GLOBAL_DATA_PTR;
* (Print information about the board to stdout.) * (Print information about the board to stdout.)
*/ */
#if defined(CONFIG_XTFPGA_LX60) #if defined(CONFIG_XTFPGA_LX60)
const char *board = "XT_AV60"; const char *board = "XT_AV60";
const char *description = "Avnet Xilinx LX60 FPGA Evaluation Board / "; const char *description = "Avnet Xilinx LX60 FPGA Evaluation Board / ";

5
board/cobra5272/flash.c
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@ -61,7 +61,6 @@ Done:
return; return;
} }
unsigned long flash_init(void) unsigned long flash_init(void)
{ {
int i, j; int i, j;
@ -112,7 +111,6 @@ unsigned long flash_init(void)
return size; return size;
} }
#define CMD_READ_ARRAY 0x00F0 #define CMD_READ_ARRAY 0x00F0
#define CMD_UNLOCK1 0x00AA #define CMD_UNLOCK1 0x00AA
#define CMD_UNLOCK2 0x0055 #define CMD_UNLOCK2 0x0055
@ -133,7 +131,6 @@ unsigned long flash_init(void)
#define ERR 2 #define ERR 2
#define TMO 4 #define TMO 4
int flash_erase(flash_info_t *info, int s_first, int s_last) int flash_erase(flash_info_t *info, int s_first, int s_last)
{ {
ulong result; ulong result;
@ -267,7 +264,6 @@ static int write_word(flash_info_t *info, ulong dest, ulong data)
if ((result & data) != data) if ((result & data) != data)
return ERR_NOT_ERASED; return ERR_NOT_ERASED;
/* /*
* Disable interrupts which might cause a timeout * Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are * here. Remember that our exception vectors are
@ -317,7 +313,6 @@ static int write_word(flash_info_t *info, ulong dest, ulong data)
return rc; return rc;
} }
int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{ {
ulong wp, data; ulong wp, data;

1
board/compulab/cm_fx6/cm_fx6.c
View File

@ -252,7 +252,6 @@ I2C_PADS(i2c2_pads,
PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL), PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
IMX_GPIO_NR(1, 6)); IMX_GPIO_NR(1, 6));
static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads) static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
{ {
int ret; int ret;

1
board/compulab/cm_fx6/common.h
View File

@ -31,6 +31,5 @@
#define CM_FX6_SATA_NRSTDLY IMX_GPIO_NR(6, 6) #define CM_FX6_SATA_NRSTDLY IMX_GPIO_NR(6, 6)
#define CM_FX6_SATA_PWLOSS_INT IMX_GPIO_NR(6, 31) #define CM_FX6_SATA_PWLOSS_INT IMX_GPIO_NR(6, 31)
void cm_fx6_set_usdhc_iomux(void); void cm_fx6_set_usdhc_iomux(void);
void cm_fx6_set_ecspi_iomux(void); void cm_fx6_set_ecspi_iomux(void);

1
board/congatec/cgtqmx8/cgtqmx8.c
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@ -371,7 +371,6 @@ void detail_board_ddr_info(void)
puts("\nDDR "); puts("\nDDR ");
} }
#ifdef CONFIG_OF_BOARD_SETUP #ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, struct bd_info *bd) int ft_board_setup(void *blob, struct bd_info *bd)
{ {

2
board/davinci/da8xxevm/omapl138_lcdk.c
View File

@ -167,7 +167,6 @@ int board_init(void)
/* address of boot parameters */ /* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
/* setup the SUSPSRC for ARM to control emulation suspend */ /* setup the SUSPSRC for ARM to control emulation suspend */
writel(readl(&davinci_syscfg_regs->suspsrc) & writel(readl(&davinci_syscfg_regs->suspsrc) &
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
@ -195,7 +194,6 @@ int board_init(void)
&davinci_emif_regs->ab2cr); /* CS3 */ &davinci_emif_regs->ab2cr); /* CS3 */
#endif #endif
#ifdef CONFIG_MMC_DAVINCI #ifdef CONFIG_MMC_DAVINCI
if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0) if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0)
return 1; return 1;

1
board/devboards/dbm-soc1/qts/iocsr_config.h
View File

@ -655,5 +655,4 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x00004000, 0x00004000,
}; };
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ #endif /* __SOCFPGA_IOCSR_CONFIG_H__ */

1
board/devboards/dbm-soc1/qts/pll_config.h
View File

@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 3 #define CFG_HPS_ALTERAGRP_MAINCLK 3
#define CFG_HPS_ALTERAGRP_DBGATCLK 3 #define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ #endif /* __SOCFPGA_PLL_CONFIG_H__ */

1
board/dhelectronics/dh_imx6/dh_imx6_spl.c
View File

@ -541,7 +541,6 @@ static int spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
return ret; return ret;
} }
/* DRAM */ /* DRAM */
static void dhcom_spl_dram_init(void) static void dhcom_spl_dram_init(void)
{ {

1
board/ebv/socrates/qts/iocsr_config.h
View File

@ -655,5 +655,4 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x00004000, 0x00004000,
}; };
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ #endif /* __SOCFPGA_IOCSR_CONFIG_H__ */

1
board/ebv/socrates/qts/pll_config.h
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@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 3 #define CFG_HPS_ALTERAGRP_MAINCLK 3
#define CFG_HPS_ALTERAGRP_DBGATCLK 3 #define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ #endif /* __SOCFPGA_PLL_CONFIG_H__ */

1
board/engicam/imx6q/imx6q.c
View File

@ -5,7 +5,6 @@
* Author: Jagan Teki <jagan@amarulasolutions.com> * Author: Jagan Teki <jagan@amarulasolutions.com>
*/ */
#include <asm/io.h> #include <asm/io.h>
#include <asm/gpio.h> #include <asm/gpio.h>
#include <linux/sizes.h> #include <linux/sizes.h>

5
board/freescale/common/cadmus.c
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@ -3,7 +3,6 @@
* Copyright 2004, 2011 Freescale Semiconductor. * Copyright 2004, 2011 Freescale Semiconductor.
*/ */
#include <config.h> #include <config.h>
#include <clock_legacy.h> #include <clock_legacy.h>
#include <linux/types.h> #include <linux/types.h>
@ -27,7 +26,6 @@ typedef struct cadmus_reg {
u_char cm_reserved[248]; /* Total 256 bytes */ u_char cm_reserved[248]; /* Total 256 bytes */
} cadmus_reg_t; } cadmus_reg_t;
unsigned int unsigned int
get_board_version(void) get_board_version(void)
{ {
@ -36,7 +34,6 @@ get_board_version(void)
return cadmus->cm_ver; return cadmus->cm_ver;
} }
unsigned long unsigned long
get_board_sys_clk(void) get_board_sys_clk(void)
{ {
@ -54,7 +51,6 @@ get_board_sys_clk(void)
} }
} }
unsigned int unsigned int
get_pci_slot(void) get_pci_slot(void)
{ {
@ -66,7 +62,6 @@ get_pci_slot(void)
return ((cadmus->cm_csr >> 6) & 0x3) + 1; return ((cadmus->cm_csr >> 6) & 0x3) + 1;
} }
unsigned int unsigned int
get_pci_dual(void) get_pci_dual(void)
{ {

4
board/freescale/common/cadmus.h
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@ -6,7 +6,6 @@
#ifndef __CADMUS_H_ #ifndef __CADMUS_H_
#define __CADMUS_H_ #define __CADMUS_H_
/* /*
* CADMUS Board System Register interface. * CADMUS Board System Register interface.
*/ */
@ -21,17 +20,14 @@ extern unsigned int get_board_version(void);
*/ */
extern unsigned long get_board_sys_clk(void); extern unsigned long get_board_sys_clk(void);
/* /*
* Returns 1 - 4, as found in the USER CSR[6:7] bits. * Returns 1 - 4, as found in the USER CSR[6:7] bits.
*/ */
extern unsigned int get_pci_slot(void); extern unsigned int get_pci_slot(void);
/* /*
* Returns PCI DUAL as found in CM_PCI[3]. * Returns PCI DUAL as found in CM_PCI[3].
*/ */
extern unsigned int get_pci_dual(void); extern unsigned int get_pci_dual(void);
#endif /* __CADMUS_H_ */ #endif /* __CADMUS_H_ */

3
board/freescale/common/eeprom.h
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@ -6,12 +6,10 @@
#ifndef __EEPROM_H_ #ifndef __EEPROM_H_
#define __EEPROM_H_ #define __EEPROM_H_
/* /*
* EEPROM Board System Register interface. * EEPROM Board System Register interface.
*/ */
/* /*
* CPU Board Revision * CPU Board Revision
*/ */
@ -29,5 +27,4 @@
*/ */
extern unsigned int get_cpu_board_revision(void); extern unsigned int get_cpu_board_revision(void);
#endif /* __CADMUS_H_ */ #endif /* __CADMUS_H_ */

2
board/freescale/common/fsl_validate.c
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@ -327,7 +327,6 @@ static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img)
} }
#endif #endif
/* This function return length of public key.*/ /* This function return length of public key.*/
static inline u32 get_key_len(struct fsl_secboot_img_priv *img) static inline u32 get_key_len(struct fsl_secboot_img_priv *img)
{ {
@ -858,7 +857,6 @@ static int secboot_init(struct fsl_secboot_img_priv **img_ptr)
return 0; return 0;
} }
/* haddr - Address of the header of image to be validated. /* haddr - Address of the header of image to be validated.
* arg_hash_str - Option hash string. If provided, this * arg_hash_str - Option hash string. If provided, this
* overrides the key hash in the SFP fuses. * overrides the key hash in the SFP fuses.

1
board/freescale/imx8mn_evk/ddr4_timing.c
View File

@ -787,7 +787,6 @@ struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0xd0000, 0x1 }, { 0xd0000, 0x1 },
}; };
/* P0 2D message block paremeter for training firmware */ /* P0 2D message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_2d_cfg[] = { struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 }, { 0xd0000, 0x0 },

2
board/freescale/imx8mn_evk/ddr4_timing_ld.c
View File

@ -765,7 +765,6 @@ struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0xd0000, 0x1 }, { 0xd0000, 0x1 },
}; };
/* P1 message block paremeter for training firmware */ /* P1 message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp1_cfg[] = { struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0xd0000, 0x0 }, { 0xd0000, 0x0 },
@ -791,7 +790,6 @@ struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0xd0000, 0x1 }, { 0xd0000, 0x1 },
}; };
/* P0 2D message block paremeter for training firmware */ /* P0 2D message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_2d_cfg[] = { struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 }, { 0xd0000, 0x0 },

1
board/freescale/ls1012ardb/ls1012ardb.c
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@ -147,7 +147,6 @@ int dram_init(void)
} }
#endif #endif
int board_early_init_f(void) int board_early_init_f(void)
{ {
fsl_lsch2_early_init_f(); fsl_lsch2_early_init_f();

1
board/freescale/ls1021aiot/ls1021aiot.c
View File

@ -33,7 +33,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define DDR_SIZE 0x40000000 #define DDR_SIZE 0x40000000
int checkboard(void) int checkboard(void)
{ {
puts("Board: LS1021AIOT\n"); puts("Board: LS1021AIOT\n");

1
board/freescale/ls1043aqds/ls1043aqds.c
View File

@ -508,7 +508,6 @@ int config_serdes_mux(void)
return 0; return 0;
} }
#ifdef CONFIG_MISC_INIT_R #ifdef CONFIG_MISC_INIT_R
int misc_init_r(void) int misc_init_r(void)
{ {

1
board/freescale/ls1088a/ddr.c
View File

@ -94,7 +94,6 @@ found:
popts->wrlvl_override = 1; popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf; popts->wrlvl_sample = 0xf;
/* Enable ZQ calibration */ /* Enable ZQ calibration */
popts->zq_en = 1; popts->zq_en = 1;

1
board/freescale/ls2080aqds/ddr.c
View File

@ -46,7 +46,6 @@ void fsl_ddr_board_options(memctl_options_t *popts,
else else
pbsp = udimms[ctrl_num]; pbsp = udimms[ctrl_num];
/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table. * freqency and n_banks specified in board_specific_parameters table.
*/ */

1
board/freescale/ls2080aqds/ddr.h
View File

@ -87,5 +87,4 @@ static const struct board_specific_parameters *rdimms[] = {
rdimm2, rdimm2,
}; };
#endif #endif

1
board/freescale/ls2080ardb/ddr.c
View File

@ -46,7 +46,6 @@ void fsl_ddr_board_options(memctl_options_t *popts,
else else
pbsp = udimms[ctrl_num]; pbsp = udimms[ctrl_num];
/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table. * freqency and n_banks specified in board_specific_parameters table.
*/ */

1
board/freescale/ls2080ardb/ddr.h
View File

@ -72,5 +72,4 @@ static const struct board_specific_parameters *rdimms[] = {
udimm2, /* DP-DDR doesn't support RDIMM */ udimm2, /* DP-DDR doesn't support RDIMM */
}; };
#endif #endif

2
board/freescale/m5249evb/m5249evb.c
View File

@ -32,7 +32,6 @@ int checkboard (void) {
return 0; return 0;
}; };
int dram_init(void) int dram_init(void)
{ {
unsigned long junk = 0xa5a59696; unsigned long junk = 0xa5a59696;
@ -91,7 +90,6 @@ int dram_init(void)
return 0; return 0;
}; };
int testdram(void) int testdram(void)
{ {
/* TODO: XXX XXX XXX */ /* TODO: XXX XXX XXX */

1
board/freescale/m5253demo/m5253demo.c
View File

@ -133,7 +133,6 @@ void ide_set_reset(int idereset)
} }
#endif /* CONFIG_IDE */ #endif /* CONFIG_IDE */
#ifdef CONFIG_DRIVER_DM9000 #ifdef CONFIG_DRIVER_DM9000
int board_eth_init(struct bd_info *bis) int board_eth_init(struct bd_info *bis)
{ {

1
board/freescale/m5275evb/m5275evb.c
View File

@ -74,7 +74,6 @@ int dram_init(void)
*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
out_be32(&sdp->sdmr, 0x018d0000); out_be32(&sdp->sdmr, 0x018d0000);
*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;

1
board/freescale/mpc8548cds/ddr.c
View File

@ -3,7 +3,6 @@
* Copyright 2008 Freescale Semiconductor, Inc. * Copyright 2008 Freescale Semiconductor, Inc.
*/ */
#include <fsl_ddr_sdram.h> #include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h> #include <fsl_ddr_dimm_params.h>

3
board/freescale/mx6sabreauto/mx6sabreauto.c
View File

@ -138,7 +138,6 @@ static void eim_clk_setup(void)
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
int cscmr1, ccgr6; int cscmr1, ccgr6;
/* Turn off EIM clock */ /* Turn off EIM clock */
ccgr6 = readl(&imx_ccm->CCGR6); ccgr6 = readl(&imx_ccm->CCGR6);
ccgr6 &= ~(0x3 << 10); ccgr6 &= ~(0x3 << 10);
@ -170,7 +169,6 @@ static void setup_iomux_eimnor(void)
} }
#endif #endif
static iomux_v3_cfg_t const usdhc3_pads[] = { static iomux_v3_cfg_t const usdhc3_pads[] = {
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
@ -480,7 +478,6 @@ int power_init_board(void)
if (ret != 0) if (ret != 0)
return ret; return ret;
if (is_mx6dqp()) { if (is_mx6dqp()) {
/* set SW2 staby volatage 0.975V*/ /* set SW2 staby volatage 0.975V*/
value = pmic_reg_read(dev, PFUZE100_SW2STBY); value = pmic_reg_read(dev, PFUZE100_SW2STBY);

1
board/freescale/mx6sllevk/mx6sllevk.c
View File

@ -54,7 +54,6 @@ int power_init_board(void)
rev_id = pmic_reg_read(dev, PFUZE100_REVID); rev_id = pmic_reg_read(dev, PFUZE100_REVID);
printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
/* Init mode to APS_PFM */ /* Init mode to APS_PFM */
pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM); pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);

1
board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
View File

@ -135,7 +135,6 @@ int power_init_board(void)
rev_id = pmic_reg_read(dev, PFUZE100_REVID); rev_id = pmic_reg_read(dev, PFUZE100_REVID);
printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
/* Init mode to APS_PFM */ /* Init mode to APS_PFM */
pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM); pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);

2
board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
View File

@ -108,7 +108,6 @@ static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
}; };
static void setup_iomux_uart(void) static void setup_iomux_uart(void)
{ {
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
@ -352,7 +351,6 @@ void board_preboot_os(void)
#include <spl.h> #include <spl.h>
#include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6-ddr.h>
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
.grp_addds = 0x00000030, .grp_addds = 0x00000030,
.grp_ddrmode_ctl = 0x00020000, .grp_ddrmode_ctl = 0x00020000,

1
board/freescale/p1010rdb/p1010rdb.c
View File

@ -622,7 +622,6 @@ void board_reset(void)
} }
#endif #endif
int misc_init_r(void) int misc_init_r(void)
{ {
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);

1
board/freescale/t102xrdb/cpld.h
View File

@ -23,7 +23,6 @@ struct cpld_data {
u8 boot_config2; /* 0x1A - Boot config override register*/ u8 boot_config2; /* 0x1A - Boot config override register*/
}; };
/* Pointer to the CPLD register set */ /* Pointer to the CPLD register set */
u8 cpld_read(unsigned int reg); u8 cpld_read(unsigned int reg);

1
board/freescale/t104xrdb/eth.c
View File

@ -84,7 +84,6 @@ int board_eth_init(struct bd_info *bis)
DEFAULT_FM_MDIO_NAME)); DEFAULT_FM_MDIO_NAME));
} }
cpu_eth_init(bis); cpu_eth_init(bis);
#endif #endif

1
board/freescale/t208xqds/t208xqds_qixis.h
View File

@ -11,7 +11,6 @@
#define QIXIS_SRDS1CLK_122 0x5a #define QIXIS_SRDS1CLK_122 0x5a
#define QIXIS_SRDS1CLK_125 0x5e #define QIXIS_SRDS1CLK_125 0x5e
/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ /* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
#define BRDCFG4_EMISEL_MASK 0xE0 #define BRDCFG4_EMISEL_MASK 0xE0
#define BRDCFG4_EMISEL_SHIFT 5 #define BRDCFG4_EMISEL_SHIFT 5

1
board/freescale/t208xqds/tlb.c
View File

@ -81,7 +81,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1), 0, 5, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCIe 4, 0xc0000000 */ /* *I*G* - PCIe 4, 0xc0000000 */
SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS, SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

1
board/freescale/t208xrdb/tlb.c
View File

@ -81,7 +81,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1), 0, 5, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCIe 4, 0xc0000000 */ /* *I*G* - PCIe 4, 0xc0000000 */
SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS, SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

1
board/freescale/t4rdb/ddr.c
View File

@ -39,7 +39,6 @@ void fsl_ddr_board_options(memctl_options_t *popts,
else else
pbsp = udimms[0]; pbsp = udimms[0];
/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table. * freqency and n_banks specified in board_specific_parameters table.
*/ */

1
board/freescale/t4rdb/ddr.h
View File

@ -73,5 +73,4 @@ static const struct board_specific_parameters *rdimms[] = {
rdimm0, rdimm0,
}; };
#endif #endif

1
board/freescale/vf610twr/vf610twr.c
View File

@ -214,7 +214,6 @@ static void setup_iomux_nfc(void)
} }
#endif #endif
static void setup_iomux_qspi(void) static void setup_iomux_qspi(void)
{ {
static const iomux_v3_cfg_t qspi0_pads[] = { static const iomux_v3_cfg_t qspi0_pads[] = {

1
board/gdsys/common/dp501.c
View File

@ -136,7 +136,6 @@ void dp501_powerdown(u8 addr)
dp501_setbits(addr, 0x0a, 0x30); /* power down encoder, standby mode */ dp501_setbits(addr, 0x0a, 0x30); /* power down encoder, standby mode */
} }
int dp501_probe(unsigned screen, bool power) int dp501_probe(unsigned screen, bool power)
{ {
#ifdef CONFIG_SYS_DP501_BASE #ifdef CONFIG_SYS_DP501_BASE

1
board/gdsys/common/ioep-fpga.c
View File

@ -6,7 +6,6 @@
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS #ifdef CONFIG_GDSYS_LEGACY_DRIVERS
#include <gdsys_fpga.h> #include <gdsys_fpga.h>
#include <linux/bitops.h> #include <linux/bitops.h>

2
board/gdsys/common/osd.c
View File

@ -165,7 +165,6 @@ static unsigned int ics8n3qv01_get_fout_calc(unsigned index)
return fout_calc; return fout_calc;
} }
static void ics8n3qv01_calc_parameters(unsigned int fout, static void ics8n3qv01_calc_parameters(unsigned int fout,
unsigned int *_mint, unsigned int *_mfrac, unsigned int *_mint, unsigned int *_mfrac,
unsigned int *_n) unsigned int *_n)
@ -424,7 +423,6 @@ int osd_write(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
y = hextoul(argv[2], NULL); y = hextoul(argv[2], NULL);
rp = argv[3]; rp = argv[3];
while (*rp) { while (*rp) {
char substr[5]; char substr[5];

1
board/ge/bx50v3/bx50v3.c
View File

@ -434,7 +434,6 @@ static const struct boot_mode board_boot_modes[] = {
}; };
#endif #endif
/* /*
* The SoM used by these boards has XTAL not connected despite datasheet * The SoM used by these boards has XTAL not connected despite datasheet
* suggesting connecting unused XTAL pins to ground. Without explicitly * suggesting connecting unused XTAL pins to ground. Without explicitly

3
board/hisilicon/hikey/hikey.c
View File

@ -244,7 +244,6 @@ static int config_sd_carddetect(void)
return 0; return 0;
} }
static void mmc1_init_pll(void) static void mmc1_init_pll(void)
{ {
uint32_t data; uint32_t data;
@ -339,7 +338,6 @@ static void mmc0_reset_clk(void)
} while (data & PERI_RST0_MMC0); } while (data & PERI_RST0_MMC0);
} }
/* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */ /* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */
static void hi6220_pmussi_init(void) static void hi6220_pmussi_init(void)
{ {
@ -398,7 +396,6 @@ static int init_dwmmc(void)
if (ret) if (ret)
printf("%s: Error adding eMMC port (%d)\n", __func__, ret); printf("%s: Error adding eMMC port (%d)\n", __func__, ret);
/* take mmc1 (sd slot) out of reset, configure clocks and pinmuxing */ /* take mmc1 (sd slot) out of reset, configure clocks and pinmuxing */
mmc1_init_pll(); mmc1_init_pll();
mmc1_reset_clk(); mmc1_reset_clk();

1
board/is1/qts/iocsr_config.h
View File

@ -655,5 +655,4 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x00004000, 0x00004000,
}; };
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ #endif /* __SOCFPGA_IOCSR_CONFIG_H__ */

1
board/is1/qts/pll_config.h
View File

@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 4 #define CFG_HPS_ALTERAGRP_MAINCLK 4
#define CFG_HPS_ALTERAGRP_DBGATCLK 4 #define CFG_HPS_ALTERAGRP_DBGATCLK 4
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ #endif /* __SOCFPGA_PLL_CONFIG_H__ */

1
board/kontron/pitx_imx8m/pitx_imx8m.c
View File

@ -84,7 +84,6 @@ int board_phys_sdram_size(phys_size_t *memsize)
return 0; return 0;
} }
#ifdef CONFIG_FEC_MXC #ifdef CONFIG_FEC_MXC
#define FEC_RST_PAD IMX_GPIO_NR(1, 11) #define FEC_RST_PAD IMX_GPIO_NR(1, 11)
static iomux_v3_cfg_t const fec1_rst_pads[] = { static iomux_v3_cfg_t const fec1_rst_pads[] = {

2
board/kontron/pitx_imx8m/spl.c
View File

@ -28,7 +28,6 @@ extern struct dram_timing_info dram_timing_4gb;
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
static void spl_dram_init(void) static void spl_dram_init(void)
{ {
struct dram_timing_info *dram_timing; struct dram_timing_info *dram_timing;
@ -89,7 +88,6 @@ int board_mmc_getcd(struct mmc *mmc)
return 0; return 0;
} }
#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
PAD_CTL_FSEL2) PAD_CTL_FSEL2)
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)

2
board/l+g/vinco/vinco.c
View File

@ -62,7 +62,6 @@ static void vinco_spi0_hw_init(void)
} }
#endif /* CONFIG_ATMEL_SPI */ #endif /* CONFIG_ATMEL_SPI */
#ifdef CONFIG_CMD_USB #ifdef CONFIG_CMD_USB
static void vinco_usb_hw_init(void) static void vinco_usb_hw_init(void)
{ {
@ -72,7 +71,6 @@ static void vinco_usb_hw_init(void)
} }
#endif #endif
#ifdef CONFIG_GENERIC_ATMEL_MCI #ifdef CONFIG_GENERIC_ATMEL_MCI
void vinco_mci0_hw_init(void) void vinco_mci0_hw_init(void)
{ {

1
board/logicpd/omap3som/omap3logic.h
View File

@ -19,7 +19,6 @@
#define NET_LAN92XX_GPMC_CONFIG5 0x00080a0a #define NET_LAN92XX_GPMC_CONFIG5 0x00080a0a
#define NET_LAN92XX_GPMC_CONFIG6 0x03000280 #define NET_LAN92XX_GPMC_CONFIG6 0x03000280
const omap3_sysinfo sysinfo = { const omap3_sysinfo sysinfo = {
DDR_DISCRETE, DDR_DISCRETE,
"Logic DM37x/OMAP35x reference board", "Logic DM37x/OMAP35x reference board",

2
board/mntre/imx8mq_reform2/imx8mq_reform2.c
View File

@ -28,14 +28,12 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
static iomux_v3_cfg_t const wdog_pads[] = { static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
}; };
int board_early_init_f(void) int board_early_init_f(void)
{ {
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;

2
board/mntre/imx8mq_reform2/lpddr4_timing.c
View File

@ -312,7 +312,6 @@ static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
{ 0xd0000, 1 }, { 0xd0000, 1 },
}; };
/* P1 message block parameter for training firmware */ /* P1 message block parameter for training firmware */
static struct dram_cfg_param lpddr4_fsp1_cfg[] = { static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
{ 0xd0000, 0 }, { 0xd0000, 0 },
@ -352,7 +351,6 @@ static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
{ 0xd0000, 1 }, { 0xd0000, 1 },
}; };
/* P0 2D message block parameter for training firmware */ /* P0 2D message block parameter for training firmware */
static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
{ 0xd0000, 0 }, { 0xd0000, 0 },

1
board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
View File

@ -254,7 +254,6 @@ unsigned long ps7_reset_apu_3_0[] = {
EMIT_EXIT(), EMIT_EXIT(),
}; };
int ps7_post_config(void) int ps7_post_config(void)
{ {
return ps7_config(ps7_post_config_3_0); return ps7_config(ps7_post_config_3_0);

1
board/qualcomm/dragonboard410c/dragonboard410c.c
View File

@ -115,7 +115,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
do_fixup_by_compat(blob, "qcom,wcnss-wlan", do_fixup_by_compat(blob, "qcom,wcnss-wlan",
"local-mac-address", mac, ARP_HLEN, 1); "local-mac-address", mac, ARP_HLEN, 1);
if (!eth_env_get_enetaddr("btaddr", mac)) { if (!eth_env_get_enetaddr("btaddr", mac)) {
msm_generate_mac_addr(mac); msm_generate_mac_addr(mac);

1
board/siemens/common/board_am335x.c
View File

@ -22,7 +22,6 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
void set_uart_mux_conf(void) void set_uart_mux_conf(void)
{ {

1
board/siemens/pxm2/pmic.h
View File

@ -50,7 +50,6 @@
#define PMIC_REG_ST_OFF_1 (0x2) #define PMIC_REG_ST_OFF_1 (0x2)
#define PMIC_REG_ST_ON_LOW_POW (0x3) #define PMIC_REG_ST_ON_LOW_POW (0x3)
/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */ /* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */
#define PMIC_OP_REG_SEL (0x7F) #define PMIC_OP_REG_SEL (0x7F)

1
board/socrates/ddr.c
View File

@ -3,7 +3,6 @@
* Copyright 2008 Freescale Semiconductor, Inc. * Copyright 2008 Freescale Semiconductor, Inc.
*/ */
#include <fsl_ddr_sdram.h> #include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h> #include <fsl_ddr_dimm_params.h>

1
board/socrates/nand.c
View File

@ -56,7 +56,6 @@ static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
} }
} }
/** /**
* sc_nand_read_byte - read one byte from the chip * sc_nand_read_byte - read one byte from the chip
* @mtd: MTD device structure * @mtd: MTD device structure

1
board/socrates/sdram.c
View File

@ -14,7 +14,6 @@
#include <spd_sdram.h> #include <spd_sdram.h>
#include <linux/delay.h> #include <linux/delay.h>
#if !defined(CONFIG_SPD_EEPROM) #if !defined(CONFIG_SPD_EEPROM)
/* /*
* Autodetect onboard DDR SDRAM on 85xx platforms * Autodetect onboard DDR SDRAM on 85xx platforms

1
board/socrates/tlb.c
View File

@ -28,7 +28,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0, MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0), 0, 0, BOOKE_PAGESZ_4K, 0),
/* /*
* TLB 1: 64M Non-cacheable, guarded * TLB 1: 64M Non-cacheable, guarded
* 0xfc000000 64M FLASH * 0xfc000000 64M FLASH

1
board/softing/vining_fpga/qts/iocsr_config.h
View File

@ -655,5 +655,4 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x00004000, 0x00004000,
}; };
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ #endif /* __SOCFPGA_IOCSR_CONFIG_H__ */

1
board/softing/vining_fpga/qts/pll_config.h
View File

@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 3 #define CFG_HPS_ALTERAGRP_MAINCLK 3
#define CFG_HPS_ALTERAGRP_DBGATCLK 3 #define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ #endif /* __SOCFPGA_PLL_CONFIG_H__ */

1
board/sr1500/qts/iocsr_config.h
View File

@ -655,5 +655,4 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x00004000, 0x00004000,
}; };
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ #endif /* __SOCFPGA_IOCSR_CONFIG_H__ */

1
board/sr1500/qts/pll_config.h
View File

@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 3 #define CFG_HPS_ALTERAGRP_MAINCLK 3
#define CFG_HPS_ALTERAGRP_DBGATCLK 3 #define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ #endif /* __SOCFPGA_PLL_CONFIG_H__ */

1
board/synopsys/emsdp/emsdp.c
View File

@ -76,7 +76,6 @@ int board_early_init_r(void)
// Switch PSRAM controller back to memory mode // Switch PSRAM controller back to memory mode
writel(0, PSRAM_FLASH_CONFIG_REG_0); writel(0, PSRAM_FLASH_CONFIG_REG_0);
// Switch PSRAM controller to command mode // Switch PSRAM controller to command mode
writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_1); writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_1);
// Program Refresh Configuration Register (RCR) for BANK1 // Program Refresh Configuration Register (RCR) for BANK1

1
board/tcl/sl50/board.c
View File

@ -348,7 +348,6 @@ int board_eth_init(struct bd_info *bis)
eth_env_set_enetaddr("eth1addr", mac_addr); eth_env_set_enetaddr("eth1addr", mac_addr);
} }
writel(MII_MODE_ENABLE, &cdev->miisel); writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_MII; PHY_INTERFACE_MODE_MII;

1
board/tcl/sl50/mux.c
View File

@ -107,7 +107,6 @@ static struct module_pin_mux mii1_pin_mux[] = {
{-1}, {-1},
}; };
void enable_uart0_pin_mux(void) void enable_uart0_pin_mux(void)
{ {
configure_module_pin_mux(uart0_pin_mux); configure_module_pin_mux(uart0_pin_mux);

1
board/terasic/de1-soc/qts/iocsr_config.h
View File

@ -655,5 +655,4 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x00004000, 0x00004000,
}; };
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ #endif /* __SOCFPGA_IOCSR_CONFIG_H__ */

1
board/terasic/de1-soc/qts/pll_config.h
View File

@ -86,5 +86,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 3 #define CFG_HPS_ALTERAGRP_MAINCLK 3
#define CFG_HPS_ALTERAGRP_DBGATCLK 3 #define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ #endif /* __SOCFPGA_PLL_CONFIG_H__ */

1
board/terasic/de10-nano/qts/iocsr_config.h
View File

@ -655,5 +655,4 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x00004000, 0x00004000,
}; };
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ #endif /* __SOCFPGA_IOCSR_CONFIG_H__ */

1
board/terasic/de10-nano/qts/pll_config.h
View File

@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 3 #define CFG_HPS_ALTERAGRP_MAINCLK 3
#define CFG_HPS_ALTERAGRP_DBGATCLK 3 #define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ #endif /* __SOCFPGA_PLL_CONFIG_H__ */

1
board/terasic/de10-standard/qts/iocsr_config.h
View File

@ -655,5 +655,4 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x00004000, 0x00004000,
}; };
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ #endif /* __SOCFPGA_IOCSR_CONFIG_H__ */

1
board/terasic/de10-standard/qts/pll_config.h
View File

@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 4 #define CFG_HPS_ALTERAGRP_MAINCLK 4
#define CFG_HPS_ALTERAGRP_DBGATCLK 4 #define CFG_HPS_ALTERAGRP_DBGATCLK 4
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ #endif /* __SOCFPGA_PLL_CONFIG_H__ */

1
board/terasic/sockit/qts/iocsr_config.h
View File

@ -655,5 +655,4 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x00004000, 0x00004000,
}; };
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ #endif /* __SOCFPGA_IOCSR_CONFIG_H__ */

1
board/terasic/sockit/qts/pll_config.h
View File

@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 3 #define CFG_HPS_ALTERAGRP_MAINCLK 3
#define CFG_HPS_ALTERAGRP_DBGATCLK 3 #define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ #endif /* __SOCFPGA_PLL_CONFIG_H__ */

1
board/theadorable/theadorable.c
View File

@ -288,7 +288,6 @@ int board_late_init(void)
} }
} while (get_timer(start_time) < ABORT_TIMEOUT); } while (get_timer(start_time) < ABORT_TIMEOUT);
/* /*
* At this stage the bootcounter has not been incremented * At this stage the bootcounter has not been incremented
* yet. We need to do this manually here to get an actually * yet. We need to do this manually here to get an actually

1
board/ti/am335x/board.c
View File

@ -339,7 +339,6 @@ static void scale_vcores_bone(int freq)
if (power_tps65217_init(0)) if (power_tps65217_init(0))
return; return;
/* /*
* On Beaglebone White we need to ensure we have AC power * On Beaglebone White we need to ensure we have AC power
* before increasing the frequency. * before increasing the frequency.

1
board/ti/am43xx/board.c
View File

@ -336,7 +336,6 @@ const struct dpll_params *get_dpll_ddr_params(void)
return NULL; return NULL;
} }
/* /*
* get_opp_offset: * get_opp_offset:
* Returns the index for safest OPP of the device to boot. * Returns the index for safest OPP of the device to boot.

1
board/ti/am57xx/board.c
View File

@ -515,7 +515,6 @@ int get_voltrail_opp(int rail_offset)
return opp; return opp;
} }
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
/* No env to setup for SPL */ /* No env to setup for SPL */
static inline void setup_board_eeprom_env(void) { } static inline void setup_board_eeprom_env(void) { }

1
board/ti/ks2_evm/ddr3_cfg.c
View File

@ -6,7 +6,6 @@
* Texas Instruments Incorporated, <www.ti.com> * Texas Instruments Incorporated, <www.ti.com>
*/ */
#include <asm/arch/ddr3.h> #include <asm/arch/ddr3.h>
#include "ddr3_cfg.h" #include "ddr3_cfg.h"

1
board/ti/panda/panda_mux_data.h
View File

@ -11,7 +11,6 @@
#include <asm/arch/mux_omap4.h> #include <asm/arch/mux_omap4.h>
const struct pad_conf_entry core_padconf_array_essential[] = { const struct pad_conf_entry core_padconf_array_essential[] = {
{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */

2
board/toradex/apalis_imx6/apalis_imx6.c
View File

@ -783,7 +783,6 @@ static void ccgr_init(void)
writel(0x010E0101, &ccm->ccosr); writel(0x010E0101, &ccm->ccosr);
} }
#define PAD_CTL_INPUT_DDR BIT(17) #define PAD_CTL_INPUT_DDR BIT(17)
struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
@ -951,7 +950,6 @@ static const struct mx6_ddr3_cfg ddr3_cfg_it = {
.SRT = 1, .SRT = 1,
}; };
/* Perform DDR DRAM calibration */ /* Perform DDR DRAM calibration */
static void spl_dram_perform_cal(const struct mx6_ddr_sysinfo *ddr_sysinfo) static void spl_dram_perform_cal(const struct mx6_ddr_sysinfo *ddr_sysinfo)
{ {

2
board/toradex/colibri_imx6/colibri_imx6.c
View File

@ -759,7 +759,6 @@ MX6_MMDC_P0_MDMISC, 0x000b17c0,
*/ */
MX6_MMDC_P0_MDSCR, 0x00008000, MX6_MMDC_P0_MDSCR, 0x00008000,
/* 800mhz_2x64mx16.cfg */ /* 800mhz_2x64mx16.cfg */
MX6_MMDC_P0_MDPDC, 0x0002002D, MX6_MMDC_P0_MDPDC, 0x0002002D,
@ -891,7 +890,6 @@ MX6_MMDC_P0_MDMISC, 0x000b17c0,
*/ */
MX6_MMDC_P0_MDSCR, 0x00008000, MX6_MMDC_P0_MDSCR, 0x00008000,
/* 800mhz_2x64mx16.cfg */ /* 800mhz_2x64mx16.cfg */
MX6_MMDC_P0_MDPDC, 0x0002002D, MX6_MMDC_P0_MDPDC, 0x0002002D,

1
board/toradex/colibri_imx7/colibri_imx7.c
View File

@ -223,7 +223,6 @@ int power_init_board(void)
int reg, ver; int reg, ver;
int ret; int ret;
ret = pmic_get("pmic@33", &dev); ret = pmic_get("pmic@33", &dev);
if (ret) if (ret)
return ret; return ret;

1
board/vscom/baltos/board.c
View File

@ -285,7 +285,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
mac_addr[4] = header.MAC1[4]; mac_addr[4] = header.MAC1[4];
mac_addr[5] = header.MAC1[5]; mac_addr[5] = header.MAC1[5];
node = fdt_path_offset(blob, "ethernet0"); node = fdt_path_offset(blob, "ethernet0");
if (node < 0) { if (node < 0) {
printf("no ethernet0 path offset\n"); printf("no ethernet0 path offset\n");

2
board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
View File

@ -4060,7 +4060,6 @@ unsigned long ps7_post_config_3_0[] = {
// //
}; };
unsigned long ps7_pll_init_data_2_0[] = { unsigned long ps7_pll_init_data_2_0[] = {
// START: top // START: top
// .. START: SLCR SETTINGS // .. START: SLCR SETTINGS
@ -8263,7 +8262,6 @@ unsigned long ps7_post_config_2_0[] = {
// //
}; };
unsigned long ps7_pll_init_data_1_0[] = { unsigned long ps7_pll_init_data_1_0[] = {
// START: top // START: top
// .. START: SLCR SETTINGS // .. START: SLCR SETTINGS

2
board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
View File

@ -4167,7 +4167,6 @@ unsigned long ps7_post_config_3_0[] = {
// //
}; };
unsigned long ps7_pll_init_data_2_0[] = { unsigned long ps7_pll_init_data_2_0[] = {
// START: top // START: top
// .. START: SLCR SETTINGS // .. START: SLCR SETTINGS
@ -8483,7 +8482,6 @@ unsigned long ps7_post_config_2_0[] = {
// //
}; };
unsigned long ps7_pll_init_data_1_0[] = { unsigned long ps7_pll_init_data_1_0[] = {
// START: top // START: top
// .. START: SLCR SETTINGS // .. START: SLCR SETTINGS

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