From 999c169c354399639d4e10d36c0ab464beeaced5 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 10 Mar 2026 10:32:22 -0500 Subject: [PATCH] clk: mediatek: mt8183: convert CLK_XTAL to CLK_PAD_CLK26M Replace all uses of CLK_XTAL with CLK_PAD_CLK26M. This avoids declaring the same parent clock two different ways and will eventually let us remove CLK_PARENT_XTAL completely. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-9-66175ca8f637@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8183.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 6158441fb95..7b2d796bc6c 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -76,7 +76,7 @@ static const struct mtk_pll_data apmixed_plls[] = { }; #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) #define FIXED_CLK1(_id, _rate) \ FIXED_CLK(_id, CLK_TOP_UNIVPLL, CLK_PARENT_TOPCKGEN, _rate) @@ -605,7 +605,6 @@ static const struct mtk_composite top_muxes[] = { }; static const struct mtk_clk_tree mt8183_clk_tree = { - .xtal_rate = 26 * MHZ, .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates),