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arm: dts: rockchip: sync rk3066/rk3188 DT files from linux-next v6.2-rc4

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Sync rk3066/rk3188 DT files from Linux.
This is the state as of linux-next v6.2-rc4.
New nfc node for MK808 rk3066a.
CRU nodes now have a clock property.
To prefend dtoc errors a fixed clock must also be
included for tpl/spl in the rk3xxx-u-boot.dtsi file.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Johan Jonker 2023-03-19 16:05:57 +01:00 committed by Kever Yang
parent e16be4dd8b
commit 98125086d6
6 changed files with 69 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
arch/arm/dts/rk3066a-mk808.dts
View File

@ -32,7 +32,7 @@
keyup-threshold-microvolt = <2500000>;
poll-interval = <100>;
recovery {
button-recovery {
label = "recovery";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <0>;
@ -157,7 +157,32 @@
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;
pinctrl-names = "default";
vmmc-supply = <&vcc_wifi>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
};
};
&nfc {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
nand@0 {
reg = <0>;
label = "rk-nand";
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-step-size = <1024>;
nand-ecc-strength = <40>;
nand-is-boot-medium;
rockchip,boot-blks = <8>;
rockchip,boot-ecc-strength = <24>;
};
};
&pinctrl {

3
arch/arm/dts/rk3066a.dtsi
View File

@ -202,8 +202,9 @@
cru: clock-controller@20000000 {
compatible = "rockchip,rk3066a-cru";
reg = <0x20000000 0x1000>;
clocks = <&xin24m>;
clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,

18
arch/arm/dts/rk3188-radxarock.dts
View File

@ -6,7 +6,6 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "rk3188.dtsi"
#include "rk3188-radxarock-u-boot.dtsi"
/ {
model = "Radxa Rock";
@ -25,7 +24,7 @@
compatible = "gpio-keys";
autorepeat;
power {
key-power {
gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
@ -72,7 +71,7 @@
#sound-dai-cells = <0>;
};
ir_recv: gpio-ir-receiver {
ir_recv: ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
@ -127,13 +126,15 @@
};
&emac {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
phy = <&phy0>;
phy-supply = <&vcc_rmii>;
pinctrl-names = "default";
pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
@ -141,6 +142,7 @@
interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;

27
arch/arm/dts/rk3188.dtsi
View File

@ -54,7 +54,7 @@
};
};
cpu0_opp_table: opp_table0 {
cpu0_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@ -195,8 +195,9 @@
cru: clock-controller@20000000 {
compatible = "rockchip,rk3188-cru";
reg = <0x20000000 0x1000>;
clocks = <&xin24m>;
clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};
@ -223,7 +224,7 @@
#size-cells = <1>;
ranges;
gpio0: gpio0@2000a000 {
gpio0: gpio@2000a000 {
compatible = "rockchip,rk3188-gpio-bank0";
reg = <0x2000a000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
@ -236,7 +237,7 @@
#interrupt-cells = <2>;
};
gpio1: gpio1@2003c000 {
gpio1: gpio@2003c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003c000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
@ -249,7 +250,7 @@
#interrupt-cells = <2>;
};
gpio2: gpio2@2003e000 {
gpio2: gpio@2003e000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003e000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
@ -262,7 +263,7 @@
#interrupt-cells = <2>;
};
gpio3: gpio3@20080000 {
gpio3: gpio@20080000 {
compatible = "rockchip,gpio-bank";
reg = <0x20080000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
@ -275,15 +276,15 @@
#interrupt-cells = <2>;
};
pcfg_pull_up: pcfg_pull_up {
pcfg_pull_up: pcfg-pull-up {
bias-pull-up;
};
pcfg_pull_down: pcfg_pull_down {
pcfg_pull_down: pcfg-pull-down {
bias-pull-down;
};
pcfg_pull_none: pcfg_pull_none {
pcfg_pull_none: pcfg-pull-none {
bias-disable;
};
@ -378,7 +379,7 @@
rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
};
lcdc1_rgb24: ldcd1-rgb24 {
lcdc1_rgb24: lcdc1-rgb24 {
rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
<2 RK_PA1 1 &pcfg_pull_none>,
<2 RK_PA2 1 &pcfg_pull_none>,
@ -606,7 +607,6 @@
&global_timer {
interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
status = "disabled";
};
&local_timer {
@ -641,6 +641,11 @@
&grf {
compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd";
io_domains: io-domains {
compatible = "rockchip,rk3188-io-voltage-domain";
status = "disabled";
};
usbphy: usbphy {
compatible = "rockchip,rk3188-usb-phy";
#address-cells = <1>;

4
arch/arm/dts/rk3xxx-u-boot.dtsi
View File

@ -33,3 +33,7 @@
&uart2 {
clock-frequency = <24000000>;
};
&xin24m {
bootph-all;
};

9
arch/arm/dts/rk3xxx.dtsi
View File

@ -76,6 +76,13 @@
reg = <0x1013c200 0x20>;
interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
clocks = <&cru CORE_PERI>;
status = "disabled";
/* The clock source and the sched_clock provided by the arm_global_timer
* on Rockchip rk3066a/rk3188 are quite unstable because their rates
* depend on the CPU frequency.
* Keep the arm_global_timer disabled in order to have the
* DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default.
*/
};
local_timer: local-timer@1013c600 {
@ -186,8 +193,6 @@
compatible = "snps,arc-emac";
reg = <0x10204000 0x3c>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
rockchip,grf = <&grf>;