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clk: qcom: Use setbits_le32() for qcom_gate_clk_en()
The other clock enable functions in clock-qcom.c use setbits_le32() to read/modify/write the enable registers. Use the same for qcom_gate_clk_en() to simplify the code a bit. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-3-fcc371c9e45f@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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@ -76,16 +76,13 @@ void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk)
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int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
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int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
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{
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{
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u32 val;
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if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) {
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if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) {
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log_err("gcc@%#08llx: unknown clock ID %lu!\n",
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log_err("gcc@%#08llx: unknown clock ID %lu!\n",
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priv->base, id);
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priv->base, id);
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return -ENOENT;
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return -ENOENT;
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}
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}
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val = readl(priv->base + priv->data->clks[id].reg);
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setbits_le32(priv->base + priv->data->clks[id].reg, priv->data->clks[id].en_val);
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writel(val | priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg);
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return 0;
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return 0;
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}
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}
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