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x86: Use defines for the cache flags

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Use some named flags when setting up the cache, so it is easier to see
what is going on.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2025-03-15 14:25:32 +00:00 committed by Tom Rini
parent 66f0dcb07f
commit 912e32d34f
1 changed files with 12 additions and 3 deletions
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15
arch/x86/cpu/i386/cpu.c
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@ -592,6 +592,13 @@ int cpu_has_64bit(void)
#define PAGETABLE_BASE 0x80000
#define PAGETABLE_SIZE (6 * 4096)
#define _PRES BIT(0) /* present */
#define _RW BIT(1) /* write allowed */
#define _US BIT(2) /* user-access allowed */
#define _A BIT(5) /* has been accessed */
#define _D BIT(6) /* has been written to */
#define _PS BIT(7) /* indicates 2MB page size here */
/**
* build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
*
@ -604,15 +611,17 @@ static void build_pagetable(uint32_t *pgtable)
memset(pgtable, '\0', PAGETABLE_SIZE);
/* Level 4 needs a single entry */
pgtable[0] = (ulong)&pgtable[1024] + 7;
pgtable[0] = (ulong)&pgtable[1024] + _PRES + _RW + _US + _A;
/* Level 3 has one 64-bit entry for each GiB of memory */
for (i = 0; i < 4; i++)
pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7;
pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i +
_PRES + _RW + _US + _A;
/* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
for (i = 0; i < 2048; i++)
pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
pgtable[2048 + i * 2] = _PRES + _RW + _US + _PS + _A + _D +
(i << 21UL);
}
int cpu_jump_to_64bit(ulong setup_base, ulong target)