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clk: starfive: jh7110: Add watchdog clocks

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Add JH7110_SYSCLK_WDT_APB and JH7110_SYSCLK_WDT_CORE clocks for JH7110
watchdog device.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Chanho Park 2023-11-06 08:13:15 +09:00 committed by Leo Yu-Chi Liang
parent 2f0282922b
commit 8ef2d7926f
1 changed files with 9 additions and 0 deletions
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9
drivers/clk/starfive/clk-jh7110.c
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@ -434,6 +434,15 @@ static int jh7110_syscrg_init(struct udevice *dev)
starfive_clk_gate(priv->reg, starfive_clk_gate(priv->reg,
"i2c5_apb", "apb0", "i2c5_apb", "apb0",
OFFSET(JH7110_SYSCLK_I2C5_APB))); OFFSET(JH7110_SYSCLK_I2C5_APB)));
/* Watchdog clocks */
clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_APB),
starfive_clk_gate(priv->reg,
"wdt_apb", "apb0",
OFFSET(JH7110_SYSCLK_WDT_APB)));
clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_CORE),
starfive_clk_gate(priv->reg,
"wdt_core", "oscillator",
OFFSET(JH7110_SYSCLK_WDT_CORE)));
/* enable noc_bus_stg_axi clock */ /* enable noc_bus_stg_axi clock */
if (!clk_get_by_id(JH7110_SYSCLK_NOC_BUS_STG_AXI, &pclk)) if (!clk_get_by_id(JH7110_SYSCLK_NOC_BUS_STG_AXI, &pclk))