mirrors/u-boot
1
0
Fork 0
mirror of https://source.denx.de/u-boot/u-boot.git synced 2025-11-04 10:21:25 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity

mpc83xx: mpc8377erdb - change DDR settings to those from latest bsp

Browse Source 
when using Linus' 83xx_defconfig, the mpc8377rdb would hang at boot
at either:

NET: Registered protocol family 16

or the

io scheduler cfq registered

message.  Fixing up these DDR settings appears to fix the problem.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Kim Phillips 2009-08-21 16:33:15 -05:00
parent 27c5248dd4
commit 8eceeb7fd6
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
include/configs/MPC837XERDB.h
View File

@ -190,8 +190,8 @@
/* 0x3937d322 */ /* 0x3937d322 */
#define CONFIG_SYS_DDR_TIMING_2 0x02984cc8 #define CONFIG_SYS_DDR_TIMING_2 0x02984cc8
#define CONFIG_SYS_DDR_INTERVAL ((1545 << SDRAM_INTERVAL_REFINT_SHIFT) \ #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
| (256 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
/* 0x06090100 */ /* 0x06090100 */
#if defined(CONFIG_DDR_2T_TIMING) #if defined(CONFIG_DDR_2T_TIMING)
@ -205,7 +205,7 @@
/* 0x43000000 */ /* 0x43000000 */
#endif #endif
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
| (0x0442 << SDRAM_MODE_SD_SHIFT)) | (0x0442 << SDRAM_MODE_SD_SHIFT))
/* 0x04400442 */ /* DDR400 */ /* 0x04400442 */ /* DDR400 */
#define CONFIG_SYS_DDR_MODE2 0x00000000 #define CONFIG_SYS_DDR_MODE2 0x00000000