mirrors/u-boot
1
0
Fork 0
mirror of https://source.denx.de/u-boot/u-boot.git synced 2025-08-17 20:57:01 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity

arm64: zynqmp: Sync licenses with Linux kernel

Browse Source 
There is difference between licenses in the Linux kernel and there
shouldn't be any diff because all changes are coming from the same source
at the same time. The difference is really in a time when they were
upstreamed. That's why sync it up.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/813b29378083153b67c60772f28cd2613519f338.1695378830.git.michal.simek@amd.com
This commit is contained in:
Michal Simek 2023-09-22 12:35:41 +02:00
parent c5eb6c2d4a
commit 8daa786211
14 changed files with 26 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/dts/avnet-ultra96-rev1.dts
View File

@ -2,7 +2,7 @@
/*
* dts file for Avnet Ultra96 rev1
*
* (C) Copyright 2018 - 2020, Xilinx, Inc.
* (C) Copyright 2018, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/

3
arch/arm/dts/zynqmp-clk-ccf.dtsi
View File

@ -2,7 +2,8 @@
/*
* Clock specification for Xilinx ZynqMP
*
* (C) Copyright 2017 - 2021, Xilinx, Inc.
* (C) Copyright 2017 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/

3
arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
View File

@ -2,7 +2,8 @@
/*
* dts file for KV260 revA Carrier Card
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
* (C) Copyright 2020 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* SD level shifter:
* "A" - A01 board un-modified (NXP)

3
arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
View File

@ -2,7 +2,8 @@
/*
* dts file for KV260 revA Carrier Card
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
* (C) Copyright 2020 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/

2
arch/arm/dts/zynqmp-zc1254-revA.dts
View File

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZC1254
*
* (C) Copyright 2015 - 2020, Xilinx, Inc.
* (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>

3
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
View File

@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm015-dc1
*
* (C) Copyright 2015 - 2021, Xilinx, Inc.
* (C) Copyright 2015 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/

3
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
View File

@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm016-dc2
*
* (C) Copyright 2015 - 2021, Xilinx, Inc.
* (C) Copyright 2015 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/

2
arch/arm/dts/zynqmp-zcu102-rev1.0.dts
View File

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU102 Rev1.0
*
* (C) Copyright 2016 - 2020, Xilinx, Inc.
* (C) Copyright 2016 - 2018, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/

3
arch/arm/dts/zynqmp-zcu102-revA.dts
View File

@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP ZCU102 RevA
*
* (C) Copyright 2015 - 2021, Xilinx, Inc.
* (C) Copyright 2015 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/

3
arch/arm/dts/zynqmp-zcu102-revB.dts
View File

@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP ZCU102 RevB
*
* (C) Copyright 2016 - 2020, Xilinx, Inc.
* (C) Copyright 2016 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/

3
arch/arm/dts/zynqmp-zcu104-revA.dts
View File

@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP ZCU104
*
* (C) Copyright 2017 - 2021, Xilinx, Inc.
* (C) Copyright 2017 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/

5
arch/arm/dts/zynqmp-zcu104-revC.dts
View File

@ -1,8 +1,9 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx ZynqMP ZCU104
*
* (C) Copyright 2017 - 2021, Xilinx, Inc.
* (C) Copyright 2017 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/

3
arch/arm/dts/zynqmp-zcu106-revA.dts
View File

@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP ZCU106
*
* (C) Copyright 2016 - 2021, Xilinx, Inc.
* (C) Copyright 2016 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/

3
arch/arm/dts/zynqmp-zcu111-revA.dts
View File

@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP ZCU111
*
* (C) Copyright 2017 - 2021, Xilinx, Inc.
* (C) Copyright 2017 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/