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ARM: uniphier: refactor MEMCONF init code

Browse Source 
Currently, memconf-sld3.c and memconf-pxs2.c duplicate the code.

There are 3 patterns in terms of MEMCONF init:
  - DRAM 2 channels: LD4, sLD8, Pro4, Pro5, LD11
  - DRAM 3 channels: sLD3
  - DRAM 3 channels (Ch2 is disable by MEMCONF[21]): Pxs2, LD20

All of them can be moved into a single file by a little more
refactoring.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada 2017-01-15 14:59:04 +09:00
parent 78c627cf1f
commit 8d6c99c66f
15 changed files with 176 additions and 259 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/mach-uniphier/Makefile
View File

@ -4,7 +4,8 @@
ifdef CONFIG_SPL_BUILD
obj-y += init/ bcu/ memconf/
obj-y += memconf.o
obj-y += init/ bcu/
obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
else

6
arch/arm/mach-uniphier/init.h
View File

@ -77,9 +77,9 @@ static inline int uniphier_pxs2_sbc_init(const struct uniphier_board_data *bd)
int uniphier_sld3_bcu_init(const struct uniphier_board_data *bd);
int uniphier_ld4_bcu_init(const struct uniphier_board_data *bd);
int memconf_init(const struct uniphier_board_data *bd);
int uniphier_sld3_memconf_init(const struct uniphier_board_data *bd);
int uniphier_pxs2_memconf_init(const struct uniphier_board_data *bd);
int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd);
int uniphier_memconf_3ch_no_disbit_init(const struct uniphier_board_data *bd);
int uniphier_memconf_3ch_init(const struct uniphier_board_data *bd);
int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd);
int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd);

2
arch/arm/mach-uniphier/init/init-ld11.c
View File

@ -25,7 +25,7 @@ int uniphier_ld11_init(const struct uniphier_board_data *bd)
led_puts("L0");
memconf_init(bd);
uniphier_memconf_2ch_init(bd);
led_puts("L1");

3
arch/arm/mach-uniphier/init/init-ld20.c
View File

@ -25,8 +25,7 @@ int uniphier_ld20_init(const struct uniphier_board_data *bd)
led_puts("L0");
memconf_init(bd);
uniphier_pxs2_memconf_init(bd);
uniphier_memconf_3ch_init(bd);
led_puts("L1");

2
arch/arm/mach-uniphier/init/init-ld4.c
View File

@ -27,7 +27,7 @@ int uniphier_ld4_init(const struct uniphier_board_data *bd)
led_puts("L0");
memconf_init(bd);
uniphier_memconf_2ch_init(bd);
led_puts("L1");

2
arch/arm/mach-uniphier/init/init-pro4.c
View File

@ -24,7 +24,7 @@ int uniphier_pro4_init(const struct uniphier_board_data *bd)
led_puts("L0");
memconf_init(bd);
uniphier_memconf_2ch_init(bd);
led_puts("L1");

2
arch/arm/mach-uniphier/init/init-pro5.c
View File

@ -20,7 +20,7 @@ int uniphier_pro5_init(const struct uniphier_board_data *bd)
led_puts("L0");
memconf_init(bd);
uniphier_memconf_2ch_init(bd);
led_puts("L1");

3
arch/arm/mach-uniphier/init/init-pxs2.c
View File

@ -23,8 +23,7 @@ int uniphier_pxs2_init(const struct uniphier_board_data *bd)
led_puts("L0");
memconf_init(bd);
uniphier_pxs2_memconf_init(bd);
uniphier_memconf_3ch_init(bd);
led_puts("L1");

3
arch/arm/mach-uniphier/init/init-sld3.c
View File

@ -26,8 +26,7 @@ int uniphier_sld3_init(const struct uniphier_board_data *bd)
led_puts("L0");
memconf_init(bd);
uniphier_sld3_memconf_init(bd);
uniphier_memconf_3ch_no_disbit_init(bd);
led_puts("L1");

2
arch/arm/mach-uniphier/init/init-sld8.c
View File

@ -27,7 +27,7 @@ int uniphier_sld8_init(const struct uniphier_board_data *bd)
led_puts("L0");
memconf_init(bd);
uniphier_memconf_2ch_init(bd);
led_puts("L1");

163
arch/arm/mach-uniphier/memconf.c Normal file
View File

@ -0,0 +1,163 @@
/*
* Copyright (C) 2011-2015 Panasonic Corporation
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include "sg-regs.h"
#include "init.h"
static int __uniphier_memconf_init(const struct uniphier_board_data *bd,
int have_ch2, int have_ch2_disable_bit)
{
u32 val = 0;
unsigned long size_per_word;
/* set up ch0 */
switch (bd->dram_ch[0].width) {
case 16:
val |= SG_MEMCONF_CH0_NUM_1;
size_per_word = bd->dram_ch[0].size;
break;
case 32:
val |= SG_MEMCONF_CH0_NUM_2;
size_per_word = bd->dram_ch[0].size >> 1;
break;
default:
pr_err("error: unsupported DRAM ch0 width\n");
return -EINVAL;
}
switch (size_per_word) {
case SZ_64M:
val |= SG_MEMCONF_CH0_SZ_64M;
break;
case SZ_128M:
val |= SG_MEMCONF_CH0_SZ_128M;
break;
case SZ_256M:
val |= SG_MEMCONF_CH0_SZ_256M;
break;
case SZ_512M:
val |= SG_MEMCONF_CH0_SZ_512M;
break;
case SZ_1G:
val |= SG_MEMCONF_CH0_SZ_1G;
break;
default:
pr_err("error: unsupported DRAM ch0 size\n");
return -EINVAL;
}
/* set up ch1 */
switch (bd->dram_ch[1].width) {
case 16:
val |= SG_MEMCONF_CH1_NUM_1;
size_per_word = bd->dram_ch[1].size;
break;
case 32:
val |= SG_MEMCONF_CH1_NUM_2;
size_per_word = bd->dram_ch[1].size >> 1;
break;
default:
pr_err("error: unsupported DRAM ch1 width\n");
return -EINVAL;
}
switch (size_per_word) {
case SZ_64M:
val |= SG_MEMCONF_CH1_SZ_64M;
break;
case SZ_128M:
val |= SG_MEMCONF_CH1_SZ_128M;
break;
case SZ_256M:
val |= SG_MEMCONF_CH1_SZ_256M;
break;
case SZ_512M:
val |= SG_MEMCONF_CH1_SZ_512M;
break;
case SZ_1G:
val |= SG_MEMCONF_CH1_SZ_1G;
break;
default:
pr_err("error: unsupported DRAM ch1 size\n");
return -EINVAL;
}
/* is sparse mem? */
if (bd->dram_ch[0].base + bd->dram_ch[0].size < bd->dram_ch[1].base)
val |= SG_MEMCONF_SPARSEMEM;
if (!have_ch2)
goto out;
if (!bd->dram_ch[2].size) {
if (have_ch2_disable_bit)
val |= SG_MEMCONF_CH2_DISABLE;
goto out;
}
/* set up ch2 */
switch (bd->dram_ch[2].width) {
case 16:
val |= SG_MEMCONF_CH2_NUM_1;
size_per_word = bd->dram_ch[2].size;
break;
case 32:
val |= SG_MEMCONF_CH2_NUM_2;
size_per_word = bd->dram_ch[2].size >> 1;
break;
default:
pr_err("error: unsupported DRAM ch2 width\n");
return -EINVAL;
}
switch (size_per_word) {
case SZ_64M:
val |= SG_MEMCONF_CH2_SZ_64M;
break;
case SZ_128M:
val |= SG_MEMCONF_CH2_SZ_128M;
break;
case SZ_256M:
val |= SG_MEMCONF_CH2_SZ_256M;
break;
case SZ_512M:
val |= SG_MEMCONF_CH2_SZ_512M;
break;
case SZ_1G:
val |= SG_MEMCONF_CH2_SZ_1G;
break;
default:
pr_err("error: unsupported DRAM ch2 size\n");
return -EINVAL;
}
out:
writel(val, SG_MEMCONF);
return 0;
}
int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd)
{
return __uniphier_memconf_init(bd, 0, 0);
}
int uniphier_memconf_3ch_no_disbit_init(const struct uniphier_board_data *bd)
{
return __uniphier_memconf_init(bd, 1, 0);
}
int uniphier_memconf_3ch_init(const struct uniphier_board_data *bd)
{
return __uniphier_memconf_init(bd, 1, 1);
}

9
arch/arm/mach-uniphier/memconf/Makefile
View File

@ -1,9 +0,0 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += memconf.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += memconf-sld3.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += memconf-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += memconf-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += memconf-pxs2.o

68
arch/arm/mach-uniphier/memconf/memconf-pxs2.c
View File

@ -1,68 +0,0 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include "../init.h"
#include "../sg-regs.h"
int uniphier_pxs2_memconf_init(const struct uniphier_board_data *bd)
{
u32 tmp;
unsigned long size_per_word;
tmp = readl(SG_MEMCONF);
tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
switch (bd->dram_ch[2].width) {
case 16:
tmp |= SG_MEMCONF_CH2_NUM_1;
size_per_word = bd->dram_ch[2].size;
break;
case 32:
tmp |= SG_MEMCONF_CH2_NUM_2;
size_per_word = bd->dram_ch[2].size >> 1;
break;
default:
pr_err("error: unsupported DRAM Ch2 width\n");
return -EINVAL;
}
/* Set DDR size */
switch (size_per_word) {
case SZ_64M:
tmp |= SG_MEMCONF_CH2_SZ_64M;
break;
case SZ_128M:
tmp |= SG_MEMCONF_CH2_SZ_128M;
break;
case SZ_256M:
tmp |= SG_MEMCONF_CH2_SZ_256M;
break;
case SZ_512M:
tmp |= SG_MEMCONF_CH2_SZ_512M;
break;
case SZ_1G:
tmp |= SG_MEMCONF_CH2_SZ_1G;
break;
default:
pr_err("error: unsupported DRAM Ch2 size\n");
return -EINVAL;
}
if (size_per_word)
tmp &= ~SG_MEMCONF_CH2_DISABLE;
else
tmp |= SG_MEMCONF_CH2_DISABLE;
writel(tmp, SG_MEMCONF);
return 0;
}

60
arch/arm/mach-uniphier/memconf/memconf-sld3.c
View File

@ -1,60 +0,0 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include "../init.h"
#include "../sg-regs.h"
int uniphier_sld3_memconf_init(const struct uniphier_board_data *bd)
{
u32 tmp;
unsigned long size_per_word;
tmp = readl(SG_MEMCONF);
tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
switch (bd->dram_ch[2].width) {
case 16:
tmp |= SG_MEMCONF_CH2_NUM_1;
size_per_word = bd->dram_ch[2].size;
break;
case 32:
tmp |= SG_MEMCONF_CH2_NUM_2;
size_per_word = bd->dram_ch[2].size >> 1;
break;
default:
pr_err("error: unsupported DRAM Ch2 width\n");
return -EINVAL;
}
/* Set DDR size */
switch (size_per_word) {
case SZ_64M:
tmp |= SG_MEMCONF_CH2_SZ_64M;
break;
case SZ_128M:
tmp |= SG_MEMCONF_CH2_SZ_128M;
break;
case SZ_256M:
tmp |= SG_MEMCONF_CH2_SZ_256M;
break;
case SZ_512M:
tmp |= SG_MEMCONF_CH2_SZ_512M;
break;
default:
pr_err("error: unsupported DRAM Ch2 size\n");
return -EINVAL;
}
writel(tmp, SG_MEMCONF);
return 0;
}

107
arch/arm/mach-uniphier/memconf/memconf.c
View File

@ -1,107 +0,0 @@
/*
* Copyright (C) 2011-2015 Panasonic Corporation
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include "../init.h"
#include "../sg-regs.h"
int memconf_init(const struct uniphier_board_data *bd)
{
u32 tmp;
unsigned long size_per_word;
tmp = readl(SG_MEMCONF);
tmp &= ~(SG_MEMCONF_CH0_SZ_MASK | SG_MEMCONF_CH0_NUM_MASK);
switch (bd->dram_ch[0].width) {
case 16:
tmp |= SG_MEMCONF_CH0_NUM_1;
size_per_word = bd->dram_ch[0].size;
break;
case 32:
tmp |= SG_MEMCONF_CH0_NUM_2;
size_per_word = bd->dram_ch[0].size >> 1;
break;
default:
pr_err("error: unsupported DRAM Ch0 width\n");
return -EINVAL;
}
/* Set DDR size */
switch (size_per_word) {
case SZ_64M:
tmp |= SG_MEMCONF_CH0_SZ_64M;
break;
case SZ_128M:
tmp |= SG_MEMCONF_CH0_SZ_128M;
break;
case SZ_256M:
tmp |= SG_MEMCONF_CH0_SZ_256M;
break;
case SZ_512M:
tmp |= SG_MEMCONF_CH0_SZ_512M;
break;
case SZ_1G:
tmp |= SG_MEMCONF_CH0_SZ_1G;
break;
default:
pr_err("error: unsupported DRAM Ch0 size\n");
return -EINVAL;
}
tmp &= ~(SG_MEMCONF_CH1_SZ_MASK | SG_MEMCONF_CH1_NUM_MASK);
switch (bd->dram_ch[1].width) {
case 16:
tmp |= SG_MEMCONF_CH1_NUM_1;
size_per_word = bd->dram_ch[1].size;
break;
case 32:
tmp |= SG_MEMCONF_CH1_NUM_2;
size_per_word = bd->dram_ch[1].size >> 1;
break;
default:
pr_err("error: unsupported DRAM Ch1 width\n");
return -EINVAL;
}
switch (size_per_word) {
case SZ_64M:
tmp |= SG_MEMCONF_CH1_SZ_64M;
break;
case SZ_128M:
tmp |= SG_MEMCONF_CH1_SZ_128M;
break;
case SZ_256M:
tmp |= SG_MEMCONF_CH1_SZ_256M;
break;
case SZ_512M:
tmp |= SG_MEMCONF_CH1_SZ_512M;
break;
case SZ_1G:
tmp |= SG_MEMCONF_CH1_SZ_1G;
break;
default:
pr_err("error: unsupported DRAM Ch1 size\n");
return -EINVAL;
}
if (bd->dram_ch[0].base + bd->dram_ch[0].size < bd->dram_ch[1].base)
tmp |= SG_MEMCONF_SPARSEMEM;
else
tmp &= ~SG_MEMCONF_SPARSEMEM;
writel(tmp, SG_MEMCONF);
return 0;
}