mirrors/u-boot
1
0
Fork 0
mirror of https://source.denx.de/u-boot/u-boot.git synced 2025-08-17 20:57:01 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity

riscv: dts: jh7110: remove redundant parent nodes

Browse Source 
- use upstream alias name for cpu and timer nodes
- remove bootph-pre-ram hint from parent nodes
- drop S7 cpu core "okay" status

Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
E Shattow 2025-05-03 14:25:54 -07:00 committed by Leo Yu-Chi Liang
parent 97833f4cf6
commit 8b43f4a7be
1 changed files with 28 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

72
arch/riscv/dts/jh7110-u-boot.dtsi
View File

@ -6,46 +6,6 @@
#include <dt-bindings/reset/starfive,jh7110-crg.h>
/ {
cpus: cpus {
bootph-pre-ram;
S7_0: cpu@0 {
bootph-pre-ram;
status = "okay";
cpu0_intc: interrupt-controller {
bootph-pre-ram;
};
};
U74_1: cpu@1 {
bootph-pre-ram;
cpu1_intc: interrupt-controller {
bootph-pre-ram;
};
};
U74_2: cpu@2 {
bootph-pre-ram;
cpu2_intc: interrupt-controller {
bootph-pre-ram;
};
};
U74_3: cpu@3 {
bootph-pre-ram;
cpu3_intc: interrupt-controller {
bootph-pre-ram;
};
};
U74_4: cpu@4 {
bootph-pre-ram;
cpu4_intc: interrupt-controller {
bootph-pre-ram;
};
};
};
timer {
compatible = "riscv,timer";
interrupts-extended = <&cpu0_intc 5>,
@ -58,10 +18,6 @@
soc {
bootph-pre-ram;
clint: timer@2000000 {
bootph-pre-ram;
};
dmc: dmc@15700000 {
bootph-pre-ram;
compatible = "starfive,jh7110-dmc";
@ -78,6 +34,34 @@
};
};
&clint {
bootph-pre-ram;
};
&cpu0_intc {
bootph-pre-ram;
};
&cpu1_intc {
bootph-pre-ram;
};
&cpu2_intc {
bootph-pre-ram;
};
&cpu3_intc {
bootph-pre-ram;
};
&cpu4_intc {
bootph-pre-ram;
};
&cpus {
bootph-pre-ram;
};
&osc {
bootph-pre-ram;
};