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https://source.denx.de/u-boot/u-boot.git
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mtd: nand: raw: Remove unused octeontx_nand driver
As no platforms use this driver anymore let's go ahead and remove it. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
Michael Trimarchi
parent
cb34f23bdb
commit
8877bbe67a
@ -568,22 +568,6 @@ config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
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This flag prevent U-Boot reconfigure NAND flash controller and reuse
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This flag prevent U-Boot reconfigure NAND flash controller and reuse
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the NAND timing from 1st stage bootloader.
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the NAND timing from 1st stage bootloader.
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config NAND_OCTEONTX
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bool "Support for OcteonTX NAND controller"
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select SYS_NAND_SELF_INIT
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imply CMD_NAND
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help
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This enables Nand flash controller hardware found on the OcteonTX
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processors.
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config NAND_OCTEONTX_HW_ECC
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bool "Support Hardware ECC for OcteonTX NAND controller"
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depends on NAND_OCTEONTX
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default y
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help
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This enables Hardware BCH engine found on the OcteonTX processors to
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support ECC for NAND flash controller.
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config NAND_STM32_FMC2
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config NAND_STM32_FMC2
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bool "Support for NAND controller on STM32MP SoCs"
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bool "Support for NAND controller on STM32MP SoCs"
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depends on ARCH_STM32MP
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depends on ARCH_STM32MP
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@ -66,8 +66,6 @@ obj-$(CONFIG_NAND_MESON) += meson_nand.o
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obj-$(CONFIG_NAND_MXC) += mxc_nand.o
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obj-$(CONFIG_NAND_MXC) += mxc_nand.o
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obj-$(CONFIG_NAND_MXS) += mxs_nand.o
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obj-$(CONFIG_NAND_MXS) += mxs_nand.o
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obj-$(CONFIG_NAND_MXS_DT) += mxs_nand_dt.o
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obj-$(CONFIG_NAND_MXS_DT) += mxs_nand_dt.o
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obj-$(CONFIG_NAND_OCTEONTX) += octeontx_nand.o
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obj-$(CONFIG_NAND_OCTEONTX_HW_ECC) += octeontx_bch.o
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obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o
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obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o
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obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
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obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
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obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
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obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
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@ -1,422 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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#include <dm.h>
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#include <dm/of_access.h>
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#include <malloc.h>
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#include <memalign.h>
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#include <nand.h>
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#include <pci.h>
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#include <pci_ids.h>
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#include <time.h>
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#include <linux/bitfield.h>
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#include <linux/ctype.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/ioport.h>
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#include <linux/libfdt.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand_bch.h>
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#include <linux/mtd/nand_ecc.h>
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#include <asm/io.h>
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#include <asm/types.h>
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#include <asm/dma-mapping.h>
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#include <asm/arch/clock.h>
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#include "octeontx_bch.h"
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static LIST_HEAD(octeontx_bch_devices);
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static unsigned int num_vfs = BCH_NR_VF;
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static void *bch_pf;
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static void *bch_vf;
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static void *token;
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static bool bch_pf_initialized;
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static bool bch_vf_initialized;
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static int pci_enable_sriov(struct udevice *dev, int nr_virtfn)
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{
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int ret;
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ret = pci_sriov_init(dev, nr_virtfn);
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if (ret)
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printf("%s(%s): pci_sriov_init returned %d\n", __func__,
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dev->name, ret);
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return ret;
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}
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void *octeontx_bch_getv(void)
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{
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if (!bch_vf)
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return NULL;
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if (bch_vf_initialized && bch_pf_initialized)
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return bch_vf;
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else
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return NULL;
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}
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void octeontx_bch_putv(void *token)
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{
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bch_vf_initialized = !!token;
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bch_vf = token;
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}
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void *octeontx_bch_getp(void)
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{
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return token;
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}
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void octeontx_bch_putp(void *token)
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{
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bch_pf = token;
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bch_pf_initialized = !!token;
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}
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static int do_bch_init(struct bch_device *bch)
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{
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return 0;
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}
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static void bch_reset(struct bch_device *bch)
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{
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writeq(1, bch->reg_base + BCH_CTL);
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mdelay(2);
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}
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static void bch_disable(struct bch_device *bch)
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{
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writeq(~0ull, bch->reg_base + BCH_ERR_INT_ENA_W1C);
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writeq(~0ull, bch->reg_base + BCH_ERR_INT);
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bch_reset(bch);
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}
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static u32 bch_check_bist_status(struct bch_device *bch)
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{
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return readq(bch->reg_base + BCH_BIST_RESULT);
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}
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static int bch_device_init(struct bch_device *bch)
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{
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u64 bist;
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int rc;
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debug("%s: Resetting...\n", __func__);
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/* Reset the PF when probed first */
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bch_reset(bch);
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debug("%s: Checking BIST...\n", __func__);
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/* Check BIST status */
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bist = (u64)bch_check_bist_status(bch);
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if (bist) {
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dev_err(dev, "BCH BIST failed with code 0x%llx\n", bist);
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return -ENODEV;
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}
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/* Get max VQs/VFs supported by the device */
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bch->max_vfs = pci_sriov_get_totalvfs(bch->dev);
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debug("%s: %d vfs\n", __func__, bch->max_vfs);
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if (num_vfs > bch->max_vfs) {
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dev_warn(dev, "Num of VFs to enable %d is greater than max available. Enabling %d VFs.\n",
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num_vfs, bch->max_vfs);
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num_vfs = bch->max_vfs;
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}
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bch->vfs_enabled = bch->max_vfs;
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/* Get number of VQs/VFs to be enabled */
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/* TODO: Get CLK frequency */
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/* Reset device parameters */
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debug("%s: Doing initialization\n", __func__);
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rc = do_bch_init(bch);
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return rc;
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}
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static int bch_sriov_configure(struct udevice *dev, int numvfs)
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{
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struct bch_device *bch = dev_get_priv(dev);
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int ret = -EBUSY;
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debug("%s(%s, %d), bch: %p, vfs_in_use: %d, enabled: %d\n", __func__,
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dev->name, numvfs, bch, bch->vfs_in_use, bch->vfs_enabled);
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if (bch->vfs_in_use)
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goto exit;
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ret = 0;
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if (numvfs > 0) {
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debug("%s: Enabling sriov\n", __func__);
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ret = pci_enable_sriov(dev, numvfs);
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if (ret == 0) {
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bch->flags |= BCH_FLAG_SRIOV_ENABLED;
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ret = numvfs;
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bch->vfs_enabled = numvfs;
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}
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}
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debug("VFs enabled: %d\n", ret);
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exit:
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debug("%s: Returning %d\n", __func__, ret);
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return ret;
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}
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static int octeontx_pci_bchpf_probe(struct udevice *dev)
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{
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struct bch_device *bch;
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int ret;
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debug("%s(%s)\n", __func__, dev->name);
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bch = dev_get_priv(dev);
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if (!bch)
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return -ENOMEM;
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bch->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
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PCI_REGION_TYPE, PCI_REGION_MEM);
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bch->dev = dev;
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debug("%s: base address: %p\n", __func__, bch->reg_base);
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ret = bch_device_init(bch);
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if (ret) {
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printf("%s(%s): init returned %d\n", __func__, dev->name, ret);
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return ret;
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}
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INIT_LIST_HEAD(&bch->list);
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list_add(&bch->list, &octeontx_bch_devices);
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token = (void *)dev;
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debug("%s: Configuring SRIOV\n", __func__);
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bch_sriov_configure(dev, num_vfs);
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debug("%s: Done.\n", __func__);
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octeontx_bch_putp(bch);
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return 0;
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}
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static const struct pci_device_id octeontx_bchpf_pci_id_table[] = {
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{ PCI_VDEVICE(CAVIUM, PCI_DEVICE_ID_CAVIUM_BCH) },
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{},
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};
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static const struct pci_device_id octeontx_bchvf_pci_id_table[] = {
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{ PCI_VDEVICE(CAVIUM, PCI_DEVICE_ID_CAVIUM_BCHVF)},
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{},
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};
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/**
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* Given a data block calculate the ecc data and fill in the response
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*
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* @param[in] block 8-byte aligned pointer to data block to calculate ECC
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* @param block_size Size of block in bytes, must be a multiple of two.
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* @param bch_level Number of errors that must be corrected. The number of
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* parity bytes is equal to ((15 * bch_level) + 7) / 8.
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* Must be 4, 8, 16, 24, 32, 40, 48, 56, 60 or 64.
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* @param[out] ecc 8-byte aligned pointer to where ecc data should go
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* @param[in] resp pointer to where responses will be written.
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*
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* Return: Zero on success, negative on failure.
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*/
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int octeontx_bch_encode(struct bch_vf *vf, dma_addr_t block, u16 block_size,
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u8 bch_level, dma_addr_t ecc, dma_addr_t resp)
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{
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union bch_cmd cmd;
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int rc;
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memset(&cmd, 0, sizeof(cmd));
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cmd.s.cword.ecc_gen = eg_gen;
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cmd.s.cword.ecc_level = bch_level;
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cmd.s.cword.size = block_size;
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cmd.s.oword.ptr = ecc;
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cmd.s.iword.ptr = block;
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cmd.s.rword.ptr = resp;
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rc = octeontx_cmd_queue_write(QID_BCH, 1,
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sizeof(cmd) / sizeof(uint64_t), cmd.u);
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if (rc)
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return -1;
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octeontx_bch_write_doorbell(1, vf);
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return 0;
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}
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/**
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* Given a data block and ecc data correct the data block
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*
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* @param[in] block_ecc_in 8-byte aligned pointer to data block with ECC
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* data concatenated to the end to correct
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* @param block_size Size of block in bytes, must be a multiple of
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* two.
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* @param bch_level Number of errors that must be corrected. The
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* number of parity bytes is equal to
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* ((15 * bch_level) + 7) / 8.
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* Must be 4, 8, 16, 24, 32, 40, 48, 56, 60 or 64.
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* @param[out] block_out 8-byte aligned pointer to corrected data buffer.
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* This should not be the same as block_ecc_in.
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* @param[in] resp pointer to where responses will be written.
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*
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* Return: Zero on success, negative on failure.
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*/
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int octeontx_bch_decode(struct bch_vf *vf, dma_addr_t block_ecc_in,
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u16 block_size, u8 bch_level,
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dma_addr_t block_out, dma_addr_t resp)
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{
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union bch_cmd cmd;
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int rc;
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memset(&cmd, 0, sizeof(cmd));
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cmd.s.cword.ecc_gen = eg_correct;
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cmd.s.cword.ecc_level = bch_level;
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cmd.s.cword.size = block_size;
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cmd.s.oword.ptr = block_out;
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cmd.s.iword.ptr = block_ecc_in;
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cmd.s.rword.ptr = resp;
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rc = octeontx_cmd_queue_write(QID_BCH, 1,
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sizeof(cmd) / sizeof(uint64_t), cmd.u);
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if (rc)
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return -1;
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octeontx_bch_write_doorbell(1, vf);
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return 0;
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}
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EXPORT_SYMBOL(octeontx_bch_decode);
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int octeontx_bch_wait(struct bch_vf *vf, union bch_resp *resp,
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dma_addr_t handle)
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{
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ulong start = get_timer(0);
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__iormb(); /* HW is updating *resp */
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while (!resp->s.done && get_timer(start) < 10)
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__iormb(); /* HW is updating *resp */
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if (resp->s.done)
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return 0;
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return -ETIMEDOUT;
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}
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struct bch_q octeontx_bch_q[QID_MAX];
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static int octeontx_cmd_queue_initialize(struct udevice *dev, int queue_id,
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int max_depth, int fpa_pool,
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int pool_size)
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{
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/* some params are for later merge with CPT or cn83xx */
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struct bch_q *q = &octeontx_bch_q[queue_id];
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unsigned long paddr;
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u64 *chunk_buffer;
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int chunk = max_depth + 1;
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int i, size;
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if ((unsigned int)queue_id >= QID_MAX)
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return -EINVAL;
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if (max_depth & chunk) /* must be 2^N - 1 */
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return -EINVAL;
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size = NQS * chunk * sizeof(u64);
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chunk_buffer = dma_alloc_coherent(size, &paddr);
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if (!chunk_buffer)
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return -ENOMEM;
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q->base_paddr = paddr;
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|
||||||
q->dev = dev;
|
|
||||||
q->index = 0;
|
|
||||||
q->max_depth = max_depth;
|
|
||||||
q->pool_size_m1 = pool_size;
|
|
||||||
q->base_vaddr = chunk_buffer;
|
|
||||||
|
|
||||||
for (i = 0; i < NQS; i++) {
|
|
||||||
u64 *ixp;
|
|
||||||
int inext = (i + 1) * chunk - 1;
|
|
||||||
int j = (i + 1) % NQS;
|
|
||||||
int jnext = j * chunk;
|
|
||||||
dma_addr_t jbase = q->base_paddr + jnext * sizeof(u64);
|
|
||||||
|
|
||||||
ixp = &chunk_buffer[inext];
|
|
||||||
*ixp = jbase;
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int octeontx_pci_bchvf_probe(struct udevice *dev)
|
|
||||||
{
|
|
||||||
struct bch_vf *vf;
|
|
||||||
union bch_vqx_ctl ctl;
|
|
||||||
union bch_vqx_cmd_buf cbuf;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
debug("%s(%s)\n", __func__, dev->name);
|
|
||||||
vf = dev_get_priv(dev);
|
|
||||||
if (!vf)
|
|
||||||
return -ENOMEM;
|
|
||||||
|
|
||||||
vf->dev = dev;
|
|
||||||
|
|
||||||
/* Map PF's configuration registers */
|
|
||||||
vf->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
|
|
||||||
PCI_REGION_TYPE, PCI_REGION_MEM);
|
|
||||||
debug("%s: reg base: %p\n", __func__, vf->reg_base);
|
|
||||||
|
|
||||||
err = octeontx_cmd_queue_initialize(dev, QID_BCH, QDEPTH - 1, 0,
|
|
||||||
sizeof(union bch_cmd) * QDEPTH);
|
|
||||||
if (err) {
|
|
||||||
dev_err(dev, "octeontx_cmd_queue_initialize() failed\n");
|
|
||||||
goto release;
|
|
||||||
}
|
|
||||||
|
|
||||||
ctl.u = readq(vf->reg_base + BCH_VQX_CTL(0));
|
|
||||||
|
|
||||||
cbuf.u = 0;
|
|
||||||
cbuf.s.ldwb = 1;
|
|
||||||
cbuf.s.dfb = 1;
|
|
||||||
cbuf.s.size = QDEPTH;
|
|
||||||
writeq(cbuf.u, vf->reg_base + BCH_VQX_CMD_BUF(0));
|
|
||||||
|
|
||||||
writeq(ctl.u, vf->reg_base + BCH_VQX_CTL(0));
|
|
||||||
|
|
||||||
writeq(octeontx_bch_q[QID_BCH].base_paddr,
|
|
||||||
vf->reg_base + BCH_VQX_CMD_PTR(0));
|
|
||||||
|
|
||||||
octeontx_bch_putv(vf);
|
|
||||||
|
|
||||||
debug("%s: bch vf initialization complete\n", __func__);
|
|
||||||
|
|
||||||
if (octeontx_bch_getv())
|
|
||||||
return octeontx_pci_nand_deferred_probe();
|
|
||||||
|
|
||||||
return -1;
|
|
||||||
|
|
||||||
release:
|
|
||||||
return err;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int octeontx_pci_bchpf_remove(struct udevice *dev)
|
|
||||||
{
|
|
||||||
struct bch_device *bch = dev_get_priv(dev);
|
|
||||||
|
|
||||||
bch_disable(bch);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
U_BOOT_DRIVER(octeontx_pci_bchpf) = {
|
|
||||||
.name = BCHPF_DRIVER_NAME,
|
|
||||||
.id = UCLASS_MISC,
|
|
||||||
.probe = octeontx_pci_bchpf_probe,
|
|
||||||
.remove = octeontx_pci_bchpf_remove,
|
|
||||||
.priv_auto = sizeof(struct bch_device),
|
|
||||||
.flags = DM_FLAG_OS_PREPARE,
|
|
||||||
};
|
|
||||||
|
|
||||||
U_BOOT_DRIVER(octeontx_pci_bchvf) = {
|
|
||||||
.name = BCHVF_DRIVER_NAME,
|
|
||||||
.id = UCLASS_MISC,
|
|
||||||
.probe = octeontx_pci_bchvf_probe,
|
|
||||||
.priv_auto = sizeof(struct bch_vf),
|
|
||||||
};
|
|
||||||
|
|
||||||
U_BOOT_PCI_DEVICE(octeontx_pci_bchpf, octeontx_bchpf_pci_id_table);
|
|
||||||
U_BOOT_PCI_DEVICE(octeontx_pci_bchvf, octeontx_bchvf_pci_id_table);
|
|
||||||
@ -1,131 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0
|
|
||||||
*
|
|
||||||
* Copyright (C) 2018 Marvell International Ltd.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __OCTEONTX_BCH_H__
|
|
||||||
#define __OCTEONTX_BCH_H__
|
|
||||||
|
|
||||||
#include "octeontx_bch_regs.h"
|
|
||||||
|
|
||||||
/* flags to indicate the features supported */
|
|
||||||
#define BCH_FLAG_SRIOV_ENABLED BIT(1)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BCH Registers map for 81xx
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* PF registers */
|
|
||||||
#define BCH_CTL 0x0ull
|
|
||||||
#define BCH_ERR_CFG 0x10ull
|
|
||||||
#define BCH_BIST_RESULT 0x80ull
|
|
||||||
#define BCH_ERR_INT 0x88ull
|
|
||||||
#define BCH_ERR_INT_W1S 0x90ull
|
|
||||||
#define BCH_ERR_INT_ENA_W1C 0xA0ull
|
|
||||||
#define BCH_ERR_INT_ENA_W1S 0xA8ull
|
|
||||||
|
|
||||||
/* VF registers */
|
|
||||||
#define BCH_VQX_CTL(z) 0x0ull
|
|
||||||
#define BCH_VQX_CMD_BUF(z) 0x8ull
|
|
||||||
#define BCH_VQX_CMD_PTR(z) 0x20ull
|
|
||||||
#define BCH_VQX_DOORBELL(z) 0x800ull
|
|
||||||
|
|
||||||
#define BCHPF_DRIVER_NAME "octeontx-bchpf"
|
|
||||||
#define BCHVF_DRIVER_NAME "octeontx-bchvf"
|
|
||||||
|
|
||||||
struct bch_device {
|
|
||||||
struct list_head list;
|
|
||||||
u8 max_vfs;
|
|
||||||
u8 vfs_enabled;
|
|
||||||
u8 vfs_in_use;
|
|
||||||
u32 flags;
|
|
||||||
void __iomem *reg_base;
|
|
||||||
struct udevice *dev;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct bch_vf {
|
|
||||||
u16 flags;
|
|
||||||
u8 vfid;
|
|
||||||
u8 node;
|
|
||||||
u8 priority;
|
|
||||||
struct udevice *dev;
|
|
||||||
void __iomem *reg_base;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct buf_ptr {
|
|
||||||
u8 *vptr;
|
|
||||||
dma_addr_t dma_addr;
|
|
||||||
u16 size;
|
|
||||||
};
|
|
||||||
|
|
||||||
void *octeontx_bch_getv(void);
|
|
||||||
void octeontx_bch_putv(void *token);
|
|
||||||
void *octeontx_bch_getp(void);
|
|
||||||
void octeontx_bch_putp(void *token);
|
|
||||||
int octeontx_bch_wait(struct bch_vf *vf, union bch_resp *resp,
|
|
||||||
dma_addr_t handle);
|
|
||||||
/**
|
|
||||||
* Given a data block calculate the ecc data and fill in the response
|
|
||||||
*
|
|
||||||
* @param[in] block 8-byte aligned pointer to data block to calculate ECC
|
|
||||||
* @param block_size Size of block in bytes, must be a multiple of two.
|
|
||||||
* @param bch_level Number of errors that must be corrected. The number of
|
|
||||||
* parity bytes is equal to ((15 * bch_level) + 7) / 8.
|
|
||||||
* Must be 4, 8, 16, 24, 32, 40, 48, 56, 60 or 64.
|
|
||||||
* @param[out] ecc 8-byte aligned pointer to where ecc data should go
|
|
||||||
* @param[in] resp pointer to where responses will be written.
|
|
||||||
*
|
|
||||||
* Return: Zero on success, negative on failure.
|
|
||||||
*/
|
|
||||||
int octeontx_bch_encode(struct bch_vf *vf, dma_addr_t block, u16 block_size,
|
|
||||||
u8 bch_level, dma_addr_t ecc, dma_addr_t resp);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Given a data block and ecc data correct the data block
|
|
||||||
*
|
|
||||||
* @param[in] block_ecc_in 8-byte aligned pointer to data block with ECC
|
|
||||||
* data concatenated to the end to correct
|
|
||||||
* @param block_size Size of block in bytes, must be a multiple of
|
|
||||||
* two.
|
|
||||||
* @param bch_level Number of errors that must be corrected. The
|
|
||||||
* number of parity bytes is equal to
|
|
||||||
* ((15 * bch_level) + 7) / 8.
|
|
||||||
* Must be 4, 8, 16, 24, 32, 40, 48, 56, 60 or 64.
|
|
||||||
* @param[out] block_out 8-byte aligned pointer to corrected data buffer.
|
|
||||||
* This should not be the same as block_ecc_in.
|
|
||||||
* @param[in] resp pointer to where responses will be written.
|
|
||||||
*
|
|
||||||
* Return: Zero on success, negative on failure.
|
|
||||||
*/
|
|
||||||
|
|
||||||
int octeontx_bch_decode(struct bch_vf *vf, dma_addr_t block_ecc_in,
|
|
||||||
u16 block_size, u8 bch_level,
|
|
||||||
dma_addr_t block_out, dma_addr_t resp);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Ring the BCH doorbell telling it that new commands are
|
|
||||||
* available.
|
|
||||||
*
|
|
||||||
* @param num_commands Number of new commands
|
|
||||||
* @param vf virtual function handle
|
|
||||||
*/
|
|
||||||
static inline void octeontx_bch_write_doorbell(u64 num_commands,
|
|
||||||
struct bch_vf *vf)
|
|
||||||
{
|
|
||||||
u64 num_words = num_commands * sizeof(union bch_cmd) / sizeof(uint64_t);
|
|
||||||
|
|
||||||
writeq(num_words, vf->reg_base + BCH_VQX_DOORBELL(0));
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Since it's possible (and even likely) that the NAND device will be probed
|
|
||||||
* before the BCH device has been probed, we may need to defer the probing.
|
|
||||||
*
|
|
||||||
* In this case, the initial probe returns success but the actual probing
|
|
||||||
* is deferred until the BCH VF has been probed.
|
|
||||||
*
|
|
||||||
* Return: 0 for success, otherwise error
|
|
||||||
*/
|
|
||||||
int octeontx_pci_nand_deferred_probe(void);
|
|
||||||
|
|
||||||
#endif /* __OCTEONTX_BCH_H__ */
|
|
||||||
@ -1,167 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0
|
|
||||||
*
|
|
||||||
* Copyright (C) 2018 Marvell International Ltd.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __OCTEONTX_BCH_REGS_H__
|
|
||||||
#define __OCTEONTX_BCH_REGS_H__
|
|
||||||
|
|
||||||
#define BCH_NR_VF 1
|
|
||||||
|
|
||||||
union bch_cmd {
|
|
||||||
u64 u[4];
|
|
||||||
struct fields {
|
|
||||||
struct {
|
|
||||||
u64 size:12;
|
|
||||||
u64 reserved_12_31:20;
|
|
||||||
u64 ecc_level:4;
|
|
||||||
u64 reserved_36_61:26;
|
|
||||||
u64 ecc_gen:2;
|
|
||||||
} cword;
|
|
||||||
struct {
|
|
||||||
u64 ptr:49;
|
|
||||||
u64 reserved_49_55:7;
|
|
||||||
u64 nc:1;
|
|
||||||
u64 fw:1;
|
|
||||||
u64 reserved_58_63:6;
|
|
||||||
} oword;
|
|
||||||
struct {
|
|
||||||
u64 ptr:49;
|
|
||||||
u64 reserved_49_55:7;
|
|
||||||
u64 nc:1;
|
|
||||||
u64 reserved_57_63:7;
|
|
||||||
} iword;
|
|
||||||
struct {
|
|
||||||
u64 ptr:49;
|
|
||||||
u64 reserved_49_63:15;
|
|
||||||
} rword;
|
|
||||||
} s;
|
|
||||||
};
|
|
||||||
|
|
||||||
enum ecc_gen {
|
|
||||||
eg_correct,
|
|
||||||
eg_copy,
|
|
||||||
eg_gen,
|
|
||||||
eg_copy3,
|
|
||||||
};
|
|
||||||
|
|
||||||
/** Response from BCH instruction */
|
|
||||||
union bch_resp {
|
|
||||||
u16 u16;
|
|
||||||
struct {
|
|
||||||
u16 num_errors:7; /** Number of errors in block */
|
|
||||||
u16 zero:6; /** Always zero, ignore */
|
|
||||||
u16 erased:1; /** Block is erased */
|
|
||||||
u16 uncorrectable:1;/** too many bits flipped */
|
|
||||||
u16 done:1; /** Block is done */
|
|
||||||
} s;
|
|
||||||
};
|
|
||||||
|
|
||||||
union bch_vqx_ctl {
|
|
||||||
u64 u;
|
|
||||||
struct {
|
|
||||||
u64 reserved_0:1;
|
|
||||||
u64 cmd_be:1;
|
|
||||||
u64 max_read:4;
|
|
||||||
u64 reserved_6_15:10;
|
|
||||||
u64 erase_disable:1;
|
|
||||||
u64 one_cmd:1;
|
|
||||||
u64 early_term:4;
|
|
||||||
u64 reserved_22_63:42;
|
|
||||||
} s;
|
|
||||||
};
|
|
||||||
|
|
||||||
union bch_vqx_cmd_buf {
|
|
||||||
u64 u;
|
|
||||||
struct {
|
|
||||||
u64 reserved_0_32:33;
|
|
||||||
u64 size:13;
|
|
||||||
u64 dfb:1;
|
|
||||||
u64 ldwb:1;
|
|
||||||
u64 reserved_48_63:16;
|
|
||||||
} s;
|
|
||||||
};
|
|
||||||
|
|
||||||
/* keep queue state indexed, even though just one supported here,
|
|
||||||
* for later generalization to similarly-shaped queues on other Cavium devices
|
|
||||||
*/
|
|
||||||
enum {
|
|
||||||
QID_BCH,
|
|
||||||
QID_MAX
|
|
||||||
};
|
|
||||||
|
|
||||||
struct bch_q {
|
|
||||||
struct udevice *dev;
|
|
||||||
int index;
|
|
||||||
u16 max_depth;
|
|
||||||
u16 pool_size_m1;
|
|
||||||
u64 *base_vaddr;
|
|
||||||
dma_addr_t base_paddr;
|
|
||||||
};
|
|
||||||
|
|
||||||
extern struct bch_q octeontx_bch_q[QID_MAX];
|
|
||||||
|
|
||||||
/* with one dma-mapped area, virt<->phys conversions by +/- (vaddr-paddr) */
|
|
||||||
static inline dma_addr_t qphys(int qid, void *v)
|
|
||||||
{
|
|
||||||
struct bch_q *q = &octeontx_bch_q[qid];
|
|
||||||
int off = (u8 *)v - (u8 *)q->base_vaddr;
|
|
||||||
|
|
||||||
return q->base_paddr + off;
|
|
||||||
}
|
|
||||||
|
|
||||||
#define octeontx_ptr_to_phys(v) qphys(QID_BCH, (v))
|
|
||||||
|
|
||||||
static inline void *qvirt(int qid, dma_addr_t p)
|
|
||||||
{
|
|
||||||
struct bch_q *q = &octeontx_bch_q[qid];
|
|
||||||
int off = p - q->base_paddr;
|
|
||||||
|
|
||||||
return q->base_vaddr + off;
|
|
||||||
}
|
|
||||||
|
|
||||||
#define octeontx_phys_to_ptr(p) qvirt(QID_BCH, (p))
|
|
||||||
|
|
||||||
/* plenty for interleaved r/w on two planes with 16k page, ecc_size 1k */
|
|
||||||
/* QDEPTH >= 16, as successive chunks must align on 128-byte boundaries */
|
|
||||||
#define QDEPTH 256 /* u64s in a command queue chunk, incl next-pointer */
|
|
||||||
#define NQS 1 /* linked chunks in the chain */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Write an arbitrary number of command words to a command queue.
|
|
||||||
* This is a generic function; the fixed number of command word
|
|
||||||
* functions yield higher performance.
|
|
||||||
*
|
|
||||||
* Could merge with crypto version for FPA use on cn83xx
|
|
||||||
*/
|
|
||||||
static inline int octeontx_cmd_queue_write(int queue_id, bool use_locking,
|
|
||||||
int cmd_count, const u64 *cmds)
|
|
||||||
{
|
|
||||||
int ret = 0;
|
|
||||||
u64 *cmd_ptr;
|
|
||||||
struct bch_q *qptr = &octeontx_bch_q[queue_id];
|
|
||||||
|
|
||||||
if (unlikely(cmd_count < 1 || cmd_count > 32))
|
|
||||||
return -EINVAL;
|
|
||||||
if (unlikely(!cmds))
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
cmd_ptr = qptr->base_vaddr;
|
|
||||||
|
|
||||||
while (cmd_count > 0) {
|
|
||||||
int slot = qptr->index % (QDEPTH * NQS);
|
|
||||||
|
|
||||||
if (slot % QDEPTH != QDEPTH - 1) {
|
|
||||||
cmd_ptr[slot] = *cmds++;
|
|
||||||
cmd_count--;
|
|
||||||
}
|
|
||||||
|
|
||||||
qptr->index++;
|
|
||||||
}
|
|
||||||
|
|
||||||
__iowmb(); /* flush commands before ringing bell */
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* __OCTEONTX_BCH_REGS_H__ */
|
|
||||||
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Reference in New Issue
Block a user