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board: phytec: phycore_imx8mp: Make RAM size configuration fix

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We might not be able to always rely on the EEPROM introspection data.
So add a config option alternative which configures the RAM size
to a fix value.

We still try to read the EEPROM introspection data at this point.
So we can print the SoM information if available.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
This commit is contained in:
Teresa Remmet 2024-05-28 15:35:14 +02:00 committed by Fabio Estevam
parent cff451e03f
commit 8869c2324d
2 changed files with 72 additions and 6 deletions
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48
board/phytec/phycore_imx8mp/Kconfig
View File

@ -12,5 +12,53 @@ config SYS_CONFIG_NAME
config IMX_CONFIG
default "board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg"
config PHYCORE_IMX8MP_RAM_SIZE_FIX
bool "Set phyCORE-i.MX8MP RAM size fix instead of detecting"
default false
help
RAM size is automatic being detected with the help of
the EEPROM introspection data. Set RAM size to a fix value
instead.
choice
prompt "phyCORE-i.MX8MP RAM size"
depends on PHYCORE_IMX8MP_RAM_SIZE_FIX
default PHYCORE_IMX8MP_RAM_SIZE_2GB
config PHYCORE_IMX8MP_RAM_SIZE_1GB
bool "1GB RAM"
help
Set RAM size fix to 1GB for phyCORE-i.MX8MP.
RAM frequency is configured independent.
config PHYCORE_IMX8MP_RAM_SIZE_2GB
bool "2GB RAM"
help
Set RAM size fix to 2GB for phyCORE-i.MX8MP.
RAM frequency is configured independent.
config PHYCORE_IMX8MP_RAM_SIZE_4GB
bool "4GB RAM"
help
Set RAM size fix to 4GB for phyCORE-i.MX8MP.
RAM frequency is configured independent.
config PHYCORE_IMX8MP_RAM_SIZE_8GB
bool "8GB RAM"
select PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS
help
Set RAM size fix to 8GB for phyCORE-i.MX8MP.
Only 2GHz RAMs are supported.
endchoice
config PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS
bool "Use 2GHz RAM timings"
depends on PHYCORE_IMX8MP_RAM_SIZE_FIX
default false
help
Use fix 2GHz RAM timings for phyCORE-i.MX8MP instead of
1.5GHz timings.
source "board/phytec/common/Kconfig"
endif

30
board/phytec/phycore_imx8mp/spl.c
View File

@ -49,20 +49,38 @@ void spl_dram_init(void)
ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR,
EEPROM_ADDR_FALLBACK);
if (ret)
if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX))
goto out;
ret = phytec_imx8m_detect(NULL);
if (!ret)
phytec_print_som_info(NULL);
u8 rev = phytec_get_rev(NULL);
u8 somtype = phytec_get_som_type(NULL);
if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX)) {
if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_1GB))
size = PHYTEC_IMX8MP_DDR_1GB;
else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_2GB))
size = PHYTEC_IMX8MP_DDR_2GB;
else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_4GB))
size = PHYTEC_IMX8MP_DDR_4GB;
else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_8GB))
size = PHYTEC_IMX8MP_DDR_8GB;
if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS)) {
if (size == PHYTEC_IMX8MP_DDR_4GB)
size = PHYTEC_IMX8MP_DDR_4GB_2GHZ;
else
use_2ghz_timings = true;
}
} else {
u8 rev = phytec_get_rev(NULL);
u8 somtype = phytec_get_som_type(NULL);
if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1)))
use_2ghz_timings = true;
if (rev != PHYTEC_EEPROM_INVAL &&
(rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1)))
use_2ghz_timings = true;
size = phytec_get_imx8m_ddr_size(NULL);
size = phytec_get_imx8m_ddr_size(NULL);
}
switch (size) {
case PHYTEC_IMX8MP_DDR_1GB: