From 0d5ddcc50b2900ddcbb32685525ad8ab60c696e8 Mon Sep 17 00:00:00 2001 From: Hrushikesh Salunke Date: Mon, 16 Feb 2026 15:58:29 +0530 Subject: [PATCH 01/10] arm: mach-k3: j784s4: Update SoC autogen data to enable PCIe boot To enable PCIe boot on J784S4 SoC SERDES0 and PCIE1 should be enabled and configured at the R5 stage. Add the required clk-data and dev-data for SERDES0 and PCIE1. Signed-off-by: Hrushikesh Salunke Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar --- arch/arm/mach-k3/r5/j784s4/clk-data.c | 190 ++++++++++++++++++++++++-- arch/arm/mach-k3/r5/j784s4/dev-data.c | 45 +++--- 2 files changed, 204 insertions(+), 31 deletions(-) diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c index 24780eb6562..228b424d3f2 100644 --- a/arch/arm/mach-k3/r5/j784s4/clk-data.c +++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof . * - * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2026 Texas Instruments Incorporated - https://www.ti.com/ */ #include @@ -64,13 +64,13 @@ static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = { "board_0_cpts0_rft_clk_out", "board_0_mcu_ext_refclk0_out", "board_0_ext_refclk1_out", + "wiz16b8m4ct3_main_0_ip2_ln0_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln1_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln2_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln3_txmclk", NULL, NULL, - NULL, - NULL, - NULL, - NULL, - NULL, + "wiz16b8m4ct3_main_0_ip1_ln2_txmclk", NULL, "hsdiv4_16fft_mcu_2_hsdivout1_clk", "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", @@ -166,6 +166,31 @@ static const char * const emmcsd1_lb_clksel_out0_parents[] = { "board_0_mmc1_clk_out", }; +static const char * const usb0_serdes_refclk_mux_out0_parents[] = { + "wiz16b8m4ct3_main_0_ip3_ln3_refclk", + NULL, +}; + +static const char * const usb0_serdes_rxclk_mux_out0_parents[] = { + "wiz16b8m4ct3_main_0_ip3_ln3_rxclk", + NULL, +}; + +static const char * const usb0_serdes_rxfclk_mux_out0_parents[] = { + "wiz16b8m4ct3_main_0_ip3_ln3_rxfclk", + NULL, +}; + +static const char * const usb0_serdes_txfclk_mux_out0_parents[] = { + "wiz16b8m4ct3_main_0_ip3_ln3_txfclk", + NULL, +}; + +static const char * const usb0_serdes_txmclk_mux_out0_parents[] = { + "wiz16b8m4ct3_main_0_ip3_ln3_txmclk", + NULL, +}; + static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { "main_pll_hfosc_sel_out0", "hsdiv4_16fft_main_0_hsdivout0_clk", @@ -197,18 +222,44 @@ static const char * const gtc_clk_mux_out0_parents[] = { "board_0_cpts0_rft_clk_out", "board_0_mcu_ext_refclk0_out", "board_0_ext_refclk1_out", + "wiz16b8m4ct3_main_0_ip2_ln0_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln1_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln2_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln3_txmclk", NULL, NULL, - NULL, - NULL, - NULL, - NULL, - NULL, + "wiz16b8m4ct3_main_0_ip1_ln2_txmclk", NULL, "hsdiv4_16fft_mcu_2_hsdivout1_clk", "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", }; +static const char * const pcien_cpts_rclk_mux_out1_parents[] = { + "hsdiv4_16fft_main_3_hsdivout1_clk", + "postdiv3_16fft_main_0_hsdivout6_clk", + "board_0_mcu_cpts0_rft_clk_out", + "board_0_cpts0_rft_clk_out", + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + "wiz16b8m4ct3_main_0_ip2_ln0_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln1_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln2_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln3_txmclk", + NULL, + NULL, + "wiz16b8m4ct3_main_0_ip1_ln2_txmclk", + NULL, + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const serdes0_core_refclk_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", + "hsdiv4_16fft_main_3_hsdivout4_clk", + "hsdiv4_16fft_main_2_hsdivout4_clk", +}; + static const struct clk_data clk_list[] = { CLK_FIXED_RATE("osc_27_mhz", 27000000, 0), CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), @@ -270,11 +321,17 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0), CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_serdes0_refclk_n_out", 0, 0), + CLK_FIXED_RATE("board_0_serdes0_refclk_p_out", 0, 0), CLK_FIXED_RATE("board_0_tck_out", 0, 0), CLK_FIXED_RATE("board_0_vout0_extpclkin_out", 0, 0), CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0, 0), + CLK_FIXED_RATE("pcie_g3x4_128_main_1_pcie_lane0_txclk", 0, 0), + CLK_FIXED_RATE("pcie_g3x4_128_main_1_pcie_lane1_txclk", 0, 0), + CLK_FIXED_RATE("pcie_g3x4_128_main_1_pcie_lane2_txclk", 0, 0), + CLK_FIXED_RATE("pcie_g3x4_128_main_1_pcie_lane3_txclk", 0, 0), CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0, 2000000000), CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), @@ -294,8 +351,42 @@ static const struct clk_data clk_list[] = { CLK_DIV("postdiv3_16fft_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0), CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0, 0), + CLK_FIXED_RATE("usb3p0ss_16ffc_main_0_pipe_txclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_cmn_refclk_m", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_cmn_refclk_p", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip1_ln2_txmclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln0_refclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln0_rxclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln0_rxfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln0_txfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln0_txmclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln1_refclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln1_rxclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln1_rxfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln1_txfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln1_txmclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln2_refclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln2_rxclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln2_rxfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln2_txfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln2_txmclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln3_refclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln3_rxclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln3_rxfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln3_txfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln3_txmclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip3_ln3_refclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip3_ln3_rxclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip3_ln3_rxfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip3_ln3_txfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip3_ln3_txmclk", 0, 0), CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2, 0x1080b4, 16, 1, 0), CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), + CLK_MUX("usb0_serdes_refclk_mux_out0", usb0_serdes_refclk_mux_out0_parents, 2, 0x104000, 27, 1, 0), + CLK_MUX("usb0_serdes_rxclk_mux_out0", usb0_serdes_rxclk_mux_out0_parents, 2, 0x104000, 27, 1, 0), + CLK_MUX("usb0_serdes_rxfclk_mux_out0", usb0_serdes_rxfclk_mux_out0_parents, 2, 0x104000, 27, 1, 0), + CLK_MUX("usb0_serdes_txfclk_mux_out0", usb0_serdes_txfclk_mux_out0_parents, 2, 0x104000, 27, 1, 0), + CLK_MUX("usb0_serdes_txmclk_mux_out0", usb0_serdes_txmclk_mux_out0_parents, 2, 0x104000, 27, 1, 0), CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), CLK_DIV("hsdiv0_16fft_main_26_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_26_foutvcop_clk", 0x69a080, 0, 7, 0, 0), CLK_DIV("hsdiv0_16fft_main_27_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_27_foutvcop_clk", 0x69b080, 0, 7, 0, 0), @@ -310,14 +401,18 @@ static const struct clk_data clk_list[] = { CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682090, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683090, 0, 7, 0, 0), CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), CLK_MUX("dpi0_ext_clksel_out0", dpi0_ext_clksel_out0_parents, 2, 0x108300, 0, 1, 0), CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0), CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0), CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0), + CLK_MUX("pcien_cpts_rclk_mux_out1", pcien_cpts_rclk_mux_out1_parents, 16, 0x108084, 0, 4, 0), + CLK_MUX("serdes0_core_refclk_out0", serdes0_core_refclk_out0_parents, 4, 0x108400, 0, 2, 0), CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000), CLK_DIV("usart_programmable_clock_divider_out5", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081d4, 0, 2, 0, 0), CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0), @@ -338,6 +433,11 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(61, 4, "board_0_cpts0_rft_clk_out"), DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"), DEV_CLK(61, 6, "board_0_ext_refclk1_out"), + DEV_CLK(61, 7, "wiz16b8m4ct3_main_0_ip2_ln0_txmclk"), + DEV_CLK(61, 8, "wiz16b8m4ct3_main_0_ip2_ln1_txmclk"), + DEV_CLK(61, 9, "wiz16b8m4ct3_main_0_ip2_ln2_txmclk"), + DEV_CLK(61, 10, "wiz16b8m4ct3_main_0_ip2_ln3_txmclk"), + DEV_CLK(61, 13, "wiz16b8m4ct3_main_0_ip1_ln2_txmclk"), DEV_CLK(61, 15, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), DEV_CLK(61, 16, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), @@ -349,6 +449,11 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(63, 7, "board_0_cpts0_rft_clk_out"), DEV_CLK(63, 8, "board_0_mcu_ext_refclk0_out"), DEV_CLK(63, 9, "board_0_ext_refclk1_out"), + DEV_CLK(63, 10, "wiz16b8m4ct3_main_0_ip2_ln0_txmclk"), + DEV_CLK(63, 11, "wiz16b8m4ct3_main_0_ip2_ln1_txmclk"), + DEV_CLK(63, 12, "wiz16b8m4ct3_main_0_ip2_ln2_txmclk"), + DEV_CLK(63, 13, "wiz16b8m4ct3_main_0_ip2_ln3_txmclk"), + DEV_CLK(63, 16, "wiz16b8m4ct3_main_0_ip1_ln2_txmclk"), DEV_CLK(63, 18, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), DEV_CLK(63, 19, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(63, 20, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), @@ -404,6 +509,8 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 239, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(157, 243, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 245, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 324, "wiz16b8m4ct3_main_0_cmn_refclk_m"), + DEV_CLK(157, 326, "wiz16b8m4ct3_main_0_cmn_refclk_p"), DEV_CLK(157, 354, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 359, "dpi0_ext_clksel_out0"), DEV_CLK(157, 360, "mshsi2c_wkup_0_porscl"), @@ -461,6 +568,42 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(279, 2, "wkup_i2c_mcupll_bypass_out0"), DEV_CLK(279, 3, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), DEV_CLK(279, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(333, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(333, 2, "pcien_cpts_rclk_mux_out1"), + DEV_CLK(333, 3, "hsdiv4_16fft_main_3_hsdivout1_clk"), + DEV_CLK(333, 4, "postdiv3_16fft_main_0_hsdivout6_clk"), + DEV_CLK(333, 5, "board_0_mcu_cpts0_rft_clk_out"), + DEV_CLK(333, 6, "board_0_cpts0_rft_clk_out"), + DEV_CLK(333, 7, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(333, 8, "board_0_ext_refclk1_out"), + DEV_CLK(333, 9, "wiz16b8m4ct3_main_0_ip2_ln0_txmclk"), + DEV_CLK(333, 10, "wiz16b8m4ct3_main_0_ip2_ln1_txmclk"), + DEV_CLK(333, 11, "wiz16b8m4ct3_main_0_ip2_ln2_txmclk"), + DEV_CLK(333, 12, "wiz16b8m4ct3_main_0_ip2_ln3_txmclk"), + DEV_CLK(333, 15, "wiz16b8m4ct3_main_0_ip1_ln2_txmclk"), + DEV_CLK(333, 17, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), + DEV_CLK(333, 18, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(333, 19, "wiz16b8m4ct3_main_0_ip2_ln0_refclk"), + DEV_CLK(333, 20, "wiz16b8m4ct3_main_0_ip2_ln0_rxclk"), + DEV_CLK(333, 21, "wiz16b8m4ct3_main_0_ip2_ln0_rxfclk"), + DEV_CLK(333, 23, "wiz16b8m4ct3_main_0_ip2_ln0_txfclk"), + DEV_CLK(333, 24, "wiz16b8m4ct3_main_0_ip2_ln0_txmclk"), + DEV_CLK(333, 25, "wiz16b8m4ct3_main_0_ip2_ln1_refclk"), + DEV_CLK(333, 26, "wiz16b8m4ct3_main_0_ip2_ln1_rxclk"), + DEV_CLK(333, 27, "wiz16b8m4ct3_main_0_ip2_ln1_rxfclk"), + DEV_CLK(333, 29, "wiz16b8m4ct3_main_0_ip2_ln1_txfclk"), + DEV_CLK(333, 30, "wiz16b8m4ct3_main_0_ip2_ln1_txmclk"), + DEV_CLK(333, 31, "wiz16b8m4ct3_main_0_ip2_ln2_refclk"), + DEV_CLK(333, 32, "wiz16b8m4ct3_main_0_ip2_ln2_rxclk"), + DEV_CLK(333, 33, "wiz16b8m4ct3_main_0_ip2_ln2_rxfclk"), + DEV_CLK(333, 35, "wiz16b8m4ct3_main_0_ip2_ln2_txfclk"), + DEV_CLK(333, 36, "wiz16b8m4ct3_main_0_ip2_ln2_txmclk"), + DEV_CLK(333, 37, "wiz16b8m4ct3_main_0_ip2_ln3_refclk"), + DEV_CLK(333, 38, "wiz16b8m4ct3_main_0_ip2_ln3_rxclk"), + DEV_CLK(333, 39, "wiz16b8m4ct3_main_0_ip2_ln3_rxfclk"), + DEV_CLK(333, 41, "wiz16b8m4ct3_main_0_ip2_ln3_txfclk"), + DEV_CLK(333, 42, "wiz16b8m4ct3_main_0_ip2_ln3_txmclk"), + DEV_CLK(333, 43, "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), DEV_CLK(392, 0, "usart_programmable_clock_divider_out5"), DEV_CLK(392, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(395, 0, "usart_programmable_clock_divider_out8"), @@ -473,11 +616,36 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(398, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(398, 2, "postdiv3_16fft_main_1_hsdivout7_clk"), DEV_CLK(398, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(398, 4, "usb0_serdes_refclk_mux_out0"), + DEV_CLK(398, 5, "wiz16b8m4ct3_main_0_ip3_ln3_refclk"), + DEV_CLK(398, 7, "usb0_serdes_rxclk_mux_out0"), + DEV_CLK(398, 8, "wiz16b8m4ct3_main_0_ip3_ln3_rxclk"), + DEV_CLK(398, 10, "usb0_serdes_rxfclk_mux_out0"), + DEV_CLK(398, 11, "wiz16b8m4ct3_main_0_ip3_ln3_rxfclk"), + DEV_CLK(398, 14, "usb0_serdes_txfclk_mux_out0"), + DEV_CLK(398, 15, "wiz16b8m4ct3_main_0_ip3_ln3_txfclk"), + DEV_CLK(398, 17, "usb0_serdes_txmclk_mux_out0"), + DEV_CLK(398, 18, "wiz16b8m4ct3_main_0_ip3_ln3_txmclk"), DEV_CLK(398, 20, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(398, 21, "usb0_refclk_sel_out0"), DEV_CLK(398, 22, "gluelogic_hfosc0_clkout"), DEV_CLK(398, 23, "board_0_hfosc1_clk_out"), DEV_CLK(398, 28, "board_0_tck_out"), + DEV_CLK(404, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(404, 3, "board_0_serdes0_refclk_n_out"), + DEV_CLK(404, 4, "board_0_serdes0_refclk_p_out"), + DEV_CLK(404, 5, "hsdiv4_16fft_main_3_hsdivout4_clk"), + DEV_CLK(404, 6, "serdes0_core_refclk_out0"), + DEV_CLK(404, 7, "gluelogic_hfosc0_clkout"), + DEV_CLK(404, 8, "board_0_hfosc1_clk_out"), + DEV_CLK(404, 9, "hsdiv4_16fft_main_3_hsdivout4_clk"), + DEV_CLK(404, 10, "hsdiv4_16fft_main_2_hsdivout4_clk"), + DEV_CLK(404, 39, "pcie_g3x4_128_main_1_pcie_lane0_txclk"), + DEV_CLK(404, 45, "pcie_g3x4_128_main_1_pcie_lane1_txclk"), + DEV_CLK(404, 51, "pcie_g3x4_128_main_1_pcie_lane2_txclk"), + DEV_CLK(404, 57, "pcie_g3x4_128_main_1_pcie_lane3_txclk"), + DEV_CLK(404, 81, "usb3p0ss_16ffc_main_0_pipe_txclk"), + DEV_CLK(404, 129, "board_0_tck_out"), }; const struct ti_k3_clk_platdata j784s4_clk_platdata = { diff --git a/arch/arm/mach-k3/r5/j784s4/dev-data.c b/arch/arm/mach-k3/r5/j784s4/dev-data.c index 19901821225..2bb1a88ab3b 100644 --- a/arch/arm/mach-k3/r5/j784s4/dev-data.c +++ b/arch/arm/mach-k3/r5/j784s4/dev-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof . * - * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2026 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-dev.h" @@ -21,10 +21,11 @@ static struct ti_pd soc_pd_list[] = { [1] = PSC_PD(3, &soc_psc_list[1], NULL), [2] = PSC_PD(0, &soc_psc_list[2], NULL), [3] = PSC_PD(1, &soc_psc_list[2], &soc_pd_list[2]), - [4] = PSC_PD(14, &soc_psc_list[2], NULL), - [5] = PSC_PD(15, &soc_psc_list[2], &soc_pd_list[4]), - [6] = PSC_PD(16, &soc_psc_list[2], &soc_pd_list[4]), - [7] = PSC_PD(38, &soc_psc_list[2], NULL), + [4] = PSC_PD(5, &soc_psc_list[2], NULL), + [5] = PSC_PD(14, &soc_psc_list[2], NULL), + [6] = PSC_PD(15, &soc_psc_list[2], &soc_pd_list[5]), + [7] = PSC_PD(16, &soc_psc_list[2], &soc_pd_list[5]), + [8] = PSC_PD(38, &soc_psc_list[2], NULL), }; static struct ti_lpsc soc_lpsc_list[] = { @@ -44,13 +45,15 @@ static struct ti_lpsc soc_lpsc_list[] = { [13] = PSC_LPSC(20, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]), [14] = PSC_LPSC(23, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]), [15] = PSC_LPSC(25, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]), - [16] = PSC_LPSC(43, &soc_psc_list[2], &soc_pd_list[3], NULL), - [17] = PSC_LPSC(45, &soc_psc_list[2], &soc_pd_list[3], NULL), - [18] = PSC_LPSC(78, &soc_psc_list[2], &soc_pd_list[4], NULL), - [19] = PSC_LPSC(80, &soc_psc_list[2], &soc_pd_list[5], &soc_lpsc_list[18]), - [20] = PSC_LPSC(81, &soc_psc_list[2], &soc_pd_list[6], &soc_lpsc_list[18]), - [21] = PSC_LPSC(120, &soc_psc_list[2], &soc_pd_list[7], &soc_lpsc_list[22]), - [22] = PSC_LPSC(121, &soc_psc_list[2], &soc_pd_list[7], NULL), + [16] = PSC_LPSC(29, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]), + [17] = PSC_LPSC(43, &soc_psc_list[2], &soc_pd_list[3], NULL), + [18] = PSC_LPSC(45, &soc_psc_list[2], &soc_pd_list[3], NULL), + [19] = PSC_LPSC(64, &soc_psc_list[2], &soc_pd_list[4], NULL), + [20] = PSC_LPSC(78, &soc_psc_list[2], &soc_pd_list[5], NULL), + [21] = PSC_LPSC(80, &soc_psc_list[2], &soc_pd_list[6], &soc_lpsc_list[20]), + [22] = PSC_LPSC(81, &soc_psc_list[2], &soc_pd_list[7], &soc_lpsc_list[20]), + [23] = PSC_LPSC(120, &soc_psc_list[2], &soc_pd_list[8], &soc_lpsc_list[24]), + [24] = PSC_LPSC(121, &soc_psc_list[2], &soc_pd_list[8], NULL), }; static struct ti_dev soc_dev_list[] = { @@ -78,14 +81,16 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(398, &soc_lpsc_list[13]), PSC_DEV(141, &soc_lpsc_list[14]), PSC_DEV(140, &soc_lpsc_list[15]), - PSC_DEV(146, &soc_lpsc_list[16]), - PSC_DEV(392, &soc_lpsc_list[17]), - PSC_DEV(395, &soc_lpsc_list[17]), - PSC_DEV(198, &soc_lpsc_list[18]), - PSC_DEV(202, &soc_lpsc_list[19]), - PSC_DEV(203, &soc_lpsc_list[20]), - PSC_DEV(133, &soc_lpsc_list[21]), - PSC_DEV(193, &soc_lpsc_list[22]), + PSC_DEV(333, &soc_lpsc_list[16]), + PSC_DEV(146, &soc_lpsc_list[17]), + PSC_DEV(392, &soc_lpsc_list[18]), + PSC_DEV(395, &soc_lpsc_list[18]), + PSC_DEV(404, &soc_lpsc_list[19]), + PSC_DEV(198, &soc_lpsc_list[20]), + PSC_DEV(202, &soc_lpsc_list[21]), + PSC_DEV(203, &soc_lpsc_list[22]), + PSC_DEV(133, &soc_lpsc_list[23]), + PSC_DEV(193, &soc_lpsc_list[24]), }; const struct ti_k3_pd_platdata j784s4_pd_platdata = { From 2a21f48771a2f4f0f05d9c76517212ffb94f3c35 Mon Sep 17 00:00:00 2001 From: Hrushikesh Salunke Date: Mon, 16 Feb 2026 15:58:30 +0530 Subject: [PATCH 02/10] phy: cadence: Add config to enable Cadence Torrent PHY at SPL stage Add SPL_PHY_CADENCE_TORRENT configuration option to enable the Cadence Torrent PHY driver in SPL stage. This is required for PCIe boot support where SERDES configuration must be done early in the boot sequence before loading the bootloader image over PCIe. Signed-off-by: Hrushikesh Salunke Signed-off-by: Siddharth Vadapalli --- drivers/phy/cadence/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig index 549ddbf5046..8c0ab80fbbc 100644 --- a/drivers/phy/cadence/Kconfig +++ b/drivers/phy/cadence/Kconfig @@ -9,3 +9,10 @@ config PHY_CADENCE_TORRENT depends on DM_RESET help Enable this to support the Cadence Torrent PHY driver + +config SPL_PHY_CADENCE_TORRENT + bool "Cadence Torrent PHY Driver" + depends on SPL_DM_RESET + help + Enable this to support the Cadence Torrent PHY driver at SPL + stage. From 35e1083fb930ba1fa3a3c5cd139bf8285043c191 Mon Sep 17 00:00:00 2001 From: Hrushikesh Salunke Date: Mon, 16 Feb 2026 15:58:31 +0530 Subject: [PATCH 03/10] phy: ti: Add config to enable J721E WIZ SERDES wrapper at SPL stage Add SPL_PHY_J721E_WIZ configuration option to enable the WIZ SERDES wrapper driver in SPL stage. This is required for PCIe boot support where SERDES configuration must be done early in the boot sequence before loading the bootloader image over PCIe. Signed-off-by: Hrushikesh Salunke Signed-off-by: Siddharth Vadapalli --- drivers/phy/ti/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/phy/ti/Kconfig b/drivers/phy/ti/Kconfig index 111085f235d..df750b26d66 100644 --- a/drivers/phy/ti/Kconfig +++ b/drivers/phy/ti/Kconfig @@ -7,3 +7,13 @@ config PHY_J721E_WIZ signals to the SERDES (Sierra/Torrent). This driver configures three clock selects (pll0, pll1, dig) and resets for each of the lanes. + +config SPL_PHY_J721E_WIZ + bool "TI J721E WIZ (SERDES Wrapper) support" + depends on ARCH_K3 + help + This option enables support for WIZ module present in TI's J721E + SoC at SPL stage. WIZ is a serdes wrapper used to configure some + of the input signals to the SERDES (Sierra/Torrent). This driver + configures three clock selects (pll0, pll1, dig) and resets for + each of the lanes. From d83eefab8cfd58b8e4259734b2e19b30a8659461 Mon Sep 17 00:00:00 2001 From: Hrushikesh Salunke Date: Mon, 16 Feb 2026 15:58:32 +0530 Subject: [PATCH 04/10] configs: j784s4_evm_r5_defconfig: Enable configs for PCIe boot J784S4 SoC has two instances of PCIe, namely PCIe0 and PCIe1. The PCIe1 instance is used for PCIe endpoint boot. Enable the configs required for PCIe boot on the J784S4 platform. Additionally, enable configs for J721E WIZ SERDES wrapper, Cadence Torrent PHY, and MMIO multiplexer. These are required to configure the SERDES lanes at the R5 SPL stage for PCIe endpoint operation. Signed-off-by: Hrushikesh Salunke Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar --- configs/j784s4_evm_r5_defconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index 25ab6f17d17..4462e7530e4 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -50,9 +50,16 @@ CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_PCI_ENDPOINT=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_PCI_DFU=y +CONFIG_SPL_PCI_DFU_SPL_LOAD_FIT_ADDRESS=0x80800000 +CONFIG_SPL_PCI_DFU_BAR_SIZE=0x400000 +CONFIG_SPL_PCI_DFU_VENDOR_ID=0x104c +CONFIG_SPL_PCI_DFU_DEVICE_ID=0xb012 +CONFIG_SPL_PCI_DFU_BOOT_PHASE="tiboot3.bin" # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y @@ -120,6 +127,12 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_S28HX_T=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MT35XU=y +CONFIG_MULTIPLEXER=y +CONFIG_SPL_MUX_MMIO=y +CONFIG_PCIE_CDNS_TI_EP=y +CONFIG_SPL_PHY=y +CONFIG_SPL_PHY_CADENCE_TORRENT=y +CONFIG_SPL_PHY_J721E_WIZ=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y From 3c28bf7719130158c2acd86c45df95262b6b8fa1 Mon Sep 17 00:00:00 2001 From: Hrushikesh Salunke Date: Mon, 16 Feb 2026 15:58:33 +0530 Subject: [PATCH 05/10] configs: j784s4_evm_a72_defconfig: Enable configs for PCIe boot J784S4 SoC has two instances of PCIe, namely PCIe0 and PCIe1. The PCIe1 instance is used for PCIe endpoint boot. Enable the configs required for PCIe boot on the J784S4 platform. Signed-off-by: Hrushikesh Salunke Signed-off-by: Siddharth Vadapalli --- configs/j784s4_evm_a72_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig index f440b18c6fc..7ca5e88276e 100644 --- a/configs/j784s4_evm_a72_defconfig +++ b/configs/j784s4_evm_a72_defconfig @@ -44,9 +44,16 @@ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_PCI_ENDPOINT=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_PCI_DFU=y +CONFIG_SPL_PCI_DFU_SPL_LOAD_FIT_ADDRESS=0x81000000 +CONFIG_SPL_PCI_DFU_BAR_SIZE=0x400000 +CONFIG_SPL_PCI_DFU_VENDOR_ID=0x104c +CONFIG_SPL_PCI_DFU_DEVICE_ID=0xb012 +CONFIG_SPL_PCI_DFU_BOOT_PHASE="tispl.bin" # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y From 014d9c5ac348cd7d11aa991df466b47428487c86 Mon Sep 17 00:00:00 2001 From: Hrushikesh Salunke Date: Mon, 16 Feb 2026 15:58:34 +0530 Subject: [PATCH 06/10] configs: am69_sk_r5_defconfig: Disable PCIe boot configs AM69 SK does not contain PCIe Boot in the list of supported Boot Modes. Hence, disable PCIe Boot related configurations that are not applicable. Signed-off-by: Hrushikesh Salunke Signed-off-by: Siddharth Vadapalli --- configs/am69_sk_r5_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/configs/am69_sk_r5_defconfig b/configs/am69_sk_r5_defconfig index 2186b9a0490..166f774aade 100644 --- a/configs/am69_sk_r5_defconfig +++ b/configs/am69_sk_r5_defconfig @@ -5,6 +5,12 @@ CONFIG_ARCH_K3=y CONFIG_SOC_K3_J784S4=y CONFIG_TARGET_J784S4_R5_EVM=y +CONFIG_MULTIPLEXER=n +CONFIG_SPL_MUX_MMIO=n +CONFIG_SPL_PCI_ENDPOINT=n +CONFIG_SPL_PCI_DFU=n +CONFIG_SPL_PHY=n + CONFIG_DEFAULT_DEVICE_TREE="k3-am69-r5-sk" CONFIG_SPL_OF_LIST="k3-am69-r5-sk" CONFIG_OF_LIST="k3-am69-r5-sk" From af3800c83dc216e8d3e951cfced7c7c27ee88530 Mon Sep 17 00:00:00 2001 From: Hrushikesh Salunke Date: Mon, 16 Feb 2026 15:58:35 +0530 Subject: [PATCH 07/10] configs: am69_sk_a72_defconfig: Disable PCIe boot configs AM69 SK does not contain PCIe Boot in the list of supported Boot Modes. Hence, disable PCIe Boot related configurations that are not applicable. Signed-off-by: Hrushikesh Salunke Signed-off-by: Siddharth Vadapalli --- configs/am69_sk_a72_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/am69_sk_a72_defconfig b/configs/am69_sk_a72_defconfig index 746b36a34ed..cf2881258e1 100644 --- a/configs/am69_sk_a72_defconfig +++ b/configs/am69_sk_a72_defconfig @@ -9,6 +9,9 @@ CONFIG_CMD_UFS=n CONFIG_UFS=n CONFIG_UFS_CADENCE=n CONFIG_UFS_TI_J721E=n +CONFIG_PCI_ENDPOINT=n +CONFIG_SPL_PCI_ENDPOINT=n +CONFIG_SPL_PCI_DFU=n CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am69-sk" CONFIG_OF_LIST="ti/k3-am69-sk" From 2abd957503eb423cc30535e6e20c2b113653f5a3 Mon Sep 17 00:00:00 2001 From: Hrushikesh Salunke Date: Mon, 16 Feb 2026 15:58:36 +0530 Subject: [PATCH 08/10] configs: j742s2_evm_r5_defconfig: Disable PCIe boot configs Although the J742S2 EVM supports PCIe boot in Hardware, since it is not enabled yet in Software, disable PCIe boot related configurations that are not applicable. Signed-off-by: Hrushikesh Salunke Signed-off-by: Siddharth Vadapalli --- configs/j742s2_evm_r5_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/configs/j742s2_evm_r5_defconfig b/configs/j742s2_evm_r5_defconfig index 2be6318df76..036954b4085 100644 --- a/configs/j742s2_evm_r5_defconfig +++ b/configs/j742s2_evm_r5_defconfig @@ -5,5 +5,11 @@ CONFIG_ARCH_K3=y CONFIG_SOC_K3_J784S4=y CONFIG_TARGET_J742S2_R5_EVM=y +CONFIG_SPL_PCI_ENDPOINT=n +CONFIG_SPL_PCI_DFU=n +CONFIG_MULTIPLEXER=n +CONFIG_SPL_MUX_MMIO=n +CONFIG_SPL_PHY=n + CONFIG_DEFAULT_DEVICE_TREE="k3-j742s2-r5-evm" CONFIG_SPL_OF_LIST="k3-j742s2-r5-evm" From 078200f1ee1857d5a1be0c53313e9e4e6ce2a4a3 Mon Sep 17 00:00:00 2001 From: Hrushikesh Salunke Date: Mon, 16 Feb 2026 15:58:37 +0530 Subject: [PATCH 09/10] configs: j742s2_evm_a72_defconfig: Disable PCIe boot configs Although the J742S2 EVM supports PCIe boot in Hardware, since it is not enabled yet in Software, disable PCIe boot related configurations that are not applicable. Signed-off-by: Hrushikesh Salunke Signed-off-by: Siddharth Vadapalli --- configs/j742s2_evm_a72_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configs/j742s2_evm_a72_defconfig b/configs/j742s2_evm_a72_defconfig index e534ce4c2e3..8263ab0bc4a 100644 --- a/configs/j742s2_evm_a72_defconfig +++ b/configs/j742s2_evm_a72_defconfig @@ -5,5 +5,9 @@ CONFIG_ARCH_K3=y CONFIG_SOC_K3_J784S4=y CONFIG_TARGET_J742S2_A72_EVM=y +CONFIG_PCI_ENDPOINT=n +CONFIG_SPL_PCI_ENDPOINT=n +CONFIG_SPL_PCI_DFU=n + CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j742s2-evm" CONFIG_SPL_OF_LIST="ti/k3-j742s2-evm" From 6230a595a733e381ecdbe35199d255f3d5801955 Mon Sep 17 00:00:00 2001 From: Hrushikesh Salunke Date: Mon, 16 Feb 2026 15:58:38 +0530 Subject: [PATCH 10/10] docs: board: ti: j784s4_evm: Add PCIe boot documentation Add PCIe boot documentation for J784S4-EVM including boot mode switch settings, hardware setup requirements, endpoint configuration details and step-by-step boot procedure. Signed-off-by: Hrushikesh Salunke [s-vadapalli@ti.com: simplified and documented the pcie_boot_util program] Co-developed-by: Siddharth Vadapalli Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar --- doc/board/ti/j784s4_evm.rst | 305 ++++++++++++++++++++++++++++++++++++ 1 file changed, 305 insertions(+) diff --git a/doc/board/ti/j784s4_evm.rst b/doc/board/ti/j784s4_evm.rst index d858dc7cdbb..fb767bedbf6 100644 --- a/doc/board/ti/j784s4_evm.rst +++ b/doc/board/ti/j784s4_evm.rst @@ -299,6 +299,10 @@ http://www.ti.com/lit/zip/spruj52 under the `Boot Mode Pins` section. - 00000000 - 01110000 + * - PCIe + - 10001000 + - 01010000 + For SW7 and SW11, the switch state in the "ON" position = 1. Boot Mode Pins for AM69-SK @@ -330,6 +334,307 @@ section. For SW2, the switch state in the "ON" position = 1. +PCIe Boot +--------- + +The J784S4 SoC supports booting over PCIe, allowing the device to function +as a PCIe endpoint and receive boot loader images from a PCIe Root Complex. +The PCIe1 instance of PCIe is configured by Boot ROM for Endpoint Mode of +operation. Hence, the PCIe Connector on the EVM corresponding to PCIe1 +should be utilized for PCIe Boot. + +Hardware Setup +^^^^^^^^^^^^^^ + +To boot the J784S4 EVM via PCIe, the following hardware setup is required: + +1. Configure the boot mode switches on J784S4-EVM for PCIe boot: + + .. code-block:: text + + SW7: 01010000 + SW11: 10001000 + +2. Connect the J784S4-EVM (endpoint) to a PCIe Root Complex (e.g., x86 host) + using a PCIe cable. Both boards should be powered off before making the + connection. + +Endpoint Configuration +^^^^^^^^^^^^^^^^^^^^^^ + +The following configuration options are enabled by default in +``j784s4_evm_r5_defconfig`` and ``j784s4_evm_a72_defconfig``: + +- ``CONFIG_SPL_PCI_DFU_BAR_SIZE``: Size of the PCIe BAR for DFU/boot image download +- ``CONFIG_SPL_PCI_DFU_VENDOR_ID``: PCIe vendor ID advertised by the endpoint +- ``CONFIG_SPL_PCI_DFU_DEVICE_ID``: PCIe device ID advertised by the endpoint +- ``CONFIG_SPL_PCI_DFU_MAGIC_WORD``: Magic word written by Root Complex to signal image transfer completion +- ``CONFIG_SPL_PCI_DFU_BOOT_PHASE``: Current boot phase indicator for Root Complex + +By default, PCIe Root Complex mode is enabled in the device tree. For PCIe Boot, +build the Bootloaders with the following content added to k3-j784s4-evm-u-boot.dtsi: + +.. code-block:: devicetree + + &serdes0 { + /delete-property/ serdes0_usb_link; + }; + + &serdes_refclk { + bootph-all; + }; + + &serdes0_pcie1_link { + bootph-all; + }; + + &serdes_ln_ctrl { + bootph-all; + }; + + &pcie1_ctrl { + bootph-all; + }; + + &pcie1_rc { + status = "disabled"; + }; + + &cbass_main { + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j784s4-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 333 0>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys = <&serdes0_pcie1_link>; + phy-names = "pcie-phy"; + bootph-all; + }; + }; + +PCIe Boot Procedure +^^^^^^^^^^^^^^^^^^^ + +The following steps describe the process of booting J784S4-EVM over PCIe: + +1. Compile the sample host program (provided after this section): + + .. prompt:: bash + + gcc -o pcie_boot_util pcie_boot_util.c + +2. Power on the J784S4-EVM (endpoint) after configuring boot mode switches + for PCIe Boot. + +3. Copy the compiled sample host program (pcie_boot_util) and the bootloader + images to the Root Complex. Check PCIe enumeration on Root Complex to ensure + that the J784S4 EVM shows up as the PCIe Endpoint: + + .. prompt:: bash + + lspci + + The endpoint will appear as a RAM device or with multiple functions: + + .. code-block:: text + + 0000:00:00.0 PCI bridge: Texas Instruments Device b012 + 0000:01:00.0 RAM memory: Texas Instruments Device b012 + 0000:01:00.1 Non-VGA unclassified device: Texas Instruments Device 0100 + 0000:01:00.2 Non-VGA unclassified device: Texas Instruments Device 0100 + +4. Copy ``tiboot3.bin`` to the endpoint. Use ``lspci -vv`` to identify the BAR + address: + + .. prompt:: bash + + sudo ./pcie_boot_util 0x4007100000 tiboot3.bin + + The sample program automatically writes the image start address to + ``0x41CF3FE0`` and the magic word ``0xB17CEAD9`` to ``0x41CF3FE4``. + +5. After ``tiboot3.bin`` is processed, the PCIe link will go down briefly. + Remove the PCIe device and rescan the bus: + + .. prompt:: bash + + echo 1 > /sys/bus/pci/devices/0000\:01\:00.0/remove + echo 1 > /sys/bus/pci/devices/0000\:00\:00.0/rescan + lspci + + The enumeration will change to something similar: + + .. code-block:: text + + 0000:00:00.0 PCI bridge: Texas Instruments Device b012 + 0000:01:00.0 RAM memory: Texas Instruments Device b010 (rev dc) + + .. note:: + + When the Root-Complex enumerates the PCIe Endpoint after a 'remove-rescan' sequence, + it is possible that the 'BAR' appears 'disabled'. If so, writing to the BAR via the + 'pcie_boot_util' to transfer the bootloader image will have no effect. In such cases, + run 'setpci -s 0000:01:00.0 COMMAND=0x02' on the Root-Complex after enumeration + (with appropriate DOMAIN:BUS:DEVICE.FUNCTION corresponding to the Endpoint) to enable + the BAR. + +6. Copy ``tispl.bin`` to the new BAR address (use ``lspci -vv`` to find): + + .. prompt:: bash + + sudo ./pcie_boot_util 0x4000400000 tispl.bin + +7. After ``tispl.bin`` is processed, the PCIe link will go down again. Remove + and rescan the PCIe device: + + .. prompt:: bash + + echo 1 > /sys/bus/pci/devices/0000\:01\:00.0/remove + echo 1 > /sys/bus/pci/devices/0000\:00\:00.0/rescan + +8. Copy ``u-boot.img``: + + .. prompt:: bash + + sudo ./pcie_boot_util 0x4000400000 u-boot.img + +9. After ``u-boot.img`` is successfully loaded, the boot process is complete + and endpoint should boot till U-Boot prompt. + +.. note:: + + During the boot process, "PCIe LINK DOWN" messages might appear in kernel + logs. This is expected as the endpoint resets and re-initializes the PCIe + link after processing each boot stage. + +Sample Host Program +^^^^^^^^^^^^^^^^^^^ + +The following C program can be used on the Root Complex to copy bootloader images +to the J784S4 endpoint: + +.. code-block:: c + + #include + #include + #include + #include + #include + #include + + #define MAP_SIZE 0x400000 + + /* + * bootloader_file: Path to the bootloader image (tiboot3.bin, tispl.bin and u-boot.img) + * bootloader_mem: Memory allocated in RAM for reading the bootloader image file + * bar_address: Address of BAR to which bootloader image will be written + * bar_map_base: Mapping of the BAR Base Address for the program + * load_address: Address in BAR region where bootloader is being transferred + * transfer_completion_offset: Offset in BAR region to write to notify completion of transfer + * fd_mem: File descriptor for opening /dev/mem + * fptr: File pointer for bootloader image in filesystem + * magic_word: Magic word to notify completion of tiboot3.bin transfer to Boot ROM + * use_magic_word: Flag to indicate if Magic Word has to be written + * file_size: Size of bootloader image + * i: Iterator used during bootloader image transfer + */ + int main(int argc, char *argv[]) + { + off_t bar_address, load_address, transfer_completion_offset; + unsigned char *bootloader_mem; + const char *bootloader_file; + int fd_mem, i, use_magic_word; + unsigned int magic_word; + void *bar_map_base; + long file_size; + FILE * fptr; + + if (argc != 3) { + printf("Usage: %s \n", argv[0]); + return 0; + } + + bar_address = strtoul(argv[1], NULL, 16); + bootloader_file = argv[2]; + + printf("Bootloader File: %s\n", bootloader_file); + printf("BAR Address: 0x%lx\n", bar_address); + + if(!strcmp(bootloader_file,"tiboot3.bin")) { + transfer_completion_offset = 0xF3FE0; + load_address = 0x41C00000; + magic_word = 0xB17CEAD9; + use_magic_word = 1; + } else { + transfer_completion_offset = MAP_SIZE - 0x4; + load_address = 0xDEADBEEF; + use_magic_word = 0; + } + + fd_mem = open("/dev/mem", O_RDWR | O_SYNC); + if(fd_mem == -1) { + printf("failed to open /dev/mem\n"); + return -1; + } + + bar_map_base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd_mem, bar_address); + if(bar_map_base == (void *)-1) { + printf("failed to map BAR\n"); + return -1; + } + + fptr = fopen(bootloader_file, "rb"); + if (!fptr) { + printf("failed to read bootloader file\n"); + return -1; + } + + fseek(fptr, 0, SEEK_END); + file_size = ftell(fptr); + rewind(fptr); + + bootloader_mem = (unsigned char *)malloc(sizeof(char) * file_size); + if(!bootloader_mem) { + printf("failed to allocate local memory for bootloader file\n"); + return -1; + } + + if (fread(bootloader_mem, 1, file_size, fptr) != file_size) { + printf("failed to read bootloader file into local memory\n"); + return -1; + } + + for(i = 0; i < file_size; i++) { + *((char *)(bar_map_base) + i) = bootloader_mem[i]; + } + + *(unsigned int *)(bar_map_base + transfer_completion_offset) = (unsigned int)(load_address); + + if(use_magic_word) { + *(unsigned int *)(bar_map_base + transfer_completion_offset + 4) = magic_word; + printf("Magic word written for Boot ROM\n"); + } + + printf("Transferred %s to Endpoint\n", bootloader_file); + return 0; + } + +This program copies the boot image to the PCIe endpoint's memory region and +writes the necessary control words to signal image transfer completion. + Debugging U-Boot ----------------