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armv8/ls1043a: Enable secondary cores

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After the secondary cores enter U-Boot, use CONFIG_ARMV8_MULTIENTRY to
make secondary cores excute in spin loop.

Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Hou Zhiqiang 2015-10-26 19:47:57 +08:00 committed by York Sun
parent c7ca8b07fc
commit 831c068fcf
3 changed files with 18 additions and 0 deletions
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1
arch/arm/Kconfig
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@ -630,6 +630,7 @@ config TARGET_LS1021ATWR
config TARGET_LS1043ARDB config TARGET_LS1043ARDB
bool "Support ls1043ardb" bool "Support ls1043ardb"
select ARM64 select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL select SUPPORT_SPL
help help
Support for Freescale LS1043ARDB platform. Support for Freescale LS1043ARDB platform.

14
arch/arm/cpu/armv8/fsl-layerscape/mp.c
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@ -25,7 +25,11 @@ phys_addr_t determine_mp_bootpg(void)
int fsl_layerscape_wake_seconday_cores(void) int fsl_layerscape_wake_seconday_cores(void)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
#ifdef CONFIG_FSL_LSCH3
struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
#elif defined(CONFIG_FSL_LSCH2)
struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
#endif
u32 cores, cpu_up_mask = 1; u32 cores, cpu_up_mask = 1;
int i, timeout = 10; int i, timeout = 10;
u64 *table = get_spin_tbl_addr(); u64 *table = get_spin_tbl_addr();
@ -48,13 +52,23 @@ int fsl_layerscape_wake_seconday_cores(void)
printf("Waking secondary cores to start from %lx\n", gd->relocaddr); printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
#ifdef CONFIG_FSL_LSCH3
gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32)); gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr); gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
gur_out32(&gur->scratchrw[6], 1); gur_out32(&gur->scratchrw[6], 1);
asm volatile("dsb st" : : : "memory"); asm volatile("dsb st" : : : "memory");
rst->brrl = cores; rst->brrl = cores;
asm volatile("dsb st" : : : "memory"); asm volatile("dsb st" : : : "memory");
#elif defined(CONFIG_FSL_LSCH2)
scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
asm volatile("dsb st" : : : "memory");
gur_out32(&gur->brrl, cores);
asm volatile("dsb st" : : : "memory");
/* Bootup online cores */
scfg_out32(&scfg->corebcr, cores);
#endif
/* This is needed as a precautionary measure. /* This is needed as a precautionary measure.
* If some code before this has accidentally released the secondary * If some code before this has accidentally released the secondary
* cores then the pre-bootloader code will trap them in a "wfe" unless * cores then the pre-bootloader code will trap them in a "wfe" unless

3
include/configs/ls1043a_common.h
View File

@ -11,6 +11,7 @@
#define CONFIG_FSL_LAYERSCAPE #define CONFIG_FSL_LAYERSCAPE
#define CONFIG_FSL_LSCH2 #define CONFIG_FSL_LSCH2
#define CONFIG_LS1043A #define CONFIG_LS1043A
#define CONFIG_MP
#define CONFIG_SYS_FSL_CLK #define CONFIG_SYS_FSL_CLK
#define CONFIG_GICV2 #define CONFIG_GICV2
@ -44,6 +45,8 @@
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CPU_RELEASE_ADDR secondary_boot_func
/* Generic Timer Definitions */ /* Generic Timer Definitions */
#define COUNTER_FREQUENCY 25000000 /* 25MHz */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */